TEMPLATE static u32 FASTCALL OP_LSL_0(const u32 i) { cpu->R[REG_NUM(i, 0)] = cpu->R[REG_NUM(i, 3)]; cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0; return 1; }
TEMPLATE static uint32_t FASTCALL OP_LSL_0(uint32_t i) { cpu->R[REG_NUM(i, 0)] = cpu->R[REG_NUM(i, 3)]; cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); cpu->CPSR.bits.Z = !cpu->R[REG_NUM(i, 0)]; return 1; }
static void enable_bigsur_l2irq(unsigned int irq) { unsigned char mask; unsigned char bit = 1 << ((irq-BIGSUR_2NDLVL_IRQ_LOW)%8); unsigned int mask_port = imr_base - REG_NUM(irq)*imr_offset; if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) { pr_debug("Enable L2 IRQ %d\n", irq); DIPRINTK(2,"enable_bigsur_l2irq: IMR=0x%08x mask=0x%x\n", mask_port, bit); /* Enable L2 IRQ - clear mask bit */ mask = inb(mask_port) & ~bit; outb(mask, mask_port); return; } pr_debug("enable_bigsur_l2irq: Invalid IRQ %d\n", irq); }
// LSL //----------------------------------------------------------------------------- TEMPLATE static u32 FASTCALL OP_LSL_0(const u32 i) { cpu->R[REG_NUM(i, 0)] = cpu->R[REG_NUM(i, 3)]; cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0; return 1; } TEMPLATE static u32 FASTCALL OP_LSL(const u32 i) { u32 v = (i>>6) & 0x1F; cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 3)], 32-v); cpu->R[REG_NUM(i, 0)] = (cpu->R[REG_NUM(i, 3)] << v); cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0; return 1; } TEMPLATE static u32 FASTCALL OP_LSL_REG(const u32 i) { u32 v = cpu->R[REG_NUM(i, 3)] & 0xFF; if(v == 0) { cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;