static void ehci_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script ehci_hc_init[] = { /* Controller init */ REG_SCRIPT_NEXT(ehci_init_script), /* Enable clock gating */ REG_SCRIPT_NEXT(ehci_clock_gating_script), /* * Disable ports if requested */ /* Open per-port disable control override */ REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN), REG_PCI_WRITE8(EHCI_USB2PDO, config->usb2_port_disable_mask), /* Close per-port disable control override */ REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0), REG_SCRIPT_END }; /* Don't reset controller in S3 resume path */ if (!acpi_is_wakeup_s3()) reg_script_run_on_dev(dev, ehci_hc_reset); /* Disable controller if ports are routed to XHCI */ if (config->usb_route_to_xhci) { /* Disable controller */ reg_script_run_on_dev(dev, ehci_disable_script); /* Hide device with southcluster function */ dev->enabled = 0; southcluster_enable_dev(dev); } else { /* Initialize EHCI controller */ reg_script_run_on_dev(dev, ehci_hc_init); } /* Setup USB2 PHY based on board config */ usb2_phy_init(dev); }
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x3310, 0x0000002f), REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3f02, ~0x0000000f, 0), /* Enable PCIe Releaxed Order */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2314, (1 << 31) | (1 << 7)), REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)), /* Setup SERIRQ, enable continuous mode */ REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), #if !CONFIG_SERIRQ_CONTINUOUS_MODE REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0), #endif REG_SCRIPT_END }; /* Magic register settings for power management */ static const struct reg_script pch_pm_init_script[] = { REG_PCI_WRITE8(0xa9, 0x46), REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x232c, ~1, 0), REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1100, 0x0000c13f), REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x2320, ~0x60, 0x10), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3314, 0x00012fff), REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3318, ~0x000f0330, 0x0dcf0400), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3324, 0x04000000), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3368, 0x00041400), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3388, 0x3f8ddbff), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33ac, 0x00007001), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b0, 0x00181900), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33c0, 0x00060A00), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33d0, 0x06200840), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a28, 0x01010101), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a2c, 0x040c0404), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a9c, 0x9000000a),
* GNU General Public License for more details. */ #include <arch/io.h> #include <device/pci_def.h> #include <device/early_smbus.h> #include <intelblocks/smbus.h> #include <reg_script.h> #include <soc/pci_devs.h> #include "smbuslib.h" static const struct reg_script smbus_init_script[] = { /* Set SMBus I/O base address */ REG_PCI_WRITE32(PCI_BASE_ADDRESS_4, SMBUS_IO_BASE), /* Set SMBus enable */ REG_PCI_WRITE8(HOSTC, HST_EN), /* Enable I/O access */ REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO), /* Disable interrupts */ REG_IO_WRITE8(SMBUS_IO_BASE + SMBHSTCTL, 0), /* Clear errors */ REG_IO_WRITE8(SMBUS_IO_BASE + SMBHSTSTAT, 0xff), /* Indicate the end of this array by REG_SCRIPT_END */ REG_SCRIPT_END, }; u16 smbus_read_word(u32 smbus_dev, u8 addr, u8 offset) { return smbus_read16(SMBUS_IO_BASE, addr, offset); }
#include <reg_script.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/rcba.h> #include <soc/romstage.h> #include <soc/smbus.h> #include <soc/intel/broadwell/chip.h> const struct reg_script pch_early_init_script[] = { /* Setup southbridge BARs */ REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1), REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1), REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN), REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1), REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN), /* Set COM1/COM2 decode range */ REG_PCI_WRITE16(LPC_IO_DEC, 0x0010), /* Enable legacy decode ranges */ REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN), /* Enable IOAPIC */ REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100), /* Read back for posted write */ REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC), /* Set HPET address and enable it */