static void process_channel_reply( struct dce_i2c_hw *dce_i2c_hw, struct i2c_payload *reply) { uint32_t length = reply->length; uint8_t *buffer = reply->data; REG_SET_3(DC_I2C_DATA, 0, DC_I2C_INDEX, dce_i2c_hw->buffer_used_write, DC_I2C_DATA_RW, 1, DC_I2C_INDEX_WRITE, 1); while (length) { /* after reading the status, * if the I2C operation executed successfully * (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller * should read data bytes from I2C circular data buffer */ uint32_t i2c_data; REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data); *buffer++ = i2c_data; --length; } }
static void process_channel_reply( struct i2c_engine *engine, struct i2c_reply_transaction_data *reply) { uint32_t length = reply->length; uint8_t *buffer = reply->data; struct i2c_hw_engine_dce110 *hw_engine = FROM_I2C_ENGINE(engine); REG_SET_3(DC_I2C_DATA, 0, DC_I2C_INDEX, hw_engine->buffer_used_write, DC_I2C_DATA_RW, 1, DC_I2C_INDEX_WRITE, 1); while (length) { /* after reading the status, * if the I2C operation executed successfully * (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller * should read data bytes from I2C circular data buffer */ uint32_t i2c_data; REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data); *buffer++ = i2c_data; --length; } }
static void program_multi_taps_filter( struct dce_transform *xfm_dce, int taps, const uint16_t *coeffs, enum ram_filter_type filter_type) { int phase, pair; int array_idx = 0; int taps_pairs = (taps + 1) / 2; int phases_to_program = SCL_PHASES / 2 + 1; uint32_t power_ctl = 0; if (!coeffs) return; /*We need to disable power gating on coeff memory to do programming*/ if (REG(DCFE_MEM_PWR_CTRL)) { power_ctl = REG_READ(DCFE_MEM_PWR_CTRL); REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1); REG_WAIT(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, 0, 1, 10); } for (phase = 0; phase < phases_to_program; phase++) { /*we always program N/2 + 1 phases, total phases N, but N/2-1 are just mirror phase 0 is unique and phase N/2 is unique if N is even*/ for (pair = 0; pair < taps_pairs; pair++) { uint16_t odd_coeff = 0; uint16_t even_coeff = coeffs[array_idx]; REG_SET_3(SCL_COEF_RAM_SELECT, 0, SCL_C_RAM_FILTER_TYPE, filter_type, SCL_C_RAM_PHASE, phase, SCL_C_RAM_TAP_PAIR_IDX, pair); if (taps % 2 && pair == taps_pairs - 1) array_idx++; else { odd_coeff = coeffs[array_idx + 1]; array_idx += 2; } REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0, SCL_C_RAM_EVEN_TAP_COEF_EN, 1, SCL_C_RAM_EVEN_TAP_COEF, even_coeff, SCL_C_RAM_ODD_TAP_COEF_EN, 1, SCL_C_RAM_ODD_TAP_COEF, odd_coeff); } } /*We need to restore power gating on coeff memory to initial state*/ if (REG(DCFE_MEM_PWR_CTRL)) REG_WRITE(DCFE_MEM_PWR_CTRL, power_ctl); }
void hubp1_program_deadline( struct hubp *hubp, struct _vcs_dpi_display_dlg_regs_st *dlg_attr, struct _vcs_dpi_display_ttu_regs_st *ttu_attr) { struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); /* DLG - Per hubp */ REG_SET_2(BLANK_OFFSET_0, 0, REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); REG_SET(BLANK_OFFSET_1, 0, MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); REG_SET(DST_DIMENSIONS, 0, REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); REG_SET_2(DST_AFTER_SCALER, 0, REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); REG_SET(REF_FREQ_TO_PIX_FREQ, 0, REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); /* DLG - Per luma/chroma */ REG_SET(VBLANK_PARAMETERS_1, 0, REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); if (REG(NOM_PARAMETERS_0)) REG_SET(NOM_PARAMETERS_0, 0, DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); if (REG(NOM_PARAMETERS_1)) REG_SET(NOM_PARAMETERS_1, 0, REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); REG_SET(NOM_PARAMETERS_4, 0, DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); REG_SET(NOM_PARAMETERS_5, 0, REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); REG_SET_2(PER_LINE_DELIVERY, 0, REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); REG_SET(VBLANK_PARAMETERS_2, 0, REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); if (REG(NOM_PARAMETERS_2)) REG_SET(NOM_PARAMETERS_2, 0, DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); if (REG(NOM_PARAMETERS_3)) REG_SET(NOM_PARAMETERS_3, 0, REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); REG_SET(NOM_PARAMETERS_6, 0, DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); REG_SET(NOM_PARAMETERS_7, 0, REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); /* TTU - per hubp */ REG_SET_2(DCN_TTU_QOS_WM, 0, QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); /* TTU - per luma/chroma */ /* Assumed surf0 is luma and 1 is chroma */ REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); }
void dpp1_cnv_setup ( struct dpp *dpp_base, enum surface_pixel_format input_format, enum expansion_mode mode) { uint32_t pixel_format; uint32_t alpha_en; enum pixel_format_description fmt ; enum dc_color_space color_space; enum dcn10_input_csc_select select; bool is_float; struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); bool force_disable_cursor = false; dpp1_setup_format_flags(input_format, &fmt); alpha_en = 1; pixel_format = 0; color_space = COLOR_SPACE_SRGB; select = INPUT_CSC_SELECT_BYPASS; is_float = false; switch (fmt) { case PIXEL_FORMAT_FIXED: case PIXEL_FORMAT_FIXED16: /*when output is float then FORMAT_CONTROL__OUTPUT_FP=1*/ REG_SET_3(FORMAT_CONTROL, 0, CNVC_BYPASS, 0, FORMAT_EXPANSION_MODE, mode, OUTPUT_FP, 0); break; case PIXEL_FORMAT_FLOAT: REG_SET_3(FORMAT_CONTROL, 0, CNVC_BYPASS, 0, FORMAT_EXPANSION_MODE, mode, OUTPUT_FP, 1); is_float = true; break; default: break; } dpp1_set_degamma_format_float(dpp_base, is_float); switch (input_format) { case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: pixel_format = 1; break; case SURFACE_PIXEL_FORMAT_GRPH_RGB565: pixel_format = 3; alpha_en = 0; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: pixel_format = 8; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: pixel_format = 10; break; case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: force_disable_cursor = false; pixel_format = 65; color_space = COLOR_SPACE_YCBCR709; select = INPUT_CSC_SELECT_ICSC; break; case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: force_disable_cursor = true; pixel_format = 64; color_space = COLOR_SPACE_YCBCR709; select = INPUT_CSC_SELECT_ICSC; break; case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: force_disable_cursor = true; pixel_format = 67; color_space = COLOR_SPACE_YCBCR709; select = INPUT_CSC_SELECT_ICSC; break; case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: force_disable_cursor = true; pixel_format = 66; color_space = COLOR_SPACE_YCBCR709; select = INPUT_CSC_SELECT_ICSC; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: pixel_format = 22; break; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: pixel_format = 24; break; case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: pixel_format = 25; break; default: break; } REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, CNVC_SURFACE_PIXEL_FORMAT, pixel_format); REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); dpp1_program_input_csc(dpp_base, color_space, select); if (force_disable_cursor) { REG_UPDATE(CURSOR_CONTROL, CURSOR_ENABLE, 0); REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, 0); } }