int main(void)
{
#ifdef BOOTLOADER_SUPPORT
_IVREG = _BV(IVCE); /* prepare ivec change */
_IVREG = _BV(IVSEL); /* change ivec to bootloader */
#endif
/* Clear the MCUSR Register to avoid endless wdreset loops */
unsigned char reset_reason = 0;
#ifdef MCUCSR
reset_reason = MCUCSR;
MCUCSR = 0;
#else
#ifdef MCUSR
reset_reason = MCUSR;
MCUSR = 0;
#endif
#endif
/* Default DDR Config */
#if IO_HARD_PORTS == 4 && DDR_MASK_A != 0
DDRA = DDR_MASK_A;
#endif
#if DDR_MASK_B != 0
DDRB = DDR_MASK_B;
#endif
#if DDR_MASK_C != 0
DDRC = DDR_MASK_C;
#endif
#if DDR_MASK_D != 0
DDRD = DDR_MASK_D;
#endif
#if IO_HARD_PORTS == 6
#if DDR_MASK_E != 0
DDRE = DDR_MASK_E;
#endif
#if DDR_MASK_F != 0
DDRF = DDR_MASK_F;
#endif
#endif
#ifdef STATUSLED_POWER_SUPPORT
PIN_SET(STATUSLED_POWER);
#endif
//FIXME: zum ethersex meta system hinzufügen, aber vor allem anderem initalisieren
debug_init();
debug_printf("Ethersex " VERSION_STRING " (Debug mode)\n");
#ifdef DEBUG_RESET_REASON
if (bit_is_set(reset_reason, BORF)) debug_printf("reset: Brown-out\n");
else if (bit_is_set(reset_reason, PORF)) debug_printf("reset: Power on\n");
else if (bit_is_set(reset_reason, WDRF)) debug_printf("reset: Watchdog\n");
else if (bit_is_set(reset_reason, EXTRF)) debug_printf("reset: Extern\n");
else debug_printf("reset: Unknown\n");
#endif
#ifdef BOOTLOADER_SUPPORT
/* disable interrupts */
cli();
#else
/* enable interrupts */
sei();
#endif //BOOTLOADER_SUPPORT
#ifdef USE_WATCHDOG
debug_printf("enabling watchdog\n");
#ifdef DEBUG
/* for debugging, test reset cause and jump to bootloader */
if (MCUSR & _BV(WDRF)) {
debug_printf("bootloader...\n");
jump_to_bootloader();
}
#endif
/* set watchdog to 2 seconds */
wdt_enable(WDTO_2S);
wdt_kick();
#else //USE_WATCHDOG
debug_printf("disabling watchdog\n");
wdt_disable();
#endif //USE_WATCHDOG
#ifdef ADC_SUPPORT
/* ADC Prescaler to 64 */
ADCSRA = _BV(ADEN) | _BV(ADPS2) | _BV(ADPS1);
/* ADC set Voltage Reference to extern*/
/* FIXME: move config to the right place */
ADMUX = ADC_REF; //_BV(REFS0) | _BV(REFS1);
#endif
#if defined(RFM12_SUPPORT) || defined(ENC28J60_SUPPORT) \
|| defined(DATAFLASH_SUPPORT)
spi_init();
#endif
ethersex_meta_init();
#ifdef RFM12_SUPPORT
rfm12_init();
#ifdef TEENSY_SUPPORT
cli ();
rfm12_trans (0xa620); /* rfm12_setfreq(RFM12FREQ(433.92)); */
rfm12_trans (0x94ac); /* rfm12_setbandwidth(5, 1, 4); */
#ifdef RFM12_IP_SUPPORT
rfm12_trans (0xc610); /* rfm12_setbaud(192); */
rfm12_trans (0x9820); /* rfm12_setpower(0, 2); */
rfm12_rxstart();
#endif /* RFM12_IP_SUPPORT */
sei ();
#else /* TEENSY_SUPPORT */
rfm12_setfreq(RFM12FREQ(433.92));
rfm12_setbandwidth(5, 1, 4);
#ifdef RFM12_IP_SUPPORT
rfm12_setbaud(CONF_RFM12_BAUD / 100);
rfm12_setpower(0, 2);
rfm12_rxstart();
#endif /* RFM12_IP_SUPPORT */
#endif /* not TEENSY_SUPPORT */
#endif /* RFM12_SUPPORT */
/* must be called AFTER all other initialization */
#ifdef PORTIO_SUPPORT
portio_init();
#elif defined(NAMED_PIN_SUPPORT)
np_simple_init();
#endif
#ifdef ENC28J60_SUPPORT
debug_printf("enc28j60 revision 0x%x\n", read_control_register(REG_EREVID));
debug_printf("mac: %02x:%02x:%02x:%02x:%02x:%02x\n",
uip_ethaddr.addr[0],
uip_ethaddr.addr[1],
uip_ethaddr.addr[2],
uip_ethaddr.addr[3],
uip_ethaddr.addr[4],
uip_ethaddr.addr[5]
);
#endif
#ifdef STATUSLED_BOOTED_SUPPORT
PIN_SET(STATUSLED_BOOTED);
#endif
ethersex_meta_startup();
/* main loop */
while(1) {
wdt_kick();
ethersex_meta_mainloop();
#ifdef SD_READER_SUPPORT
if (sd_active_partition == NULL) {
if (! sd_try_init ())
vfs_sd_try_open_rootnode ();
wdt_kick();
}
#endif
#ifndef BOOTLOAD_SUPPORT
if(status.request_bootloader) {
#ifdef CLOCK_CRYSTAL_SUPPORT
_TIMSK_TIMER2 &= ~_BV(TOIE2);
#endif
#ifdef DCF77_SUPPORT
ACSR &= ~_BV(ACIE);
#endif
cli();
jump_to_bootloader();
}
#ifndef TEENSY_SUPPORT
if(status.request_wdreset) {
cli();
wdt_enable(WDTO_15MS);
for(;;);
}
#endif
if(status.request_reset) {
cli();
void (* reset)(void) = NULL;
reset();
}
#endif
}
}
void
rfm12_net_init(void)
{
/* wait until POR done */
for (uint8_t i = 15; i; i--)
_delay_ms(10);
rfm12_prologue(RFM12_MODULE_IP);
rfm12_trans(RFM12_CMD_LBDMCD | 0xE0);
rfm12_trans(RFM12BAND(CONF_RFM12_FREQ));
rfm12_trans(RFM12_CMD_DATAFILTER | RFM12_DATAFILTER_AL | 0x03);
rfm12_trans(RFM12_CMD_FIFORESET | 0x80 | RFM12_FIFORESET_DR);
rfm12_trans(RFM12_CMD_WAKEUP);
rfm12_trans(RFM12_CMD_DUTYCYCLE);
rfm12_trans(RFM12_CMD_AFC | 0xF7);
#ifdef CONF_RFM12B_SUPPORT
rfm12_trans(0xCED4); /* Set Sync=2DD4 */
rfm12_trans(0xCC16); /* pll bandwitdh 0: max bitrate 86.2kHz */
#endif
#ifdef DEBUG
uint16_t result = rfm12_trans(RFM12_CMD_STATUS);
RFM12_DEBUG("rfm12_net/init: %x", result);
#endif
#ifdef RFM12_DISABLE
rfm12_trans(RFM12_CMD_PWRMGT);
#else
#ifdef TEENSY_SUPPORT
rfm12_trans(RFM12_CMD_FREQUENCY | RFM12FREQ(CONF_RFM12_FREQ));
rfm12_trans(RFM12_CMD_RXCTRL | 0x04ac);
rfm12_trans(RFM12_CMD_DATARATE | 0x10);
rfm12_trans(RFM12_CMD_TXCONF | 0x20);
#else
rfm12_setfreq(RFM12FREQ(CONF_RFM12_FREQ));
rfm12_setbandwidth(5, 1, 4);
rfm12_setbaud(CONF_RFM12_BAUD / 100);
rfm12_setpower(0, 2);
#endif /* not TEENSY_SUPPORT */
#ifdef STATUSLED_RFM12_RX_SUPPORT
PIN_CLEAR(STATUSLED_RFM12_RX);
#endif
#ifdef STATUSLED_RFM12_TX_SUPPORT
PIN_CLEAR(STATUSLED_RFM12_TX);
#endif
rfm12_status = RFM12_OFF;
rfm12_int_enable();
rfm12_rxstart();
#ifdef DEBUG
result = rfm12_trans(RFM12_CMD_STATUS);
RFM12_DEBUG("rfm12_net/init'd: %x", result);
#endif
#endif /* !RFM12_DISABLE */
rfm12_epilogue();
}