//***************************************************************************** // //! Starts playback of a block of PCM audio samples. //! //! \param pvData is a pointer to the audio data to play. //! \param ulLength is the length of the data in bytes. //! \param pfnCallback is a function to call when this buffer has be played. //! //! This function starts the playback of a block of PCM audio samples. If //! playback of another buffer is currently ongoing, its playback is cancelled //! and the buffer starts playing immediately. //! //! \return 0 if the buffer was accepted, returns non-zero if there was no //! space available for this buffer. // //***************************************************************************** unsigned long SoundBufferPlay(const void *pvData, unsigned long ulLength, tBufferCallback pfnCallback) { unsigned long ulChannel; unsigned long ulDMASetting; // // Must disable I2S interrupts during this time to prevent state problems. // ROM_IntDisable(INT_I2S0); // // Save the buffer information. // g_sBuffers[g_ulPlaying].pulData = (const unsigned long *)pvData; g_sBuffers[g_ulPlaying].ulSize = ulLength; g_sBuffers[g_ulPlaying].pfnBufferCallback = pfnCallback; // // Configure the I2S TX DMA channel. // Program it to only use burst transfer. The arb size is 8 to // match the FIFO trigger level (set above). // The transfer size is 32 bits, from the TX buffer to the // TX FIFO. // ROM_uDMAChannelAttributeEnable(UDMA_CHANNEL_I2S0TX, (UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY)); if(g_ulPlaying) { ulChannel = UDMA_CHANNEL_I2S0TX | UDMA_ALT_SELECT; } else { ulChannel = UDMA_CHANNEL_I2S0TX | UDMA_PRI_SELECT; } if(g_usChannels == 1) { if(g_usBitsPerSample == 8) { ulDMASetting = UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | UDMA_ARB_4; } else { ulDMASetting = UDMA_SIZE_16 | UDMA_SRC_INC_16 | UDMA_DST_INC_NONE | UDMA_ARB_4; // // Modify the DMA transfer is 16 bits. // g_sBuffers[g_ulPlaying].ulSize >>= 1; } } else { if(g_usBitsPerSample == 8)
void WIZ610Transfer(void) { ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_UART1TX, UDMA_ATTR_ALTSELECT | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK); ROM_uDMAChannelAttributeEnable(UDMA_CHANNEL_UART1TX, UDMA_ATTR_USEBURST); ROM_uDMAChannelControlSet(UDMA_CHANNEL_UART1TX | UDMA_PRI_SELECT, UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | UDMA_ARB_4); }
//***************************************************************************** // // Initializes the UART0 peripheral and sets up the TX and RX uDMA channels. // The UART is configured for loopback mode so that any data sent on TX will be // received on RX. The uDMA channels are configured so that the TX channel // will copy data from a buffer to the UART TX output. And the uDMA RX channel // will receive any incoming data into a pair of buffers in ping-pong mode. // //***************************************************************************** void InitUART0Transfer(void) { unsigned int uIdx; // // Fill the TX buffer with a simple data pattern. // for(uIdx = 0; uIdx < UART_TXBUF_SIZE; uIdx++) { g_ucTxBuf[uIdx] = uIdx; } // // Enable the UART peripheral, and configure it to operate even if the CPU // is in sleep. // ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); ROM_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UART0); // // Configure the UART communication parameters. // ROM_UARTConfigSetExpClk(UART0_BASE, ROM_SysCtlClockGet(), 115200, UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE); // // Set both the TX and RX trigger thresholds to 4. This will be used by // the uDMA controller to signal when more data should be transferred. The // uDMA TX and RX channels will be configured so that it can transfer 4 // bytes in a burst when the UART is ready to transfer more data. // ROM_UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8); // // Enable the UART for operation, and enable the uDMA interface for both TX // and RX channels. // ROM_UARTEnable(UART0_BASE); ROM_UARTDMAEnable(UART0_BASE, UART_DMA_RX | UART_DMA_TX); // // This register write will set the UART to operate in loopback mode. Any // data sent on the TX output will be received on the RX input. // HWREG(UART0_BASE + UART_O_CTL) |= UART_CTL_LBE; // // Enable the UART peripheral interrupts. Note that no UART interrupts // were enabled, but the uDMA controller will cause an interrupt on the // UART interrupt signal when a uDMA transfer is complete. // ROM_IntEnable(INT_UART0); // // Put the attributes in a known state for the uDMA UART0RX channel. These // should already be disabled by default. // ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_UART0RX, UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK); // // Configure the control parameters for the primary control structure for // the UART RX channel. The primary contol structure is used for the "A" // part of the ping-pong receive. The transfer data size is 8 bits, the // source address does not increment since it will be reading from a // register. The destination address increment is byte 8-bit bytes. The // arbitration size is set to 4 to match the RX FIFO trigger threshold. // The uDMA controller will use a 4 byte burst transfer if possible. This // will be somewhat more effecient that single byte transfers. // ROM_uDMAChannelControlSet(UDMA_CHANNEL_UART0RX | UDMA_PRI_SELECT, UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 | UDMA_ARB_4); // // Configure the control parameters for the alternate control structure for // the UART RX channel. The alternate contol structure is used for the "B" // part of the ping-pong receive. The configuration is identical to the // primary/A control structure. // ROM_uDMAChannelControlSet(UDMA_CHANNEL_UART0RX | UDMA_ALT_SELECT, UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 | UDMA_ARB_4); // // Set up the transfer parameters for the UART RX primary control // structure. The mode is set to ping-pong, the transfer source is the // UART data register, and the destination is the receive "A" buffer. The // transfer size is set to match the size of the buffer. // ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0RX | UDMA_PRI_SELECT, UDMA_MODE_PINGPONG, (void *)(UART0_BASE + UART_O_DR), g_ucRxBufA, sizeof(g_ucRxBufA)); // // Set up the transfer parameters for the UART RX alternate control // structure. The mode is set to ping-pong, the transfer source is the // UART data register, and the destination is the receive "B" buffer. The // transfer size is set to match the size of the buffer. // ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0RX | UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, (void *)(UART0_BASE + UART_O_DR), g_ucRxBufB, sizeof(g_ucRxBufB)); // // Put the attributes in a known state for the uDMA UART0TX channel. These // should already be disabled by default. // ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_UART0TX, UDMA_ATTR_ALTSELECT | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK); // // Set the USEBURST attribute for the uDMA UART TX channel. This will // force the controller to always use a burst when transferring data from // the TX buffer to the UART. This is somewhat more effecient bus usage // than the default which allows single or burst transfers. // ROM_uDMAChannelAttributeEnable(UDMA_CHANNEL_UART0TX, UDMA_ATTR_USEBURST); // // Configure the control parameters for the UART TX. The uDMA UART TX // channel is used to transfer a block of data from a buffer to the UART. // The data size is 8 bits. The source address increment is 8-bit bytes // since the data is coming from a buffer. The destination increment is // none since the data is to be written to the UART data register. The // arbitration size is set to 4, which matches the UART TX FIFO trigger // threshold. // ROM_uDMAChannelControlSet(UDMA_CHANNEL_UART0TX | UDMA_PRI_SELECT, UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | UDMA_ARB_4); // // Set up the transfer parameters for the uDMA UART TX channel. This will // configure the transfer source and destination and the transfer size. // Basic mode is used because the peripheral is making the uDMA transfer // request. The source is the TX buffer and the destination is the UART // data register. // ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0TX | UDMA_PRI_SELECT, UDMA_MODE_BASIC, g_ucTxBuf, (void *)(UART0_BASE + UART_O_DR), sizeof(g_ucTxBuf)); // // Now both the uDMA UART TX and RX channels are primed to start a // transfer. As soon as the channels are enabled, the peripheral will // issue a transfer request and the data transfers will begin. // ROM_uDMAChannelEnable(UDMA_CHANNEL_UART0RX); ROM_uDMAChannelEnable(UDMA_CHANNEL_UART0TX); }
//***************************************************************************** // // Initializes the SSI1 peripheral and sets up the TX and RX uDMA channels. // The SSI is configured for loopback mode so that any data sent on TX will be // received on RX. The uDMA channels are configured so that the TX channel // will copy data from a buffer to the SSI TX output. And the uDMA RX channel // will receive any incoming data into a pair of buffers in ping-pong mode. // //***************************************************************************** void InitSSI2Transfer(void) { unsigned long SysClock=ROM_SysCtlClockGet(); // // Enable the SSI peripheral, and configure it to operate even if the CPU // is in sleep. // ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2); ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); ROM_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_SSI2); UARTprintf("%u\n",SysClock); GPIOPinConfigure(GPIO_PB4_SSI2CLK); GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_3, GPIO_PIN_3); GPIOPinConfigure(GPIO_PB5_SSI2FSS); GPIOPinConfigure(GPIO_PB6_SSI2RX); GPIOPinConfigure(GPIO_PB7_SSI2TX); GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); // // Configure the SSI communication parameters. // //UARTprintf("%u\n",SysClock); ROM_SSIConfigSetExpClk(SSI2_BASE, SysClock, SSI_FRF_MOTO_MODE_1, SSI_MODE_SLAVE, 1000000, 16); // // Set both the TX and RX trigger thresholds to 4. This will be used by // the uDMA controller to signal when more data should be transferred. The // uDMA TX and RX channels will be configured so that it can transfer 4 // bytes in a burst when the SSI is ready to transfer more data. // //ROM_SSIFIFOLevelSet(SSI2_BASE, SSI_FIFO_TX4_8, SSI_FIFO_RX4_8); HWREG(SSI2_BASE + SSI_O_CR1) |= 0x00000020; // set Slave Bypass mode // // Enable the SSI for operation, and enable the uDMA interface for both TX // and RX channels. // ROM_SSIEnable(SSI2_BASE); ROM_SSIDMAEnable(SSI2_BASE, SSI_DMA_RX | SSI_DMA_TX); // // This register write will set the SSI to operate in loopback mode. Any // data sent on the TX output will be received on the RX input. // // // Enable the SSI peripheral interrupts. Note that no SSI interrupts // were enabled, but the uDMA controller will cause an interrupt on the // SSI interrupt signal when a uDMA transfer is complete. // ROM_IntEnable(INT_SSI2); // // Put the attributes in a known state for the uDMA SSI2RX channel. These // should already be disabled by default. // ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_SSI2TX, UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK); ROM_uDMAChannelAssign(UDMA_CH13_SSI2TX); // // Configure the control parameters for the primary control structure for // the SSI RX channel. The primary contol structure is used for the "A" // part of the ping-pong receive. The transfer data size is 8 bits, the // source address does not increment since it will be reading from a // register. The destination address increment is byte 8-bit bytes. The // arbitration size is set to 4 to match the RX FIFO trigger threshold. // The uDMA controller will use a 4 byte burst transfer if possible. This // will be somewhat more effecient that single byte transfers. // ROM_uDMAChannelControlSet(UDMA_CHANNEL_SSI2TX | UDMA_PRI_SELECT, UDMA_SIZE_16 | UDMA_SRC_INC_16 | UDMA_DST_INC_NONE | UDMA_ARB_4); // // Configure the control parameters for the alternate control structure for // the SSI RX channel. The alternate contol structure is used for the "B" // part of the ping-pong receive. The configuration is identical to the // primary/A control structure. // ROM_uDMAChannelControlSet(UDMA_CHANNEL_SSI2TX | UDMA_ALT_SELECT, UDMA_SIZE_16 | UDMA_SRC_INC_16 | UDMA_DST_INC_NONE | UDMA_ARB_4); // // Set up the transfer parameters for the SSI RX primary control // structure. The mode is set to ping-pong, the transfer source is the // SSI data register, and the destination is the receive "A" buffer. The // transfer size is set to match the size of the buffer. // ROM_uDMAChannelTransferSet(UDMA_CHANNEL_SSI2TX | UDMA_PRI_SELECT, UDMA_MODE_PINGPONG, (void *)g_uiSsiTxBufA, (void *)(SSI2_BASE + SSI_O_DR), SSI_TXBUF_SIZE); // // Set up the transfer parameters for the SSI RX alternate control // structure. The mode is set to ping-pong, the transfer source is the // SSI data register, and the destination is the receive "B" buffer. The // transfer size is set to match the size of the buffer. // ROM_uDMAChannelTransferSet(UDMA_CHANNEL_SSI2TX | UDMA_ALT_SELECT, UDMA_MODE_PINGPONG, (void *)g_uiSsiTxBufB, (void *)(SSI2_BASE + SSI_O_DR), SSI_TXBUF_SIZE); ROM_uDMAChannelAttributeEnable(UDMA_CHANNEL_SSI2TX, UDMA_ATTR_USEBURST); UARTprintf("A_base: %X \n",(void *)g_uiSsiTxBufA); UARTprintf("B_base: %X \n",(void *)(g_uiSsiTxBufB)); // // Put the attributes in a known state for the uDMA SSI2TX channel. These // should already be disabled by default. // ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_SSI2RX, UDMA_ATTR_ALTSELECT | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK); ROM_uDMAChannelAssign(UDMA_CH12_SSI2RX); // // Set the USEBURST attribute for the uDMA SSI RX channel. This will // force the controller to always use a burst when transferring data from // the TX buffer to the SSI. This is somewhat more effecient bus usage // than the default which allows single or burst transfers. // ROM_uDMAChannelAttributeEnable(UDMA_CHANNEL_SSI2RX, UDMA_ATTR_USEBURST); // // Configure the control parameters for the SSI TX. The uDMA SSI TX // channel is used to transfer a block of data from a buffer to the SSI. // The data size is 8 bits. The source address increment is 8-bit bytes // since the data is coming from a buffer. The destination increment is // none since the data is to be written to the SSI data register. The // arbitration size is set to 4, which matches the SSI TX FIFO trigger // threshold. // ROM_uDMAChannelControlSet(UDMA_CHANNEL_SSI2RX | UDMA_PRI_SELECT, UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 | UDMA_ARB_4); // // Set up the transfer parameters for the uDMA SSI TX channel. This will // configure the transfer source and destination and the transfer size. // Basic mode is used because the peripheral is making the uDMA transfer // request. The source is the TX buffer and the destination is the SSI // data register. // ROM_uDMAChannelTransferSet(UDMA_CHANNEL_SSI2RX | UDMA_PRI_SELECT, UDMA_MODE_BASIC, (void *)(SSI2_BASE + SSI_O_DR), (void *)g_uiSsiRxBuf, SSI_RXBUF_SIZE); // // Now both the uDMA SSI TX and RX channels are primed to start a // transfer. As soon as the channels are enabled, the peripheral will // issue a transfer request and the data transfers will begin. // ROM_uDMAChannelEnable(UDMA_CHANNEL_SSI2TX); ROM_uDMAChannelEnable(UDMA_CHANNEL_SSI2RX); GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_3, 0); }