Area Ship::bounding() const { // the idea in the following code is to calculate a bounding box // around the ship's triangle and use it for collision detection. // TODO: find a nicer way of rotating and translating // (-center_ and +center_ is not intuitive) // first calculate the triangle 'shadowing' the triangle on display // this means a rotation and translation needs to be applied to the // known points (see Ship::draw for comparison to the OpenGL code) const vector2 &RA = A_ - center_, &RB = B_ - center_, &RC = C_ - center_; // this is probably inefficient vector2 RRA(0, 0), RRB(0, 0), RRC(0, 0); float ra = to_radians(rot_angle_); rotate_vector(RA, ra, RRA); rotate_vector(RB, ra, RRB); rotate_vector(RC, ra, RRC); RRA += pos_ + center_; RRB += pos_ + center_; RRC += pos_ + center_; const vector2* points[3] = { &RRA, &RRB, &RRC } ; // no point storing the bounding box, because it depends on position // find a bounding box encompassing all points return Area::minimumArea(points, 3); }
int cpu::cpu_emulate(int ciclos){ UINT8 op,b,cbop; UINT32 i; UINT32 clen = 10; UINT16 w; static cpuReg acc; i = ciclos; //next: while((!CPU->IME) && i > 0){ mt.lock(); op = FETCH; ciclos = cycles_table[op]; switch(op) { case 0x00: /* NOP */ case 0x40: /* LD B,B */ case 0x49: /* LD C,C */ case 0x52: /* LD D,D */ case 0x5B: /* LD E,E */ case 0x64: /* LD H,H */ case 0x6D: /* LD L,L */ case 0x7F: /* LD A,A */ break; case 0x41: /* LD B,C */ B = C; break; case 0x42: /* LD B,D */ B = D; break; case 0x43: /* LD B,E */ B = E; break; case 0x44: /* LD B,H */ B = H; break; case 0x45: /* LD B,L */ B = L; break; case 0x46: /* LD B,(HL) */ B = memoria::readByte(xHL); break; case 0x47: /* LD B,A */ B = A; break; case 0x48: /* LD C,B */ C = B; break; case 0x4A: /* LD C,D */ C = D; break; case 0x4B: /* LD C,E */ C = E; break; case 0x4C: /* LD C,H */ C = H; break; case 0x4D: /* LD C,L */ C = L; break; case 0x4E: /* LD C,(HL) */ C = memoria::readByte(xHL); break; case 0x4F: /* LD C,A */ C = A; break; case 0x50: /* LD D,B */ D = B; break; case 0x51: /* LD D,C */ D = C; break; case 0x53: /* LD D,E */ D = E; break; case 0x54: /* LD D,H */ D = H; break; case 0x55: /* LD D,L */ D = L; break; case 0x56: /* LD D,(HL) */ D = memoria::readByte(xHL); break; case 0x57: /* LD D,A */ D = A; break; case 0x58: /* LD E,B */ E = B; break; case 0x59: /* LD E,C */ E = C; break; case 0x5A: /* LD E,D */ E = D; break; case 0x5C: /* LD E,H */ E = H; break; case 0x5D: /* LD E,L */ E = L; break; case 0x5E: /* LD E,(HL) */ E = memoria::readByte(xHL); break; case 0x5F: /* LD E,A */ E = A; break; case 0x60: /* LD H,B */ H = B; break; case 0x61: /* LD H,C */ H = C; break; case 0x62: /* LD H,D */ H = D; break; case 0x63: /* LD H,E */ H = E; break; case 0x65: /* LD H,L */ H = L; break; case 0x66: /* LD H,(HL) */ H = memoria::readByte(xHL); break; case 0x67: /* LD H,A */ H = A; break; case 0x68: /* LD L,B */ L = B; break; case 0x69: /* LD L,C */ L = C; break; case 0x6A: /* LD L,D */ L = D; break; case 0x6B: /* LD L,E */ L = E; break; case 0x6C: /* LD L,H */ L = H; break; case 0x6E: /* LD L,(HL) */ L = memoria::readByte(xHL); break; case 0x6F: /* LD L,A */ L = A; break; case 0x70: /* LD (HL),B */ b = B; goto __LD_HL; case 0x71: /* LD (HL),C */ b = C; goto __LD_HL; case 0x72: /* LD (HL),D */ b = D; goto __LD_HL; case 0x73: /* LD (HL),E */ b = E; goto __LD_HL; case 0x74: /* LD (HL),H */ b = H; goto __LD_HL; case 0x75: /* LD (HL),L */ b = L; goto __LD_HL; case 0x77: /* LD (HL),A */ b = A; __LD_HL: memoria::writeByte(xHL,b); break; case 0x78: /* LD A,B */ A = B; break; case 0x79: /* LD A,C */ A = C; break; case 0x7A: /* LD A,D */ A = D; break; case 0x7B: /* LD A,E */ A = E; break; case 0x7C: /* LD A,H */ A = H; break; case 0x7D: /* LD A,L */ A = L; break; case 0x7E: /* LD A,(HL) */ A = memoria::readByte(xHL); break; case 0x01: /* LD BC,imm */ CPU->BC.w = memoria::readWord(xPC); CPU->PC += 2; break; case 0x11: /* LD DE,imm */ CPU->DE.w = memoria::readWord(xPC); CPU->PC += 2; break; case 0x21: /* LD HL,imm */ CPU->HL.w = memoria::readWord(xPC); CPU->PC += 2; break; case 0x31: /* LD SP,imm */ CPU->SP = memoria::readWord(xPC); CPU->PC += 2; break; case 0x02: /* LD (BC),A */ memoria::writeByte(CPU->BC.w, A); break; case 0x0A: /* LD A,(BC) */ A = memoria::readByte(CPU->BC.w); break; case 0x12: /* LD (DE),A */ memoria::writeByte(CPU->BC.w, A); break; case 0x1A: /* LD A,(DE) */ A = memoria::readByte(CPU->DE.w); break; case 0x22: /* LDI (HL),A */ memoria::writeByte(xHL, A); CPU->HL.w++; break; case 0x2A: /* LDI A,(HL) */ A = memoria::readByte(xHL); CPU->HL.w++; break; case 0x32: /* LDD (HL),A */ memoria::writeByte(xHL, A); CPU->HL.w--; break; case 0x3A: /* LDD A,(HL) */ A = memoria::readByte(xHL); CPU->HL.w--; break; case 0x06: /* LD B,imm */ B = FETCH; break; case 0x0E: /* LD C,imm */ C = FETCH; break; case 0x16: /* LD D,imm */ D = FETCH; break; case 0x1E: /* LD E,imm */ E = FETCH; break; case 0x26: /* LD H,imm */ H = FETCH; break; case 0x2E: /* LD L,imm */ L = FETCH; break; case 0x36: /* LD (HL),imm */ b = FETCH; memoria::writeByte(xHL, b); break; case 0x3E: /* LD A,imm */ A = FETCH; break; case 0x08: /* LD (imm),CPU->SP */ memoria::writeWord(memoria::readWord(xPC), CPU->SP); CPU->PC += 2; break; case 0xEA: /* LD (imm),A */ memoria::writeByte(memoria::readWord(xPC), A); CPU->PC += 2; break; case 0xF8: /* LD HL,CPU->SP+imm */ b = FETCH; LDHLSP(b); break; case 0xF9: /* LD CPU->SP,HL */ CPU->SP = CPU->HL.w; break; case 0xFA: /* LD A,(imm) */ A = memoria::readByte(memoria::readWord(xPC)); CPU->PC += 2; break; ALU_CASES(0x80, 0xC6, ADD, __ADD) ALU_CASES(0x88, 0xCE, ADC, __ADC) ALU_CASES(0x90, 0xD6, SUB, __SUB) ALU_CASES(0x98, 0xDE, SBC, __SBC) ALU_CASES(0xA0, 0xE6, AND, __AND) ALU_CASES(0xA8, 0xEE, XOR, __XOR) ALU_CASES(0xB0, 0xF6, OR, __OR) ALU_CASES(0xB8, 0xFE, CP, __CP) case 0x09: /* ADD HL,BC */ w = CPU->BC.w; goto __ADDW; case 0x19: /* ADD HL,DE */ w = CPU->DE.w; goto __ADDW; case 0x39: /* ADD HL,CPU->SP */ w = CPU->SP; goto __ADDW; case 0x29: /* ADD HL,HL */ w = CPU->HL.w; __ADDW: ADDW(w); break; case 0x04: /* INC B */ INC(B); break; case 0x0C: /* INC C */ INC(C); break; case 0x14: /* INC D */ INC(D); break; case 0x1C: /* INC E */ INC(E); break; case 0x24: /* INC H */ INC(H); break; case 0x2C: /* INC L */ INC(L); break; case 0x34: /* INC (HL) */ b = memoria::readByte(xHL); INC(b); memoria::writeByte(xHL, b); break; case 0x3C: /* INC A */ INC(A); break; case 0x03: /* INC BC */ INCW(CPU->BC.w); break; case 0x13: /* INC DE */ INCW(CPU->DE.w); break; case 0x23: /* INC HL */ INCW(CPU->HL.w); break; case 0x33: /* INC CPU->SP */ INCW(CPU->SP); break; case 0x05: /* DEC B */ DEC(B); break; case 0x0D: /* DEC C */ DEC(C); break; case 0x15: /* DEC D */ DEC(D); break; case 0x1D: /* DEC E */ DEC(E); break; case 0x25: /* DEC H */ DEC(H); break; case 0x2D: /* DEC L */ DEC(L); break; case 0x35: /* DEC (HL) */ b = memoria::readByte(xHL); DEC(b); memoria::writeByte(xHL, b); break; case 0x3D: /* DEC A */ DEC(A); break; case 0x0B: /* DEC BC */ DECW(CPU->BC.w); break; case 0x1B: /* DEC DE */ DECW(CPU->DE.w); break; case 0x2B: /* DEC HL */ DECW(CPU->HL.w); break; case 0x3B: /* DEC CPU->SP */ DECW(CPU->SP); break; case 0x07: /* RLCA */ RLCA(A); break; case 0x0F: /* RRCA */ RRCA(A); break; case 0x17: /* RLA */ RLA(A); break; case 0x1F: /* RRA */ RRA(A); break; case 0x27: /* DAA */ DAA; break; case 0x2F: /* CPL */ CPL(A); break; case 0x18: /* JR */ __JR: JR; break; case 0x20: /* JR NZ */ if (!(F&FZ)) goto __JR; NOJR; break; case 0x28: /* JR Z */ if (F&FZ) goto __JR; NOJR; break; case 0x30: /* JR NC */ if (!(F&FC)) goto __JR; NOJR; break; case 0x38: /* JR C */ if (F&FC) goto __JR; NOJR; break; case 0xC3: /* JP */ __JP: JP; break; case 0xC2: /* JP NZ */ if (!(F&FZ)) goto __JP; NOJP; break; case 0xCA: /* JP Z */ if (F&FZ) goto __JP; NOJP; break; case 0xD2: /* JP NC */ if (!(F&FC)) goto __JP; NOJP; break; case 0xDA: /* JP C */ if (F&FC) goto __JP; NOJP; break; case 0xE9: /* JP HL */ CPU->PC = CPU->HL.w; break; case 0xC9: /* RET */ __RET: RET; break; case 0xC0: /* RET NZ */ if (!(F&FZ)) goto __RET; NORET; break; case 0xC8: /* RET Z */ if (F&FZ) goto __RET; NORET; break; case 0xD0: /* RET NC */ if (!(F&FC)) goto __RET; NORET; break; case 0xD8: /* RET C */ if (F&FC) goto __RET; NORET; break; case 0xD9: /* RETI */ CPU->IME = CPU->IMA = 1; goto __RET; case 0xCD: /* CALL */ __CALL: CALL; break; case 0xC4: /* CALL NZ */ if (!(F&FZ)) goto __CALL; NOCALL; break; case 0xCC: /* CALL Z */ if (F&FZ) goto __CALL; NOCALL; break; case 0xD4: /* CALL NC */ if (!(F&FC)) goto __CALL; NOCALL; break; case 0xDC: /* CALL C */ if (F&FC) goto __CALL; NOCALL; break; case 0xC7: /* RST 0 */ b = 0x00; goto __RST; case 0xCF: /* RST 8 */ b = 0x08; goto __RST; case 0xD7: /* RST 10 */ b = 0x10; goto __RST; case 0xDF: /* RST 18 */ b = 0x18; goto __RST; case 0xE7: /* RST 20 */ b = 0x20; goto __RST; case 0xEF: /* RST 28 */ b = 0x28; goto __RST; case 0xF7: /* RST 30 */ b = 0x30; goto __RST; case 0xFF: /* RST 38 */ b = 0x38; __RST: RST(b); break; case 0xC1: /* POP BC */ POP(CPU->BC.w); break; case 0xC5: /* PUSH BC */ PUSH(CPU->BC.w); break; case 0xD1: /* POP DE */ POP(CPU->DE.w); break; case 0xD5: /* PUSH DE */ PUSH(CPU->DE.w); break; case 0xE1: /* POP HL */ POP(CPU->HL.w); break; case 0xE5: /* PUSH HL */ PUSH(CPU->HL.w); break; case 0xF1: /* POP AF */ POP(CPU->AF.w); break; case 0xF5: /* PUSH AF */ PUSH(CPU->AF.w); break; case 0xE8: /* ADD CPU->SP,imm */ b = FETCH; ADDSP(b); break; case 0xF3: /* DI */ DI; break; case 0xFB: /* EI */ EI; break; case 0x37: /* SCF */ SCF; break; case 0x3F: /* CCF */ CCF; break; case 0x10: /* STOP */ break; //to do// case 0x76: /* HALT */ CPU->halt = 1; break; case 0xCB: /* CB prefix */ cbop = FETCH; clen = cb_cycles_table[cbop]; switch (cbop) { CB_REG_CASES(B, 0); CB_REG_CASES(C, 1); CB_REG_CASES(D, 2); CB_REG_CASES(E, 3); CB_REG_CASES(H, 4); CB_REG_CASES(L, 5); CB_REG_CASES(A, 7); default: b = memoria::readByte(xHL); switch(cbop) { CB_REG_CASES(b, 6); } if ((cbop & 0xC0) != 0x40) /* exclude BIT */ memoria::writeByte(xHL, b); break; } break; default: printf("erro"); break; } clen <<= 1; i -= clen; emit onEndProcess((UINT32)op); mt.unlock(); //msleep(600); } //if(i >0) goto next; wt.wait(&mt); return ciclos-i; }
// // 柦椷幚峴 // INT CPU::EXEC( INT request_cycles ) { BYTE opcode; // 僆儁僐乕僪 INT OLD_cycles = TOTAL_cycles; INT exec_cycles; BYTE nmi_request, irq_request; BOOL bClockProcess = m_bClockProcess; // TEMP register WORD EA; register WORD ET; register WORD WT; register BYTE DT; while( request_cycles > 0 ) { exec_cycles = 0; if( DMA_cycles ) { if( request_cycles <= DMA_cycles ) { DMA_cycles -= request_cycles; TOTAL_cycles += request_cycles; // 僋儘僢僋摨婜張棟 mapper->Clock( request_cycles ); #if DPCM_SYNCCLOCK apu->SyncDPCM( request_cycles ); #endif if( bClockProcess ) { nes->Clock( request_cycles ); } // nes->Clock( request_cycles ); goto _execute_exit; } else { exec_cycles += DMA_cycles; // request_cycles -= DMA_cycles; DMA_cycles = 0; } } nmi_request = irq_request = 0; opcode = OP6502( R.PC++ ); if( R.INT_pending ) { if( R.INT_pending & NMI_FLAG ) { nmi_request = 0xFF; R.INT_pending &= ~NMI_FLAG; } else if( R.INT_pending & IRQ_MASK ) { R.INT_pending &= ~IRQ_TRIGGER2; if( !(R.P & I_FLAG) && opcode != 0x40 ) { irq_request = 0xFF; R.INT_pending &= ~IRQ_TRIGGER; } } } //增加指令预测忽略功能 //opcode BYTE iInstructionLen =1; switch (TraceAddrMode[opcode]) { case IND: case ADR: case ABS: case ABX: case ABY: iInstructionLen = 3; break; case IMM: case ZPG: case ZPX: case ZPY: case INX: case INY: iInstructionLen = 2; break; case IMP:case ACC:case ERR: break; case REL:iInstructionLen = 2;break; } if( ((TraceArr[opcode][0]=='*') || (TraceArr[opcode][1]=='?'))&& (!Config.emulator.bIllegalOp) ) { //这里可以优化输出信息 //char str[111]; //DecodeInstruction (R.PC-1, str); //DEBUGOUT( "Bad Instruction:%s\n",str); R.PC=(R.PC-1)+iInstructionLen; ADD_CYCLE(iInstructionLen*2); goto end_is; } // switch( opcode ) { case 0x69: // ADC #$?? MR_IM(); ADC(); ADD_CYCLE(2); break; case 0x65: // ADC $?? MR_ZP(); ADC(); ADD_CYCLE(3); break; case 0x75: // ADC $??,X MR_ZX(); ADC(); ADD_CYCLE(4); break; case 0x6D: // ADC $???? MR_AB(); ADC(); ADD_CYCLE(4); break; case 0x7D: // ADC $????,X MR_AX(); ADC(); CHECK_EA(); ADD_CYCLE(4); break; case 0x79: // ADC $????,Y MR_AY(); ADC(); CHECK_EA(); ADD_CYCLE(4); break; case 0x61: // ADC ($??,X) MR_IX(); ADC(); ADD_CYCLE(6); break; case 0x71: // ADC ($??),Y MR_IY(); ADC(); CHECK_EA(); ADD_CYCLE(4); break; case 0xE9: // SBC #$?? MR_IM(); SBC(); ADD_CYCLE(2); break; case 0xE5: // SBC $?? MR_ZP(); SBC(); ADD_CYCLE(3); break; case 0xF5: // SBC $??,X MR_ZX(); SBC(); ADD_CYCLE(4); break; case 0xED: // SBC $???? MR_AB(); SBC(); ADD_CYCLE(4); break; case 0xFD: // SBC $????,X MR_AX(); SBC(); CHECK_EA(); ADD_CYCLE(4); break; case 0xF9: // SBC $????,Y MR_AY(); SBC(); CHECK_EA(); ADD_CYCLE(4); break; case 0xE1: // SBC ($??,X) MR_IX(); SBC(); ADD_CYCLE(6); break; case 0xF1: // SBC ($??),Y MR_IY(); SBC(); CHECK_EA(); ADD_CYCLE(5); break; case 0xC6: // DEC $?? MR_ZP(); DEC(); MW_ZP(); ADD_CYCLE(5); break; case 0xD6: // DEC $??,X MR_ZX(); DEC(); MW_ZP(); ADD_CYCLE(6); break; case 0xCE: // DEC $???? MR_AB(); DEC(); MW_EA(); ADD_CYCLE(6); break; case 0xDE: // DEC $????,X MR_AX(); DEC(); MW_EA(); ADD_CYCLE(7); break; case 0xCA: // DEX DEX(); ADD_CYCLE(2); break; case 0x88: // DEY DEY(); ADD_CYCLE(2); break; case 0xE6: // INC $?? MR_ZP(); INC(); MW_ZP(); ADD_CYCLE(5); break; case 0xF6: // INC $??,X MR_ZX(); INC(); MW_ZP(); ADD_CYCLE(6); break; case 0xEE: // INC $???? MR_AB(); INC(); MW_EA(); ADD_CYCLE(6); break; case 0xFE: // INC $????,X MR_AX(); INC(); MW_EA(); ADD_CYCLE(7); break; case 0xE8: // INX INX(); ADD_CYCLE(2); break; case 0xC8: // INY INY(); ADD_CYCLE(2); break; case 0x29: // AND #$?? MR_IM(); AND(); ADD_CYCLE(2); break; case 0x25: // AND $?? MR_ZP(); AND(); ADD_CYCLE(3); break; case 0x35: // AND $??,X MR_ZX(); AND(); ADD_CYCLE(4); break; case 0x2D: // AND $???? MR_AB(); AND(); ADD_CYCLE(4); break; case 0x3D: // AND $????,X MR_AX(); AND(); CHECK_EA(); ADD_CYCLE(4); break; case 0x39: // AND $????,Y MR_AY(); AND(); CHECK_EA(); ADD_CYCLE(4); break; case 0x21: // AND ($??,X) MR_IX(); AND(); ADD_CYCLE(6); break; case 0x31: // AND ($??),Y MR_IY(); AND(); CHECK_EA(); ADD_CYCLE(5); break; case 0x0A: // ASL A ASL_A(); ADD_CYCLE(2); break; case 0x06: // ASL $?? MR_ZP(); ASL(); MW_ZP(); ADD_CYCLE(5); break; case 0x16: // ASL $??,X MR_ZX(); ASL(); MW_ZP(); ADD_CYCLE(6); break; case 0x0E: // ASL $???? MR_AB(); ASL(); MW_EA(); ADD_CYCLE(6); break; case 0x1E: // ASL $????,X MR_AX(); ASL(); MW_EA(); ADD_CYCLE(7); break; case 0x24: // BIT $?? MR_ZP(); BIT(); ADD_CYCLE(3); break; case 0x2C: // BIT $???? MR_AB(); BIT(); ADD_CYCLE(4); break; case 0x49: // EOR #$?? MR_IM(); EOR(); ADD_CYCLE(2); break; case 0x45: // EOR $?? MR_ZP(); EOR(); ADD_CYCLE(3); break; case 0x55: // EOR $??,X MR_ZX(); EOR(); ADD_CYCLE(4); break; case 0x4D: // EOR $???? MR_AB(); EOR(); ADD_CYCLE(4); break; case 0x5D: // EOR $????,X MR_AX(); EOR(); CHECK_EA(); ADD_CYCLE(4); break; case 0x59: // EOR $????,Y MR_AY(); EOR(); CHECK_EA(); ADD_CYCLE(4); break; case 0x41: // EOR ($??,X) MR_IX(); EOR(); ADD_CYCLE(6); break; case 0x51: // EOR ($??),Y MR_IY(); EOR(); CHECK_EA(); ADD_CYCLE(5); break; case 0x4A: // LSR A LSR_A(); ADD_CYCLE(2); break; case 0x46: // LSR $?? MR_ZP(); LSR(); MW_ZP(); ADD_CYCLE(5); break; case 0x56: // LSR $??,X MR_ZX(); LSR(); MW_ZP(); ADD_CYCLE(6); break; case 0x4E: // LSR $???? MR_AB(); LSR(); MW_EA(); ADD_CYCLE(6); break; case 0x5E: // LSR $????,X MR_AX(); LSR(); MW_EA(); ADD_CYCLE(7); break; case 0x09: // ORA #$?? MR_IM(); ORA(); ADD_CYCLE(2); break; case 0x05: // ORA $?? MR_ZP(); ORA(); ADD_CYCLE(3); break; case 0x15: // ORA $??,X MR_ZX(); ORA(); ADD_CYCLE(4); break; case 0x0D: // ORA $???? MR_AB(); ORA(); ADD_CYCLE(4); break; case 0x1D: // ORA $????,X MR_AX(); ORA(); CHECK_EA(); ADD_CYCLE(4); break; case 0x19: // ORA $????,Y MR_AY(); ORA(); CHECK_EA(); ADD_CYCLE(4); break; case 0x01: // ORA ($??,X) MR_IX(); ORA(); ADD_CYCLE(6); break; case 0x11: // ORA ($??),Y MR_IY(); ORA(); CHECK_EA(); ADD_CYCLE(5); break; case 0x2A: // ROL A ROL_A(); ADD_CYCLE(2); break; case 0x26: // ROL $?? MR_ZP(); ROL(); MW_ZP(); ADD_CYCLE(5); break; case 0x36: // ROL $??,X MR_ZX(); ROL(); MW_ZP(); ADD_CYCLE(6); break; case 0x2E: // ROL $???? MR_AB(); ROL(); MW_EA(); ADD_CYCLE(6); break; case 0x3E: // ROL $????,X MR_AX(); ROL(); MW_EA(); ADD_CYCLE(7); break; case 0x6A: // ROR A ROR_A(); ADD_CYCLE(2); break; case 0x66: // ROR $?? MR_ZP(); ROR(); MW_ZP(); ADD_CYCLE(5); break; case 0x76: // ROR $??,X MR_ZX(); ROR(); MW_ZP(); ADD_CYCLE(6); break; case 0x6E: // ROR $???? MR_AB(); ROR(); MW_EA(); ADD_CYCLE(6); break; case 0x7E: // ROR $????,X MR_AX(); ROR(); MW_EA(); ADD_CYCLE(7); break; case 0xA9: // LDA #$?? MR_IM(); LDA(); ADD_CYCLE(2); break; case 0xA5: // LDA $?? MR_ZP(); LDA(); ADD_CYCLE(3); break; case 0xB5: // LDA $??,X MR_ZX(); LDA(); ADD_CYCLE(4); break; case 0xAD: // LDA $???? MR_AB(); LDA(); ADD_CYCLE(4); break; case 0xBD: // LDA $????,X MR_AX(); LDA(); CHECK_EA(); ADD_CYCLE(4); break; case 0xB9: // LDA $????,Y MR_AY(); LDA(); CHECK_EA(); ADD_CYCLE(4); break; case 0xA1: // LDA ($??,X) MR_IX(); LDA(); ADD_CYCLE(6); break; case 0xB1: // LDA ($??),Y MR_IY(); LDA(); CHECK_EA(); ADD_CYCLE(5); break; case 0xA2: // LDX #$?? MR_IM(); LDX(); ADD_CYCLE(2); break; case 0xA6: // LDX $?? MR_ZP(); LDX(); ADD_CYCLE(3); break; case 0xB6: // LDX $??,Y MR_ZY(); LDX(); ADD_CYCLE(4); break; case 0xAE: // LDX $???? MR_AB(); LDX(); ADD_CYCLE(4); break; case 0xBE: // LDX $????,Y MR_AY(); LDX(); CHECK_EA(); ADD_CYCLE(4); break; case 0xA0: // LDY #$?? MR_IM(); LDY(); ADD_CYCLE(2); break; case 0xA4: // LDY $?? MR_ZP(); LDY(); ADD_CYCLE(3); break; case 0xB4: // LDY $??,X MR_ZX(); LDY(); ADD_CYCLE(4); break; case 0xAC: // LDY $???? MR_AB(); LDY(); ADD_CYCLE(4); break; case 0xBC: // LDY $????,X MR_AX(); LDY(); CHECK_EA(); ADD_CYCLE(4); break; case 0x85: // STA $?? EA_ZP(); STA(); MW_ZP(); ADD_CYCLE(3); break; case 0x95: // STA $??,X EA_ZX(); STA(); MW_ZP(); ADD_CYCLE(4); break; case 0x8D: // STA $???? EA_AB(); STA(); MW_EA(); ADD_CYCLE(4); break; case 0x9D: // STA $????,X EA_AX(); STA(); MW_EA(); ADD_CYCLE(5); break; case 0x99: // STA $????,Y EA_AY(); STA(); MW_EA(); ADD_CYCLE(5); break; case 0x81: // STA ($??,X) EA_IX(); STA(); MW_EA(); ADD_CYCLE(6); break; case 0x91: // STA ($??),Y EA_IY(); STA(); MW_EA(); ADD_CYCLE(6); break; case 0x86: // STX $?? EA_ZP(); STX(); MW_ZP(); ADD_CYCLE(3); break; case 0x96: // STX $??,Y EA_ZY(); STX(); MW_ZP(); ADD_CYCLE(4); break; case 0x8E: // STX $???? EA_AB(); STX(); MW_EA(); ADD_CYCLE(4); break; case 0x84: // STY $?? EA_ZP(); STY(); MW_ZP(); ADD_CYCLE(3); break; case 0x94: // STY $??,X EA_ZX(); STY(); MW_ZP(); ADD_CYCLE(4); break; case 0x8C: // STY $???? EA_AB(); STY(); MW_EA(); ADD_CYCLE(4); break; case 0xAA: // TAX TAX(); ADD_CYCLE(2); break; case 0x8A: // TXA TXA(); ADD_CYCLE(2); break; case 0xA8: // TAY TAY(); ADD_CYCLE(2); break; case 0x98: // TYA TYA(); ADD_CYCLE(2); break; case 0xBA: // TSX TSX(); ADD_CYCLE(2); break; case 0x9A: // TXS TXS(); ADD_CYCLE(2); break; case 0xC9: // CMP #$?? MR_IM(); CMP_(); ADD_CYCLE(2); break; case 0xC5: // CMP $?? MR_ZP(); CMP_(); ADD_CYCLE(3); break; case 0xD5: // CMP $??,X MR_ZX(); CMP_(); ADD_CYCLE(4); break; case 0xCD: // CMP $???? MR_AB(); CMP_(); ADD_CYCLE(4); break; case 0xDD: // CMP $????,X MR_AX(); CMP_(); CHECK_EA(); ADD_CYCLE(4); break; case 0xD9: // CMP $????,Y MR_AY(); CMP_(); CHECK_EA(); ADD_CYCLE(4); break; case 0xC1: // CMP ($??,X) MR_IX(); CMP_(); ADD_CYCLE(6); break; case 0xD1: // CMP ($??),Y MR_IY(); CMP_(); CHECK_EA(); ADD_CYCLE(5); break; case 0xE0: // CPX #$?? MR_IM(); CPX(); ADD_CYCLE(2); break; case 0xE4: // CPX $?? MR_ZP(); CPX(); ADD_CYCLE(3); break; case 0xEC: // CPX $???? MR_AB(); CPX(); ADD_CYCLE(4); break; case 0xC0: // CPY #$?? MR_IM(); CPY(); ADD_CYCLE(2); break; case 0xC4: // CPY $?? MR_ZP(); CPY(); ADD_CYCLE(3); break; case 0xCC: // CPY $???? MR_AB(); CPY(); ADD_CYCLE(4); break; case 0x90: // BCC MR_IM(); BCC(); ADD_CYCLE(2); break; case 0xB0: // BCS MR_IM(); BCS(); ADD_CYCLE(2); break; case 0xF0: // BEQ MR_IM(); BEQ(); ADD_CYCLE(2); break; case 0x30: // BMI MR_IM(); BMI(); ADD_CYCLE(2); break; case 0xD0: // BNE MR_IM(); BNE(); ADD_CYCLE(2); break; case 0x10: // BPL MR_IM(); BPL(); ADD_CYCLE(2); break; case 0x50: // BVC MR_IM(); BVC(); ADD_CYCLE(2); break; case 0x70: // BVS MR_IM(); BVS(); ADD_CYCLE(2); break; case 0x4C: // JMP $???? JMP(); ADD_CYCLE(3); break; case 0x6C: // JMP ($????) JMP_ID(); ADD_CYCLE(5); break; case 0x20: // JSR JSR(); ADD_CYCLE(6); break; case 0x40: // RTI RTI(); ADD_CYCLE(6); break; case 0x60: // RTS RTS(); ADD_CYCLE(6); break; // 僼儔僌惂屼宯 case 0x18: // CLC CLC(); ADD_CYCLE(2); break; case 0xD8: // CLD CLD(); ADD_CYCLE(2); break; case 0x58: // CLI CLI(); ADD_CYCLE(2); break; case 0xB8: // CLV CLV(); ADD_CYCLE(2); break; case 0x38: // SEC SEC(); ADD_CYCLE(2); break; case 0xF8: // SED SED(); ADD_CYCLE(2); break; case 0x78: // SEI SEI(); ADD_CYCLE(2); break; // 僗僞僢僋宯 case 0x48: // PHA PUSH( R.A ); ADD_CYCLE(3); break; case 0x08: // PHP PUSH( R.P | B_FLAG ); ADD_CYCLE(3); break; case 0x68: // PLA (N-----Z-) R.A = POP(); SET_ZN_FLAG(R.A); ADD_CYCLE(4); break; case 0x28: // PLP R.P = POP() | R_FLAG; ADD_CYCLE(4); break; // 偦偺懠 case 0x00: // BRK BRK(); ADD_CYCLE(7); break; case 0xEA: // NOP ADD_CYCLE(2); break; // 枹岞奐柦椷孮 case 0x0B: // ANC #$?? case 0x2B: // ANC #$?? MR_IM(); ANC(); ADD_CYCLE(2); break; case 0x8B: // ANE #$?? MR_IM(); ANE(); ADD_CYCLE(2); break; case 0x6B: // ARR #$?? MR_IM(); ARR(); ADD_CYCLE(2); break; case 0x4B: // ASR #$?? MR_IM(); ASR(); ADD_CYCLE(2); break; case 0xC7: // DCP $?? MR_ZP(); DCP(); MW_ZP(); ADD_CYCLE(5); break; case 0xD7: // DCP $??,X MR_ZX(); DCP(); MW_ZP(); ADD_CYCLE(6); break; case 0xCF: // DCP $???? MR_AB(); DCP(); MW_EA(); ADD_CYCLE(6); break; case 0xDF: // DCP $????,X MR_AX(); DCP(); MW_EA(); ADD_CYCLE(7); break; case 0xDB: // DCP $????,Y MR_AY(); DCP(); MW_EA(); ADD_CYCLE(7); break; case 0xC3: // DCP ($??,X) MR_IX(); DCP(); MW_EA(); ADD_CYCLE(8); break; case 0xD3: // DCP ($??),Y MR_IY(); DCP(); MW_EA(); ADD_CYCLE(8); break; case 0xE7: // ISB $?? MR_ZP(); ISB(); MW_ZP(); ADD_CYCLE(5); break; case 0xF7: // ISB $??,X MR_ZX(); ISB(); MW_ZP(); ADD_CYCLE(5); break; case 0xEF: // ISB $???? MR_AB(); ISB(); MW_EA(); ADD_CYCLE(5); break; case 0xFF: // ISB $????,X MR_AX(); ISB(); MW_EA(); ADD_CYCLE(5); break; case 0xFB: // ISB $????,Y MR_AY(); ISB(); MW_EA(); ADD_CYCLE(5); break; case 0xE3: // ISB ($??,X) MR_IX(); ISB(); MW_EA(); ADD_CYCLE(5); break; case 0xF3: // ISB ($??),Y MR_IY(); ISB(); MW_EA(); ADD_CYCLE(5); break; case 0xBB: // LAS $????,Y MR_AY(); LAS(); CHECK_EA(); ADD_CYCLE(4); break; case 0xA7: // LAX $?? MR_ZP(); LAX(); ADD_CYCLE(3); break; case 0xB7: // LAX $??,Y MR_ZY(); LAX(); ADD_CYCLE(4); break; case 0xAF: // LAX $???? MR_AB(); LAX(); ADD_CYCLE(4); break; case 0xBF: // LAX $????,Y MR_AY(); LAX(); CHECK_EA(); ADD_CYCLE(4); break; case 0xA3: // LAX ($??,X) MR_IX(); LAX(); ADD_CYCLE(6); break; case 0xB3: // LAX ($??),Y MR_IY(); LAX(); CHECK_EA(); ADD_CYCLE(5); break; case 0xAB: // LXA #$?? MR_IM(); LXA(); ADD_CYCLE(2); break; case 0x27: // RLA $?? MR_ZP(); RLA(); MW_ZP(); ADD_CYCLE(5); break; case 0x37: // RLA $??,X MR_ZX(); RLA(); MW_ZP(); ADD_CYCLE(6); break; case 0x2F: // RLA $???? MR_AB(); RLA(); MW_EA(); ADD_CYCLE(6); break; case 0x3F: // RLA $????,X MR_AX(); RLA(); MW_EA(); ADD_CYCLE(7); break; case 0x3B: // RLA $????,Y MR_AY(); RLA(); MW_EA(); ADD_CYCLE(7); break; case 0x23: // RLA ($??,X) MR_IX(); RLA(); MW_EA(); ADD_CYCLE(8); break; case 0x33: // RLA ($??),Y MR_IY(); RLA(); MW_EA(); ADD_CYCLE(8); break; case 0x67: // RRA $?? MR_ZP(); RRA(); MW_ZP(); ADD_CYCLE(5); break; case 0x77: // RRA $??,X MR_ZX(); RRA(); MW_ZP(); ADD_CYCLE(6); break; case 0x6F: // RRA $???? MR_AB(); RRA(); MW_EA(); ADD_CYCLE(6); break; case 0x7F: // RRA $????,X MR_AX(); RRA(); MW_EA(); ADD_CYCLE(7); break; case 0x7B: // RRA $????,Y MR_AY(); RRA(); MW_EA(); ADD_CYCLE(7); break; case 0x63: // RRA ($??,X) MR_IX(); RRA(); MW_EA(); ADD_CYCLE(8); break; case 0x73: // RRA ($??),Y MR_IY(); RRA(); MW_EA(); ADD_CYCLE(8); break; case 0x87: // SAX $?? MR_ZP(); SAX(); MW_ZP(); ADD_CYCLE(3); break; case 0x97: // SAX $??,Y MR_ZY(); SAX(); MW_ZP(); ADD_CYCLE(4); break; case 0x8F: // SAX $???? MR_AB(); SAX(); MW_EA(); ADD_CYCLE(4); break; case 0x83: // SAX ($??,X) MR_IX(); SAX(); MW_EA(); ADD_CYCLE(6); break; case 0xCB: // SBX #$?? MR_IM(); SBX(); ADD_CYCLE(2); break; case 0x9F: // SHA $????,Y MR_AY(); SHA(); MW_EA(); ADD_CYCLE(5); break; case 0x93: // SHA ($??),Y MR_IY(); SHA(); MW_EA(); ADD_CYCLE(6); break; case 0x9B: // SHS $????,Y MR_AY(); SHS(); MW_EA(); ADD_CYCLE(5); break; case 0x9E: // SHX $????,Y MR_AY(); SHX(); MW_EA(); ADD_CYCLE(5); break; case 0x9C: // SHY $????,X MR_AX(); SHY(); MW_EA(); ADD_CYCLE(5); break; case 0x07: // SLO $?? MR_ZP(); SLO(); MW_ZP(); ADD_CYCLE(5); break; case 0x17: // SLO $??,X MR_ZX(); SLO(); MW_ZP(); ADD_CYCLE(6); break; case 0x0F: // SLO $???? MR_AB(); SLO(); MW_EA(); ADD_CYCLE(6); break; case 0x1F: // SLO $????,X MR_AX(); SLO(); MW_EA(); ADD_CYCLE(7); break; case 0x1B: // SLO $????,Y MR_AY(); SLO(); MW_EA(); ADD_CYCLE(7); break; case 0x03: // SLO ($??,X) MR_IX(); SLO(); MW_EA(); ADD_CYCLE(8); break; case 0x13: // SLO ($??),Y MR_IY(); SLO(); MW_EA(); ADD_CYCLE(8); break; case 0x47: // SRE $?? MR_ZP(); SRE(); MW_ZP(); ADD_CYCLE(5); break; case 0x57: // SRE $??,X MR_ZX(); SRE(); MW_ZP(); ADD_CYCLE(6); break; case 0x4F: // SRE $???? MR_AB(); SRE(); MW_EA(); ADD_CYCLE(6); break; case 0x5F: // SRE $????,X MR_AX(); SRE(); MW_EA(); ADD_CYCLE(7); break; case 0x5B: // SRE $????,Y MR_AY(); SRE(); MW_EA(); ADD_CYCLE(7); break; case 0x43: // SRE ($??,X) MR_IX(); SRE(); MW_EA(); ADD_CYCLE(8); break; case 0x53: // SRE ($??),Y MR_IY(); SRE(); MW_EA(); ADD_CYCLE(8); break; case 0xEB: // SBC #$?? (Unofficial) MR_IM(); SBC(); ADD_CYCLE(2); break; case 0x1A: // NOP (Unofficial) case 0x3A: // NOP (Unofficial) case 0x5A: // NOP (Unofficial) case 0x7A: // NOP (Unofficial) case 0xDA: // NOP (Unofficial) case 0xFA: // NOP (Unofficial) ADD_CYCLE(2); break; case 0x80: // DOP (CYCLES 2) case 0x82: // DOP (CYCLES 2) case 0x89: // DOP (CYCLES 2) case 0xC2: // DOP (CYCLES 2) case 0xE2: // DOP (CYCLES 2) R.PC++; ADD_CYCLE(2); break; case 0x04: // DOP (CYCLES 3) case 0x44: // DOP (CYCLES 3) case 0x64: // DOP (CYCLES 3) R.PC++; ADD_CYCLE(3); break; case 0x14: // DOP (CYCLES 4) case 0x34: // DOP (CYCLES 4) case 0x54: // DOP (CYCLES 4) case 0x74: // DOP (CYCLES 4) case 0xD4: // DOP (CYCLES 4) case 0xF4: // DOP (CYCLES 4) R.PC++; ADD_CYCLE(4); break; case 0x0C: // TOP case 0x1C: // TOP case 0x3C: // TOP case 0x5C: // TOP case 0x7C: // TOP case 0xDC: // TOP case 0xFC: // TOP R.PC+=2; ADD_CYCLE(4); break; case 0x02: /* JAM */ case 0x12: /* JAM */ case 0x22: /* JAM */ case 0x32: /* JAM */ case 0x42: /* JAM */ case 0x52: /* JAM */ case 0x62: /* JAM */ case 0x72: /* JAM */ case 0x92: /* JAM */ case 0xB2: /* JAM */ case 0xD2: /* JAM */ case 0xF2: /* JAM */ default: if( !Config.emulator.bIllegalOp ) { throw CApp::GetErrorString( IDS_ERROR_ILLEGALOPCODE ); goto _execute_exit; } else { R.PC--; ADD_CYCLE(4); } break; // default: // __assume(0); } end_is: __asm nop; if( nmi_request ) { _NMI(); } else if( irq_request ) { _IRQ(); } request_cycles -= exec_cycles; TOTAL_cycles += exec_cycles; // 僋儘僢僋摨婜張棟 mapper->Clock( exec_cycles ); #if DPCM_SYNCCLOCK apu->SyncDPCM( exec_cycles ); #endif if( bClockProcess ) { nes->Clock( exec_cycles ); } // nes->Clock( exec_cycles ); } _execute_exit: #if !DPCM_SYNCCLOCK apu->SyncDPCM( TOTAL_cycles - OLD_cycles ); #endif return TOTAL_cycles - OLD_cycles; }
/*RRA*/ static void op_0x1f(Z80EX_CONTEXT *cpu) { RRA(); T_WAIT_UNTIL(4); return; }