static int
rs5c313_todr_settime_ymdhms(todr_chip_handle_t todr, struct clock_ymdhms *dt)
{
struct rs5c313_softc *sc = todr->cookie;
int retry;
int t;
int s;
s = splhigh();
rtc_begin(sc);
for (retry = 10; retry > 0; --retry) {
rtc_ce(sc, 1);
rs5c313_write_reg(sc, RS5C313_CTRL, sc->sc_ctrl[0]);
if ((rs5c313_read_reg(sc, RS5C313_CTRL) & CTRL_BSY) == 0)
break;
rtc_ce(sc, 0);
delay(1);
}
if (retry == 0) {
splx(s);
return EIO;
}
#define RTCSET(x, y) \
do { \
t = TOBCD(dt->dt_ ## y) & 0xff; \
rs5c313_write_reg(sc, RS5C313_ ## x ## 1, t & 0x0f); \
rs5c313_write_reg(sc, RS5C313_ ## x ## 10, (t >> 4) & 0x0f); \
} while (/* CONSTCOND */0)
RTCSET(SEC, sec);
RTCSET(MIN, min);
RTCSET(HOUR, hour);
RTCSET(DAY, day);
RTCSET(MON, mon);
#undef RTCSET
t = dt->dt_year % 100;
t = TOBCD(t);
rs5c313_write_reg(sc, RS5C313_YEAR1, t & 0x0f);
rs5c313_write_reg(sc, RS5C313_YEAR10, (t >> 4) & 0x0f);
rs5c313_write_reg(sc, RS5C313_WDAY, dt->dt_wday);
rtc_ce(sc, 0);
splx(s);
sc->sc_valid = 1;
return 0;
}
void
sh_rtc_set(void *cookie, struct clock_ymdhms *dt)
{
uint8_t r;
/* stop clock */
r = _reg_read_1(SH_(RCR2));
r |= SH_RCR2_RESET;
r &= ~SH_RCR2_START;
_reg_write_1(SH_(RCR2), r);
/* set time */
if (CPU_IS_SH3)
_reg_write_1(SH3_RYRCNT, TOBCD(dt->dt_year % 100));
else
_reg_write_2(SH4_RYRCNT, TOBCD(dt->dt_year % 100));
#define RTCSET(x, y) _reg_write_1(SH_(R ## x ## CNT), TOBCD(dt->dt_ ## y))
RTCSET(MON, mon);
RTCSET(WK, wday);
RTCSET(DAY, day);
RTCSET(HR, hour);
RTCSET(MIN, min);
RTCSET(SEC, sec);
#undef RTCSET
/* start clock */
_reg_write_1(SH_(RCR2), r | SH_RCR2_START);
}
