/*
Description : Send PSMP Action frame If PSMP mode switches.
*/
VOID SendPSMPAction(
IN PRTMP_ADAPTER pAd,
IN UCHAR Wcid,
IN UCHAR Psmp)
{
PUCHAR pOutBuffer = NULL;
NDIS_STATUS NStatus;
//ULONG Idx;
FRAME_PSMP_ACTION Frame;
ULONG FrameLen;
#ifdef RT30xx
UCHAR bbpdata=0;
UINT32 macdata;
#endif // RT30xx //
NStatus = MlmeAllocateMemory(pAd, &pOutBuffer); //Get an unused nonpaged memory
if (NStatus != NDIS_STATUS_SUCCESS)
{
DBGPRINT(RT_DEBUG_ERROR,("BA - MlmeADDBAAction() allocate memory failed \n"));
return;
}
#ifdef CONFIG_STA_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
ActHeaderInit(pAd, &Frame.Hdr, pAd->CommonCfg.Bssid, pAd->CurrentAddress, pAd->MacTab.Content[Wcid].Addr);
#endif // CONFIG_STA_SUPPORT //
Frame.Category = CATEGORY_HT;
Frame.Action = SMPS_ACTION;
switch (Psmp)
{
case MMPS_ENABLE:
#ifdef RT30xx
if (IS_RT3090(pAd))
{
// disable MMPS BBP control register
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &bbpdata);
bbpdata &= ~(0x04); //bit 2
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, bbpdata);
// disable MMPS MAC control register
RTMP_IO_READ32(pAd, 0x1210, &macdata);
macdata &= ~(0x09); //bit 0, 3
RTMP_IO_WRITE32(pAd, 0x1210, macdata);
}
#endif // RT30xx //
Frame.Psmp = 0;
break;
case MMPS_DYNAMIC:
#ifdef RT30xx
if (IS_RT3090(pAd))
{
// enable MMPS BBP control register
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &bbpdata);
bbpdata |= 0x04; //bit 2
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, bbpdata);
// enable MMPS MAC control register
RTMP_IO_READ32(pAd, 0x1210, &macdata);
macdata |= 0x09; //bit 0, 3
RTMP_IO_WRITE32(pAd, 0x1210, macdata);
}
#endif // RT30xx //
Frame.Psmp = 3;
break;
case MMPS_STATIC:
#ifdef RT30xx
if (IS_RT3090(pAd))
{
// enable MMPS BBP control register
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &bbpdata);
bbpdata |= 0x04; //bit 2
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, bbpdata);
// enable MMPS MAC control register
RTMP_IO_READ32(pAd, 0x1210, &macdata);
macdata |= 0x09; //bit 0, 3
RTMP_IO_WRITE32(pAd, 0x1210, macdata);
}
#endif // RT30xx //
Frame.Psmp = 1;
break;
}
MakeOutgoingFrame(pOutBuffer, &FrameLen,
sizeof(FRAME_PSMP_ACTION), &Frame,
END_OF_ARGS);
MiniportMMRequest(pAd, QID_AC_BE, pOutBuffer, FrameLen);
MlmeFreeMemory(pAd, pOutBuffer);
DBGPRINT(RT_DEBUG_ERROR,("HT - SendPSMPAction( %d ) \n", Frame.Psmp));
}
static void ChgSignalStrengthLed(
IN PRTMP_ADAPTER pAd)
{
RTMP_IO_WRITE32(pAd, GPIO_DIR, 0x00); /* set GPIO to output. */
RTMP_IO_WRITE32(pAd, GPIO_DAT, (pAd->LedCntl.SWMCULedCntl.GPIOPolarity ? pAd->LedCntl.SWMCULedCntl.SignalStrength : ~pAd->LedCntl.SWMCULedCntl.SignalStrength));
}
VOID NICInitRT3370RFRegisters(IN PRTMP_ADAPTER pAd)
{
INT i;
UINT8 RfReg = 0;
UINT32 data;
CHAR bbpreg;
/* Driver must read EEPROM to get RfIcType before initial RF registers*/
/* Initialize RF register to default value*/
/* Init RF calibration*/
/* Driver should toggle RF R30 bit7 before init RF registers*/
RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg);
RfReg |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
RTMPusecDelay(1000);
RfReg &= 0x7F;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
for (i = 0; i < RT3370_NUM_RF_REG_PARMS; i++)
{
RT30xxWriteRFRegister(pAd, RT3370_RFRegTable[i].Register, RT3370_RFRegTable[i].Value);
}
/* Driver should set RF R6 bit6 on before init RF registers */
RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg);
RfReg |= 0x40;
RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg);
/* RT3071 version E has fixed this issue*/
if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211))
{
/* patch tx EVM issue temporarily*/
RTUSBReadMACRegister(pAd, LDO_CFG0, &data);
data = ((data & 0xE0FFFFFF) | 0x0D000000);
RTUSBWriteMACRegister(pAd, LDO_CFG0, data);
}
else
{
/* patch CCK ok, OFDM failed issue, just toggle and restore LDO_CFG0.*/
RTUSBReadMACRegister(pAd, LDO_CFG0, &data);
data = ((data & 0xE0FFFFFF) | 0x0D000000);
RTUSBWriteMACRegister(pAd, LDO_CFG0, data);
RTMPusecDelay(1000);
data = ((data & 0xE0FFFFFF) | 0x01000000);
RTUSBWriteMACRegister(pAd, LDO_CFG0, data);
}
/* patch LNA_PE_G1 failed issue*/
RTMP_IO_READ32(pAd, GPIO_SWITCH, &data);
data &= ~(0x20);
RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data);
if (IS_RT3390(pAd)) /* Disable RF filter calibration*/
{
pAd->Mlme.CaliBW20RfR24 = BW20RFR24;
pAd->Mlme.CaliBW40RfR24 = BW40RFR24;
pAd->Mlme.CaliBW20RfR31 = BW20RFR31;
pAd->Mlme.CaliBW40RfR31 = BW40RFR31;
}
else
{
/*For RF filter Calibration*/
/*RTMPFilterCalibration(pAd);*/
}
/* set led open drain enable*/
RTMP_IO_READ32(pAd, OPT_14, &data);
data |= 0x01;
RTMP_IO_WRITE32(pAd, OPT_14, data);
/* set default antenna as main*/
if (pAd->RfIcType == RFIC_3320)
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
/*
From RT3071 Power Sequence v1.1 document, the Normal Operation Setting Registers as follow :
BBP_R138 / RF_R1 / RF_R15 / RF_R17 / RF_R20 / RF_R21.
*/
/* add by johnli, RF power sequence setup, load RF normal operation-mode setup*/
RT33xxLoadRFNormalModeSetup(pAd);
}
/*
==========================================================================
Description:
Reverse RF sleep-mode setup
==========================================================================
*/
VOID RT30xxReverseRFSleepModeSetup(
IN PRTMP_ADAPTER pAd)
{
UCHAR RFValue;
UINT32 MACValue;
if(!IS_RT3572(pAd))
{
#ifdef RT53xx
if (IS_RT5390(pAd))
{
UCHAR rfreg;
RT30xxReadRFRegister(pAd, RF_R01, &rfreg);
if (IS_RT5392(pAd))
{
rfreg = ((rfreg & ~0x3F) | 0x3F);
}
else
{
rfreg = ((rfreg & ~0x0F) | 0x0F); // Enable rf_block_en, pll_en, rx0_en and tx0_en
}
RT30xxWriteRFRegister(pAd, RF_R01, rfreg);
RT30xxReadRFRegister(pAd, RF_R06, &rfreg);
if (IS_RT5390F(pAd) || IS_RT5392C(pAd))
{
rfreg = ((rfreg & ~0xC0) | 0xC0); // vco_ic (VCO bias current control, 11: high)
}
else
{
rfreg = ((rfreg & ~0xC0) | 0x80); // vco_ic (VCO bias current control, 10: mid.)
}
RT30xxWriteRFRegister(pAd, RF_R06, rfreg);
if (!IS_RT5392(pAd))
{
RT30xxReadRFRegister(pAd, RF_R02, &rfreg);
rfreg = ((rfreg & ~0x80) | 0x80); // rescal_en (initiate calibration)
RT30xxWriteRFRegister(pAd, RF_R02, rfreg);
}
RT30xxReadRFRegister(pAd, RF_R22, &rfreg);
rfreg = ((rfreg & ~0xE0) | 0x20); // cp_ic (reference current control, 001: 0.33 mA)
RT30xxWriteRFRegister(pAd, RF_R22, rfreg);
RT30xxReadRFRegister(pAd, RF_R42, &rfreg);
rfreg = ((rfreg & ~0x40) | 0x40); // rx_ctb_en
RT30xxWriteRFRegister(pAd, RF_R42, rfreg);
RT30xxReadRFRegister(pAd, RF_R20, &rfreg);
rfreg = ((rfreg & ~0x77) | 0x00); // ldo_rf_vc and ldo_pll_vc ( 111: +0.15)
RT30xxWriteRFRegister(pAd, RF_R20, rfreg);
RT30xxReadRFRegister(pAd, RF_R03, &rfreg);
rfreg = ((rfreg & ~0x80) | 0x80); // vcocal_en (initiate VCO calibration (reset after completion))
RT30xxWriteRFRegister(pAd, RF_R03, rfreg);
}
else
#endif // RT53xx //
{
// RF_BLOCK_en, RF R1 register Bit 0 to 1
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue |= 0x01;
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
// VCO_IC, RF R7 register Bit 5 to 1 (VCO bias current control, 11: high)
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue |= 0x30;
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
// Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1
RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
RFValue |= 0x0E;
RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
// RX_CTB_en, RF R21 register Bit 7 to 1
RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
RFValue |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
}
}
if (IS_RT3090(pAd) || // IS_RT3090 including RT309x and RT3071/72
IS_RT3572(pAd) ||
IS_RT3390(pAd) ||
IS_RT3593(pAd) ||
IS_RT5390(pAd) ||
(IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201)))
{
if ((!IS_RT3572(pAd)) && (!IS_RT3593(pAd)) && (!IS_RT5390(pAd)) && (!IS_RT3390(pAd)) && (!IS_RT3090(pAd)))
{
RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
if ((pAd->MACVersion & 0xffff) < 0x0211)
RFValue = (RFValue & (~0x77)) | 0x3;
else
RFValue = (RFValue & (~0x77));
RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
}
// RT3071 version E has fixed this issue
if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211))
{
// patch tx EVM issue temporarily
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue = ((MACValue & 0xE0FFFFFF) | 0x0D000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
// else if ((!IS_RT3090(pAd) && !IS_RT3593(pAd)) || (pAd->CommonCfg.PatchHWControl.field.LDOCfg == 1))
else if ((!IS_RT3090(pAd) && !IS_RT3593(pAd) && !IS_RT5390(pAd)))
{
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue = ((MACValue & 0xE0FFFFFF) | 0x01000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
}
if(IS_RT3572(pAd))
RT30xxWriteRFRegister(pAd, RF_R08, 0x80);
}
/*
==========================================================================
Description:
AsicSwitchChannel() dedicated for RT28xx ATE.
==========================================================================
*/
VOID RT28xxATEAsicSwitchChannel(
IN PRTMP_ADAPTER pAd)
{
PATE_INFO pATEInfo = &(pAd->ate);
UINT32 Value = 0;
CHAR TxPwer = 0, TxPwer2 = 0;
UCHAR index = 0, BbpValue = 0, Channel = 0;
UINT32 R2 = 0, R3 = DEFAULT_RF_TX_POWER, R4 = 0;
RTMP_RF_REGS *RFRegTable = NULL;
SYNC_CHANNEL_WITH_QA(pATEInfo, &Channel);
/* fill Tx power value */
TxPwer = pATEInfo->TxPower0;
TxPwer2 = pATEInfo->TxPower1;
RFRegTable = RF2850RegTable;
switch (pAd->RfIcType)
{
/* But only 2850 and 2750 support 5.5GHz band... */
case RFIC_2820:
case RFIC_2850:
case RFIC_2720:
case RFIC_2750:
for (index = 0; index < NUM_OF_2850_CHNL; index++)
{
if (Channel == RFRegTable[index].Channel)
{
R2 = RFRegTable[index].R2;
/* If TX path is 1, bit 14 = 1. */
if (pAd->Antenna.field.TxPath == 1)
{
R2 |= 0x4000;
}
if (pAd->Antenna.field.TxPath == 2)
{
if (pATEInfo->TxAntennaSel == 1)
{
/* If TX Antenna select is 1 , bit 14 = 1; Disable Ant 2 */
R2 |= 0x4000;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpValue);
BbpValue &= 0xE7; /* 11100111B */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpValue);
}
else if (pATEInfo->TxAntennaSel == 2)
{
/* If TX Antenna select is 2 , bit 15 = 1; Disable Ant 1 */
R2 |= 0x8000;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpValue);
BbpValue &= 0xE7;
BbpValue |= 0x08;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpValue);
}
else
{
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpValue);
BbpValue &= 0xE7;
BbpValue |= 0x10;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpValue);
}
}
if (pAd->Antenna.field.RxPath == 2)
{
switch (pATEInfo->RxAntennaSel)
{
case 1:
R2 |= 0x20040;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
BbpValue |= 0x00;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
case 2:
R2 |= 0x10040;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
BbpValue |= 0x01;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
default:
R2 |= 0x40;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
/* Only enable two Antenna to receive. */
BbpValue |= 0x08;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
}
}
else if (pAd->Antenna.field.RxPath == 1)
{
/* write 1 to off RxPath */
R2 |= 0x20040;
}
if (pAd->Antenna.field.RxPath == 3)
{
switch (pATEInfo->RxAntennaSel)
{
case 1:
R2 |= 0x20040;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
BbpValue |= 0x00;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
case 2:
R2 |= 0x10040;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
BbpValue |= 0x01;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
case 3:
R2 |= 0x30000;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
BbpValue |= 0x02;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
default:
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
BbpValue |= 0x10;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
}
}
if (Channel > 14)
{
/* initialize R3, R4 */
R3 = (RFRegTable[index].R3 & 0xffffc1ff);
R4 = (RFRegTable[index].R4 & (~0x001f87c0)) | (pATEInfo->RFFreqOffset << 15);
/*
According the Rory's suggestion to solve the middle range issue.
5.5G band power range : 0xF9~0X0F, TX0 Reg3 bit9/TX1 Reg4 bit6="0"
means the TX power reduce 7dB.
*/
/* R3 */
if ((TxPwer >= -7) && (TxPwer < 0))
{
TxPwer = (7+TxPwer);
R3 |= (TxPwer << 10);
DBGPRINT(RT_DEBUG_TRACE, ("ATEAsicSwitchChannel: TxPwer=%d \n", TxPwer));
}
else
{
TxPwer = (TxPwer > 0xF) ? (0xF) : (TxPwer);
R3 |= (TxPwer << 10) | (1 << 9);
}
/* R4 */
if ((TxPwer2 >= -7) && (TxPwer2 < 0))
{
TxPwer2 = (7+TxPwer2);
R4 |= (TxPwer2 << 7);
DBGPRINT(RT_DEBUG_TRACE, ("ATEAsicSwitchChannel: TxPwer2=%d \n", TxPwer2));
}
else
{
TxPwer2 = (TxPwer2 > 0xF) ? (0xF) : (TxPwer2);
R4 |= (TxPwer2 << 7) | (1 << 6);
}
}
else
{
/* Set TX power0. */
R3 = (RFRegTable[index].R3 & 0xffffc1ff) | (TxPwer << 9);
/* Set frequency offset and TX power1. */
R4 = (RFRegTable[index].R4 & (~0x001f87c0)) | (pATEInfo->RFFreqOffset << 15) | (TxPwer2 <<6);
}
/* based on BBP current mode before changing RF channel */
if (pATEInfo->TxWI.BW == BW_40)
{
R4 |=0x200000;
}
/* Update variables. */
pAd->LatchRfRegs.Channel = Channel;
pAd->hw_cfg.lan_gain = GET_LNA_GAIN(pAd);
pAd->LatchRfRegs.R1 = RFRegTable[index].R1;
pAd->LatchRfRegs.R2 = R2;
pAd->LatchRfRegs.R3 = R3;
pAd->LatchRfRegs.R4 = R4;
RtmpRfIoWrite(pAd);
break;
}
}
break;
default:
break;
}
/* Change BBP setting during switch from a->g, g->a */
if (Channel <= 14)
{
UINT32 TxPinCfg = 0x00050F0A;/* 2007.10.09 by Brian : 0x0005050A ==> 0x00050F0A */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - pAd->hw_cfg.lan_gain));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - pAd->hw_cfg.lan_gain));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - pAd->hw_cfg.lan_gain));
/* According the Rory's suggestion to solve the middle range issue. */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);
/* Rx High power VGA offset for LNA select */
if (pAd->NicConfig2.field.ExternalLNAForG)
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
/* 2.4 G band selection PIN */
rtmp_mac_set_band(pAd, BAND_24G);
/* Turn off unused PA or LNA when only 1T or 1R. */
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
/* calibration power unbalance issues */
if (pAd->Antenna.field.TxPath == 2)
{
if (pATEInfo->TxAntennaSel == 1)
{
TxPinCfg &= 0xFFFFFFF7;
}
else if (pATEInfo->TxAntennaSel == 2)
{
TxPinCfg &= 0xFFFFFFFD;
}
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
/* channel > 14 */
else
{
UINT32 TxPinCfg = 0x00050F05;/* 2007.10.09 by Brian : 0x00050505 ==> 0x00050F05 */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - pAd->hw_cfg.lan_gain));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - pAd->hw_cfg.lan_gain));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - pAd->hw_cfg.lan_gain));
/* According the Rory's suggestion to solve the middle range issue. */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0xF2);
/* Rx High power VGA offset for LNA select */
if (pAd->NicConfig2.field.ExternalLNAForA)
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R91, &BbpValue);
ASSERT((BbpValue == 0x04));
/* 5 G band selection PIN, bit1 and bit2 are complement */
rtmp_mac_set_band(pAd, BAND_5G);
/* Turn off unused PA or LNA when only 1T or 1R. */
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
ATE_CHIP_RX_VGA_GAIN_INIT(pAd);
#ifdef RELEASE_EXCLUDE
/*
On 11A, We should delay and wait RF/BBP to be stable
and the appropriate time should be 1000 micro seconds.
2005/06/05 - On 11G, We also need this delay time.
Otherwise it's difficult to pass the WHQL.
*/
#endif /* RELEASE_EXCLUDE */
RtmpOsMsDelay(1);
#ifndef RTMP_RF_RW_SUPPORT
if (Channel > 14)
{
/* When 5.5GHz band the LSB of TxPwr will be used to reduced 7dB or not. */
DBGPRINT(RT_DEBUG_TRACE, ("RT28xx:SwitchChannel#%d(RF=%d, %dT) to , R1=0x%08x, R2=0x%08x, R3=0x%08x, R4=0x%08x\n",
Channel,
pAd->RfIcType,
pAd->Antenna.field.TxPath,
pAd->LatchRfRegs.R1,
pAd->LatchRfRegs.R2,
pAd->LatchRfRegs.R3,
pAd->LatchRfRegs.R4));
}
else
{
DBGPRINT(RT_DEBUG_TRACE, ("RT28xx:SwitchChannel#%d(RF=%d, Pwr0=%u, Pwr1=%u, %dT) to , R1=0x%08x, R2=0x%08x, R3=0x%08x, R4=0x%08x\n",
Channel,
pAd->RfIcType,
(R3 & 0x00003e00) >> 9,
(R4 & 0x000007c0) >> 6,
pAd->Antenna.field.TxPath,
pAd->LatchRfRegs.R1,
pAd->LatchRfRegs.R2,
pAd->LatchRfRegs.R3,
pAd->LatchRfRegs.R4));
}
#endif /* !RTMP_RF_RW_SUPPORT */
}
/* Before switch channel, driver needs doing channel switch announcement.*/
VOID RadarDetectPeriodic(
IN PRTMP_ADAPTER pAd)
{
#ifdef RT2880
ULONG Value;
/* Roger add to fix false detection(long pulse only) in the first 60 seconds */
if (pAd->CommonCfg.W56_debug)
{
if (pAd->CommonCfg.W56_idx < 300)
{
pAd->CommonCfg.RadarElectNum = 5;
}
else if (pAd->CommonCfg.W56_total <= 5000)
{
if (pAd->CommonCfg.RadarElectNum > 4)
pAd->CommonCfg.RadarElectNum--;
else
pAd->CommonCfg.RadarElectNum = 3;
}
else if (pAd->CommonCfg.W56_total <= 10000)
{
if (pAd->CommonCfg.RadarElectNum > 5)
pAd->CommonCfg.RadarElectNum--;
else
pAd->CommonCfg.RadarElectNum = 4;
}
else if (pAd->CommonCfg.W56_total <= 20000)
{
if (pAd->CommonCfg.RadarElectNum > 7)
pAd->CommonCfg.RadarElectNum--;
else if (pAd->CommonCfg.RadarElectNum < 5)
pAd->CommonCfg.RadarElectNum++;
else
pAd->CommonCfg.RadarElectNum = 6;
}
else if (pAd->CommonCfg.W56_total <= 30000)
{
if (pAd->CommonCfg.RadarElectNum > 8)
pAd->CommonCfg.RadarElectNum--;
else if (pAd->CommonCfg.RadarElectNum < 6)
pAd->CommonCfg.RadarElectNum++;
else
pAd->CommonCfg.RadarElectNum = 7;
}
else if (pAd->CommonCfg.W56_total <= 50000)
{
if (pAd->CommonCfg.RadarElectNum > 9)
pAd->CommonCfg.RadarElectNum--;
else if (pAd->CommonCfg.RadarElectNum < 6)
pAd->CommonCfg.RadarElectNum++;
else
pAd->CommonCfg.RadarElectNum = 8;
}
else if (pAd->CommonCfg.W56_total <= 70000)
{
if (pAd->CommonCfg.RadarElectNum > 7)
pAd->CommonCfg.RadarElectNum--;
else if (pAd->CommonCfg.RadarElectNum < 8)
pAd->CommonCfg.RadarElectNum++;
else
pAd->CommonCfg.RadarElectNum = 9;
}
else
{
if (pAd->CommonCfg.RadarElectNum < 9)
pAd->CommonCfg.RadarElectNum++;
else
pAd->CommonCfg.RadarElectNum = 10;
}
}
#endif /* RT2880 */
/* need to check channel availability, after switch channel*/
if (pAd->CommonCfg.RadarDetect.RDMode != RD_SILENCE_MODE)
return;
#ifdef RT2880
#ifdef DFS_SOFTWARE_SUPPORT
if (pAd->CommonCfg.dfs_func < HARDWARE_DFS_V1)
{
/* Roger add to fix false detection(long pulse only) in the first 60 seconds */
if ((pAd->CommonCfg.RadarDetect.RDDurRegion == JAP_W56) || (pAd->CommonCfg.RadarDetect.RDDurRegion == FCC))
{
if (pAd->CommonCfg.W56_debug == 0)
{
RTMP_IO_READ32(pAd, PBF_LIFE_TIMER, &pAd->CommonCfg.W56_hw_1);
RTMP_IO_READ32(pAd, CH_TIME_CFG, &Value);
RTMP_IO_WRITE32(pAd, CH_TIME_CFG, Value | 1);
pAd->CommonCfg.W56_hw_sum = 0;
pAd->CommonCfg.W56_idx = 0;
pAd->CommonCfg.W56_debug = 1;
}
}
}
#endif /* DFS_SOFTWARE_SUPPORT */
#endif /* RT2880 */
/* channel availability check time is 60sec, use 65 for assurance*/
if (pAd->CommonCfg.RadarDetect.RDCount++ > pAd->CommonCfg.RadarDetect.ChMovingTime)
{
DBGPRINT(RT_DEBUG_TRACE, ("Not found radar signal, start send beacon and radar detection in service monitor\n\n"));
#ifdef DFS_SOFTWARE_SUPPORT
if (pAd->CommonCfg.dfs_func < HARDWARE_DFS_V1)
BbpRadarDetectionStop(pAd);
#endif /* DFS_SOFTWARE_SUPPORT */
#ifdef RT2880
pAd->CommonCfg.R66 = pAd->CommonCfg.DFS_R66;
#endif /* RT2880 */
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
#ifdef CARRIER_DETECTION_SUPPORT
if (pAd->CommonCfg.CarrierDetect.Enable == TRUE)
{
/* trun on Carrier-Detection. (Carrier-Detect with CTS protection).*/
CARRIER_DETECT_START(pAd, 1);
}
#endif /* CARRIER_DETECTION_SUPPORT */
}
#endif /* CONFIG_AP_SUPPORT */
AsicEnableBssSync(pAd);
pAd->CommonCfg.RadarDetect.RDMode = RD_NORMAL_MODE;
#ifdef RT2880
#ifdef DFS_SOFTWARE_SUPPORT
if (pAd->CommonCfg.dfs_func < HARDWARE_DFS_V1)
{
if ((pAd->CommonCfg.RadarDetect.RDDurRegion == JAP_W56) || (pAd->CommonCfg.RadarDetect.RDDurRegion == FCC))
{
pAd->CommonCfg.W56_debug = 0;
RTMP_IO_READ32(pAd, CH_TIME_CFG, &Value);
if (Value & 1)
{
RTMP_IO_WRITE32(pAd, CH_TIME_CFG, Value & ~1);
}
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, 114, 0x02);
}
}
#endif /* DFS_SOFTWARE_SUPPORT */
#endif /* RT2880 */
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
#ifdef DFS_SUPPORT
#ifdef RTMP_RBUS_SUPPORT
#ifdef DFS_HARDWARE_SUPPORT
if ((pAd->MACVersion == 0x28720200) && (pAd->CommonCfg.CID == 0x200))
{
if (pAd->CommonCfg.RadarDetect.RDMode != RD_NORMAL_MODE)
{
return;
}
/*NewRadarDetectionStart(pAd);*/
}
else
#endif /* DFS_HARDWARE_SUPPORT */
#endif /* RTMP_RBUS_SUPPORT */
{
#ifdef DFS_SOFTWARE_SUPPORT
if (pAd->CommonCfg.dfs_func < HARDWARE_DFS_V1)
AdaptRadarDetection(pAd); /* start radar detection.*/
#endif /* DFS_SOFTWARE_SUPPORT */
}
#endif /* DFS_SUPPORT */
}
#endif /* CONFIG_AP_SUPPORT */
return;
}
/*
========================================================================
Routine Description: Write RT30xx RF register through MAC
Arguments:
Return Value:
IRQL =
Note:
========================================================================
*/
NDIS_STATUS RT30xxWriteRFRegister(
IN PRTMP_ADAPTER pAd,
IN UCHAR regID,
IN UCHAR value)
{
RF_CSR_CFG_STRUC rfcsr = { { 0 } };
UINT i = 0;
#ifdef RTMP_MAC_PCI
if ((pAd->bPCIclkOff == TRUE) || (pAd->LastMCUCmd == SLEEP_MCU_CMD))
{
DBGPRINT_ERR(("RT30xxWriteRFRegister. Not allow to write RF 0x%x : fail\n", regID));
return STATUS_UNSUCCESSFUL;
}
#endif /* RTMP_MAC_PCI */
ASSERT((regID <= pAd->chipCap.MaxNumOfRfId));
do
{
RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word);
if (!rfcsr.field.RF_CSR_KICK)
break;
i++;
}
while ((i < MAX_BUSY_COUNT) && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)));
if ((i == MAX_BUSY_COUNT) || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)))
{
DBGPRINT_RAW(RT_DEBUG_ERROR, ("Retry count exhausted or device removed!!!\n"));
return STATUS_UNSUCCESSFUL;
}
rfcsr.field.RF_CSR_WR = 1;
rfcsr.field.RF_CSR_KICK = 1;
rfcsr.field.TESTCSR_RFACC_REGNUM = regID;
if ((pAd->chipCap.RfReg17WtMethod == RF_REG_WT_METHOD_STEP_ON) && (regID == RF_R17))
{
UCHAR IdRf;
UCHAR RfValue;
BOOLEAN beAdd;
RT30xxReadRFRegister(pAd, RF_R17, &RfValue);
beAdd = (RfValue < value) ? TRUE : FALSE;
IdRf = RfValue;
while(IdRf != value)
{
if (beAdd)
IdRf++;
else
IdRf--;
rfcsr.field.RF_CSR_DATA = IdRf;
RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
RtmpOsMsDelay(1);
}
}
rfcsr.field.RF_CSR_DATA = value;
RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
return NDIS_STATUS_SUCCESS;
}
NDIS_STATUS MlmeHardTransmitTxRing(
IN PRTMP_ADAPTER pAd,
IN UCHAR QueIdx,
IN PNDIS_PACKET pPacket)
{
PACKET_INFO PacketInfo;
PUCHAR pSrcBufVA;
UINT SrcBufLen;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
PHEADER_802_11 pHeader_802_11;
BOOLEAN bAckRequired, bInsertTimestamp;
ULONG SrcBufPA;
//UCHAR TxBufIdx;
UCHAR MlmeRate;
ULONG SwIdx = pAd->TxRing[QueIdx].TxCpuIdx;
PTXWI_STRUC pFirstTxWI;
//ULONG i;
//HTTRANSMIT_SETTING MlmeTransmit; //Rate for this MGMT frame.
ULONG FreeNum;
MAC_TABLE_ENTRY *pMacEntry = NULL;
RTMP_QueryPacketInfo(pPacket, &PacketInfo, &pSrcBufVA, &SrcBufLen);
if (pSrcBufVA == NULL)
{
// The buffer shouldn't be NULL
return NDIS_STATUS_FAILURE;
}
// Make sure MGMT ring resource won't be used by other threads
//NdisAcquireSpinLock(&pAd->TxRingLock);
FreeNum = GET_TXRING_FREENO(pAd, QueIdx);
if (FreeNum == 0)
{
//NdisReleaseSpinLock(&pAd->TxRingLock);
return NDIS_STATUS_FAILURE;
}
SwIdx = pAd->TxRing[QueIdx].TxCpuIdx;
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) pAd->TxRing[QueIdx].Cell[SwIdx].AllocVa;
#else
pDestTxD = (PTXD_STRUC)pAd->TxRing[QueIdx].Cell[SwIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
if (pAd->TxRing[QueIdx].Cell[SwIdx].pNdisPacket)
{
DBGPRINT(RT_DEBUG_OFF, ("MlmeHardTransmit Error\n"));
//NdisReleaseSpinLock(&pAd->TxRingLock);
return NDIS_STATUS_FAILURE;
}
#ifdef CONFIG_STA_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
{
// outgoing frame always wakeup PHY to prevent frame lost
// if (pAd->StaCfg.Psm == PWR_SAVE)
if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE))
AsicForceWakeup(pAd, TRUE);
}
#endif // CONFIG_STA_SUPPORT //
pFirstTxWI =(PTXWI_STRUC)pSrcBufVA;
pHeader_802_11 = (PHEADER_802_11) (pSrcBufVA + TXWI_SIZE);
if (pHeader_802_11->Addr1[0] & 0x01)
{
MlmeRate = pAd->CommonCfg.BasicMlmeRate;
}
else
{
MlmeRate = pAd->CommonCfg.MlmeRate;
}
if ((pHeader_802_11->FC.Type == BTYPE_DATA) &&
(pHeader_802_11->FC.SubType == SUBTYPE_QOS_NULL))
{
pMacEntry = MacTableLookup(pAd, pHeader_802_11->Addr1);
}
// Verify Mlme rate for a / g bands.
if ((pAd->LatchRfRegs.Channel > 14) && (MlmeRate < RATE_6)) // 11A band
MlmeRate = RATE_6;
//
// Should not be hard code to set PwrMgmt to 0 (PWR_ACTIVE)
// Snice it's been set to 0 while on MgtMacHeaderInit
// By the way this will cause frame to be send on PWR_SAVE failed.
//
//
// In WMM-UAPSD, mlme frame should be set psm as power saving but probe request frame
#ifdef CONFIG_STA_SUPPORT
// Data-Null packets alse pass through MMRequest in RT2860, however, we hope control the psm bit to pass APSD
if (pHeader_802_11->FC.Type != BTYPE_DATA)
{
if ((pHeader_802_11->FC.SubType == SUBTYPE_PROBE_REQ) || !(pAd->CommonCfg.bAPSDCapable && pAd->CommonCfg.APEdcaParm.bAPSDCapable))
{
pHeader_802_11->FC.PwrMgmt = PWR_ACTIVE;
}
else
{
pHeader_802_11->FC.PwrMgmt = pAd->CommonCfg.bAPSDForcePowerSave;
}
}
#endif // CONFIG_STA_SUPPORT //
bInsertTimestamp = FALSE;
if (pHeader_802_11->FC.Type == BTYPE_CNTL) // must be PS-POLL
{
bAckRequired = FALSE;
}
else // BTYPE_MGMT or BTYPE_DATA(must be NULL frame)
{
if (pHeader_802_11->Addr1[0] & 0x01) // MULTICAST, BROADCAST
{
bAckRequired = FALSE;
pHeader_802_11->Duration = 0;
}
else
{
bAckRequired = TRUE;
pHeader_802_11->Duration = RTMPCalcDuration(pAd, MlmeRate, 14);
if (pHeader_802_11->FC.SubType == SUBTYPE_PROBE_RSP)
{
bInsertTimestamp = TRUE;
}
}
}
pHeader_802_11->Sequence = pAd->Sequence++;
if (pAd->Sequence > 0xfff)
pAd->Sequence = 0;
// Before radar detection done, mgmt frame can not be sent but probe req
// Because we need to use probe req to trigger driver to send probe req in passive scan
if ((pHeader_802_11->FC.SubType != SUBTYPE_PROBE_REQ)
&& (pAd->CommonCfg.bIEEE80211H == 1)
&& (pAd->CommonCfg.RadarDetect.RDMode != RD_NORMAL_MODE))
{
DBGPRINT(RT_DEBUG_ERROR,("MlmeHardTransmit --> radar detect not in normal mode !!!\n"));
//NdisReleaseSpinLock(&pAd->TxRingLock);
return (NDIS_STATUS_FAILURE);
}
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader_802_11, DIR_WRITE, FALSE);
#endif
//
// fill scatter-and-gather buffer list into TXD. Internally created NDIS PACKET
// should always has only one ohysical buffer, and the whole frame size equals
// to the first scatter buffer size
//
// Initialize TX Descriptor
// For inter-frame gap, the number is for this frame and next frame
// For MLME rate, we will fix as 2Mb to match other vendor's implement
// pAd->CommonCfg.MlmeTransmit.field.MODE = 1;
// management frame doesn't need encryption. so use RESERVED_WCID no matter u are sending to specific wcid or not.
// Only beacon use Nseq=TRUE. So here we use Nseq=FALSE.
if (pMacEntry == NULL)
{
RTMPWriteTxWI(pAd, pFirstTxWI, FALSE, FALSE, bInsertTimestamp, FALSE, bAckRequired, FALSE,
0, RESERVED_WCID, (SrcBufLen - TXWI_SIZE), PID_MGMT, 0, (UCHAR)pAd->CommonCfg.MlmeTransmit.field.MCS, IFS_BACKOFF, FALSE, &pAd->CommonCfg.MlmeTransmit);
}
else
{
RTMPWriteTxWI(pAd, pFirstTxWI, FALSE, FALSE,
bInsertTimestamp, FALSE, bAckRequired, FALSE,
0, pMacEntry->Aid, (SrcBufLen - TXWI_SIZE),
pMacEntry->MaxHTPhyMode.field.MCS, 0,
(UCHAR)pMacEntry->MaxHTPhyMode.field.MCS,
IFS_BACKOFF, FALSE, &pMacEntry->MaxHTPhyMode);
}
pAd->TxRing[QueIdx].Cell[SwIdx].pNdisPacket = pPacket;
pAd->TxRing[QueIdx].Cell[SwIdx].pNextNdisPacket = NULL;
// pFirstTxWI->MPDUtotalByteCount = SrcBufLen - TXWI_SIZE;
#ifdef RT_BIG_ENDIAN
RTMPWIEndianChange((PUCHAR)pFirstTxWI, TYPE_TXWI);
#endif
SrcBufPA = PCI_MAP_SINGLE(pAd, pSrcBufVA, SrcBufLen, 0, PCI_DMA_TODEVICE);
RTMPWriteTxDescriptor(pAd, pTxD, TRUE, FIFO_EDCA);
pTxD->LastSec0 = 1;
pTxD->LastSec1 = 1;
pTxD->SDLen0 = SrcBufLen;
pTxD->SDLen1 = 0;
pTxD->SDPtr0 = SrcBufPA;
pTxD->DMADONE = 0;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif
pAd->RalinkCounters.KickTxCount++;
pAd->RalinkCounters.OneSecTxDoneCount++;
// Increase TX_CTX_IDX, but write to register later.
INC_RING_INDEX(pAd->TxRing[QueIdx].TxCpuIdx, TX_RING_SIZE);
RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QueIdx*0x10, pAd->TxRing[QueIdx].TxCpuIdx);
// Make sure to release MGMT ring resource
// NdisReleaseSpinLock(&pAd->TxRingLock);
return NDIS_STATUS_SUCCESS;
}
/*
Must be run in Interrupt context
This function handle PCI specific TxDesc and cpu index update and kick the packet out.
*/
int RtmpPCIMgmtKickOut(
IN RTMP_ADAPTER *pAd,
IN UCHAR QueIdx,
IN PNDIS_PACKET pPacket,
IN PUCHAR pSrcBufVA,
IN UINT SrcBufLen)
{
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
TXD_STRUC TxD;
#endif
ULONG SwIdx = pAd->MgmtRing.TxCpuIdx;
#ifdef RT_BIG_ENDIAN
pDestTxD = (PTXD_STRUC)pAd->MgmtRing.Cell[SwIdx].AllocVa;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#else
pTxD = (PTXD_STRUC) pAd->MgmtRing.Cell[SwIdx].AllocVa;
#endif
pAd->MgmtRing.Cell[SwIdx].pNdisPacket = pPacket;
pAd->MgmtRing.Cell[SwIdx].pNextNdisPacket = NULL;
RTMPWriteTxDescriptor(pAd, pTxD, TRUE, FIFO_MGMT);
pTxD->LastSec0 = 1;
pTxD->LastSec1 = 1;
pTxD->DMADONE = 0;
pTxD->SDLen1 = 0;
pTxD->SDPtr0 = PCI_MAP_SINGLE(pAd, pSrcBufVA, SrcBufLen, 0, PCI_DMA_TODEVICE);
pTxD->SDLen0 = SrcBufLen;
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD);
#endif
//==================================================================
/* DBGPRINT_RAW(RT_DEBUG_TRACE, ("MLMEHardTransmit\n"));
for (i = 0; i < (TXWI_SIZE+24); i++)
{
DBGPRINT_RAW(RT_DEBUG_TRACE, ("%x:", *(pSrcBufVA+i)));
if ( i%4 == 3)
DBGPRINT_RAW(RT_DEBUG_TRACE, (" :: "));
if ( i%16 == 15)
DBGPRINT_RAW(RT_DEBUG_TRACE, ("\n "));
}
DBGPRINT_RAW(RT_DEBUG_TRACE, ("\n "));*/
//=======================================================================
pAd->RalinkCounters.KickTxCount++;
pAd->RalinkCounters.OneSecTxDoneCount++;
// Increase TX_CTX_IDX, but write to register later.
INC_RING_INDEX(pAd->MgmtRing.TxCpuIdx, MGMT_RING_SIZE);
RTMP_IO_WRITE32(pAd, TX_MGMTCTX_IDX, pAd->MgmtRing.TxCpuIdx);
return 0;
}
VOID RTMP_BBP_IO_READ8(
PRTMP_ADAPTER pAd,
UCHAR bbp_id,
UINT8 *pValue,
BOOLEAN bViaMCU)
{
BBP_CSR_CFG_STRUC BbpCsr;
int _busyCnt, _secCnt, _regID;
ULONG __IrqFlags = 0;
#ifdef RT65xx
if (IS_RT65XX(pAd))
return;
#endif /* RT65xx */
if ((bViaMCU) == TRUE)
RTMP_MAC_SHR_MSEL_PROTECT_LOCK(pAd, __IrqFlags);
_regID = ((bViaMCU) == TRUE ? H2M_BBP_AGENT : BBP_CSR_CFG);
for (_busyCnt=0; _busyCnt<MAX_BUSY_COUNT; _busyCnt++)
{
RTMP_IO_READ32(pAd, _regID, &BbpCsr.word);
if (BbpCsr.field.Busy == BUSY)
continue;
BbpCsr.word = 0;
BbpCsr.field.fRead = 1;
BbpCsr.field.BBP_RW_MODE = 1;
BbpCsr.field.Busy = 1;
BbpCsr.field.RegNum = bbp_id;
RTMP_IO_WRITE32(pAd, _regID, BbpCsr.word);
if ((bViaMCU) == TRUE)
{
AsicSendCommandToMcuBBP(pAd, 0x80, 0xff, 0x0, 0x0, FALSE);
/*RtmpusecDelay(1000);*/
}
for (_secCnt=0; _secCnt<MAX_BUSY_COUNT; _secCnt++)
{
RTMP_IO_READ32(pAd, _regID, &BbpCsr.word);
if (BbpCsr.field.Busy == IDLE)
break;
}
if ((BbpCsr.field.Busy == IDLE) && (BbpCsr.field.RegNum == bbp_id))
{
*pValue = (UCHAR)BbpCsr.field.Value;
break;
}
}
if (BbpCsr.field.Busy == BUSY)
{
DBGPRINT_ERR(("BBP(viaMCU=%d) read R%d fail\n", bViaMCU, bbp_id));
*pValue = pAd->BbpWriteLatch[bbp_id];
if (bViaMCU == TRUE)
{
RTMP_IO_READ32(pAd, _regID, &BbpCsr.word);
BbpCsr.field.Busy = 0;
RTMP_IO_WRITE32(pAd, _regID, BbpCsr.word);
}
}
if (bViaMCU == TRUE)
RTMP_MAC_SHR_MSEL_PROTECT_UNLOCK(pAd, __IrqFlags);
}
PNDIS_PACKET GetPacketFromRxRing(
IN PRTMP_ADAPTER pAd,
OUT PRT28XX_RXD_STRUC pSaveRxD,
OUT BOOLEAN *pbReschedule,
IN OUT UINT32 *pRxPending)
{
PRXD_STRUC pRxD;
#ifdef RT_BIG_ENDIAN
PRXD_STRUC pDestRxD;
RXD_STRUC RxD;
#endif
PNDIS_PACKET pRxPacket = NULL;
PNDIS_PACKET pNewPacket;
PVOID AllocVa;
NDIS_PHYSICAL_ADDRESS AllocPa;
BOOLEAN bReschedule = FALSE;
RTMP_DMACB *pRxCell;
RTMP_SEM_LOCK(&pAd->RxRingLock);
if (*pRxPending == 0)
{
// Get how may packets had been received
RTMP_IO_READ32(pAd, RX_DRX_IDX , &pAd->RxRing.RxDmaIdx);
if (pAd->RxRing.RxSwReadIdx == pAd->RxRing.RxDmaIdx)
{
// no more rx packets
bReschedule = FALSE;
goto done;
}
// get rx pending count
if (pAd->RxRing.RxDmaIdx > pAd->RxRing.RxSwReadIdx)
*pRxPending = pAd->RxRing.RxDmaIdx - pAd->RxRing.RxSwReadIdx;
else
*pRxPending = pAd->RxRing.RxDmaIdx + RX_RING_SIZE - pAd->RxRing.RxSwReadIdx;
}
pRxCell = &pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx];
#ifdef RT_BIG_ENDIAN
pDestRxD = (PRXD_STRUC) pRxCell->AllocVa;
RxD = *pDestRxD;
pRxD = &RxD;
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
#else
// Point to Rx indexed rx ring descriptor
pRxD = (PRXD_STRUC) pRxCell->AllocVa;
#endif
if (pRxD->DDONE == 0)
{
*pRxPending = 0;
// DMAIndx had done but DDONE bit not ready
bReschedule = TRUE;
goto done;
}
// return rx descriptor
NdisMoveMemory(pSaveRxD, pRxD, RXD_SIZE);
pNewPacket = RTMP_AllocateRxPacketBuffer(pAd, RX_BUFFER_AGGRESIZE, FALSE, &AllocVa, &AllocPa);
if (pNewPacket)
{
// unmap the rx buffer
PCI_UNMAP_SINGLE(pAd, pRxCell->DmaBuf.AllocPa,
pRxCell->DmaBuf.AllocSize, PCI_DMA_FROMDEVICE);
pRxPacket = pRxCell->pNdisPacket;
pRxCell->DmaBuf.AllocSize = RX_BUFFER_AGGRESIZE;
pRxCell->pNdisPacket = (PNDIS_PACKET) pNewPacket;
pRxCell->DmaBuf.AllocVa = AllocVa;
pRxCell->DmaBuf.AllocPa = AllocPa;
/* update SDP0 to new buffer of rx packet */
pRxD->SDP0 = AllocPa;
}
else
{
//DBGPRINT(RT_DEBUG_TRACE,("No Rx Buffer\n"));
pRxPacket = NULL;
bReschedule = TRUE;
}
pRxD->DDONE = 0;
// had handled one rx packet
*pRxPending = *pRxPending - 1;
// update rx descriptor and kick rx
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pRxD, TYPE_RXD);
WriteBackToDescriptor((PUCHAR)pDestRxD, (PUCHAR)pRxD, FALSE, TYPE_RXD);
#endif
INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
pAd->RxRing.RxCpuIdx = (pAd->RxRing.RxSwReadIdx == 0) ? (RX_RING_SIZE-1) : (pAd->RxRing.RxSwReadIdx-1);
RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
done:
RTMP_SEM_UNLOCK(&pAd->RxRingLock);
*pbReschedule = bReschedule;
return pRxPacket;
}
VOID RTMP_BBP_IO_WRITE8(
RTMP_ADAPTER *pAd,
UCHAR bbp_id,
UINT8 Value,
BOOLEAN bViaMCU)
{
BBP_CSR_CFG_STRUC BbpCsr;
int _busyCnt=0, _regID;
BOOLEAN brc;
ULONG __IrqFlags = 0;
#ifdef RT65xx
if (IS_RT65XX(pAd))
return;
#endif /* RT65xx */
if (bViaMCU == TRUE)
RTMP_MAC_SHR_MSEL_PROTECT_LOCK(pAd, __IrqFlags);
_regID = (bViaMCU == TRUE ? H2M_BBP_AGENT : BBP_CSR_CFG);
for (_busyCnt=1; _busyCnt<MAX_BUSY_COUNT; _busyCnt++)
{
RTMP_IO_READ32((pAd), _regID, &BbpCsr.word);
if (BbpCsr.field.Busy == BUSY)
{
if ( (bViaMCU == TRUE) && ((_busyCnt % 20) == 0))
{
BbpCsr.field.Busy = IDLE;
RTMP_IO_WRITE32(pAd, H2M_BBP_AGENT, BbpCsr.word);
}
continue;
}
BbpCsr.word = 0;
BbpCsr.field.fRead = 0;
BbpCsr.field.BBP_RW_MODE = 1;
BbpCsr.field.Busy = 1;
BbpCsr.field.Value = Value;
BbpCsr.field.RegNum = bbp_id;
RTMP_IO_WRITE32((pAd), _regID, BbpCsr.word);
if (bViaMCU == TRUE)
{
brc = AsicSendCommandToMcuBBP(pAd, 0x80, 0xff, 0x0, 0x0, FALSE);
if (pAd->OpMode == OPMODE_AP)
RtmpusecDelay(1000);
if (brc == FALSE)
{
BbpCsr.field.Busy = IDLE;
RTMP_IO_WRITE32(pAd, H2M_BBP_AGENT, BbpCsr.word);
}
}
pAd->BbpWriteLatch[bbp_id] = Value;
break;
}
if (_busyCnt == MAX_BUSY_COUNT)
{
DBGPRINT_ERR(("BBP write R%d fail\n", bbp_id));
if(bViaMCU == TRUE)
{
RTMP_IO_READ32(pAd, H2M_BBP_AGENT, &BbpCsr.word);
BbpCsr.field.Busy = 0;
RTMP_IO_WRITE32(pAd, H2M_BBP_AGENT, BbpCsr.word);
}
}
if (bViaMCU == TRUE)
RTMP_MAC_SHR_MSEL_PROTECT_UNLOCK(pAd, __IrqFlags);
}
BOOLEAN CFG80211DRV_OpsChgVirtualInf(RTMP_ADAPTER *pAd, VOID *pData)
{
PCFG80211_CTRL pCfg80211_ctrl = &pAd->cfg80211_ctrl;
CFG80211_CB *p80211CB = pAd->pCfg80211_CB;
UINT newType, oldType;
CMD_RTPRIV_IOCTL_80211_VIF_PARM *pVifParm;
pVifParm = (CMD_RTPRIV_IOCTL_80211_VIF_PARM *)pData;
newType = pVifParm->newIfType;
oldType = pVifParm->oldIfType;
#ifdef RT_CFG80211_P2P_CONCURRENT_DEVICE
/* After P2P NEGO phase, the device type may be change from GC to GO
or no change. We remove the GC in VIF list if nego as GO case.
*/
if ((newType == RT_CMD_80211_IFTYPE_P2P_GO) &&
(oldType == RT_CMD_80211_IFTYPE_P2P_CLIENT))
{
RTMP_CFG80211_VirtualIF_CancelP2pClient(pAd);
}
#endif /* RT_CFG80211_P2P_CONCURRENT_DEVICE */
#ifdef RT_CFG80211_P2P_SINGLE_DEVICE
CFG80211DBG(RT_DEBUG_TRACE, ("80211> @@@ Change from %u to %u Mode\n",oldType,newType));
pCfg80211_ctrl->P2POpStatusFlags = CFG_P2P_DISABLE;
if (newType == RT_CMD_80211_IFTYPE_P2P_CLIENT)
{
pCfg80211_ctrl->P2POpStatusFlags = CFG_P2P_CLI_UP;
}
else if (newType == RT_CMD_80211_IFTYPE_P2P_GO)
{
pCfg80211_ctrl->P2POpStatusFlags = CFG_P2P_GO_UP;
}
#endif /* RT_CFG80211_P2P_SINGLE_DEVICE */
#ifdef CONFIG_STA_SUPPORT
/* Change Device Type */
if (newType == RT_CMD_80211_IFTYPE_ADHOC)
{
Set_NetworkType_Proc(pAd, "Adhoc");
}
else if ((newType == RT_CMD_80211_IFTYPE_STATION) ||
(newType == RT_CMD_80211_IFTYPE_P2P_CLIENT))
{
CFG80211DBG(RT_DEBUG_TRACE, ("80211> Change the Interface to STA Mode\n"));
#ifdef CONFIG_AP_SUPPORT
if (pAd->cfg80211_ctrl.isCfgInApMode == RT_CMD_80211_IFTYPE_AP && RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_START_UP))
CFG80211DRV_DisableApInterface(pAd);
#endif /* CONFIG_AP_SUPPORT */
pAd->cfg80211_ctrl.isCfgInApMode = RT_CMD_80211_IFTYPE_STATION;
}
else
#endif /*CONFIG_STA_SUPPORT*/
if ((newType == RT_CMD_80211_IFTYPE_AP) ||
(newType == RT_CMD_80211_IFTYPE_P2P_GO))
{
CFG80211DBG(RT_DEBUG_TRACE, ("80211> Change the Interface to AP Mode\n"));
pAd->cfg80211_ctrl.isCfgInApMode = RT_CMD_80211_IFTYPE_AP;
}
#ifdef CONFIG_STA_SUPPORT
else if (newType == RT_CMD_80211_IFTYPE_MONITOR)
{
/* set packet filter */
Set_NetworkType_Proc(pAd, "Monitor");
if (pVifParm->MonFilterFlag != 0)
{
UINT32 Filter;
RTMP_IO_READ32(pAd, RX_FILTR_CFG, &Filter);
if ((pVifParm->MonFilterFlag & RT_CMD_80211_FILTER_FCSFAIL) == RT_CMD_80211_FILTER_FCSFAIL)
{
Filter = Filter & (~0x01);
}
else
{
Filter = Filter | 0x01;
}
if ((pVifParm->MonFilterFlag & RT_CMD_80211_FILTER_PLCPFAIL) == RT_CMD_80211_FILTER_PLCPFAIL)
{
Filter = Filter & (~0x02);
}
else
{
Filter = Filter | 0x02;
}
if ((pVifParm->MonFilterFlag & RT_CMD_80211_FILTER_CONTROL) == RT_CMD_80211_FILTER_CONTROL)
{
Filter = Filter & (~0xFF00);
}
else
{
Filter = Filter | 0xFF00;
}
if ((pVifParm->MonFilterFlag & RT_CMD_80211_FILTER_OTHER_BSS) == RT_CMD_80211_FILTER_OTHER_BSS)
{
Filter = Filter & (~0x08);
}
else
{
Filter = Filter | 0x08;
}
RTMP_IO_WRITE32(pAd, RX_FILTR_CFG, Filter);
pVifParm->MonFilterFlag = Filter;
}
}
#endif /*CONFIG_STA_SUPPORT*/
if ((newType == RT_CMD_80211_IFTYPE_P2P_CLIENT) ||
(newType == RT_CMD_80211_IFTYPE_P2P_GO))
{
COPY_MAC_ADDR(pAd->cfg80211_ctrl.P2PCurrentAddress, pVifParm->net_dev->dev_addr);
}
else
{
#ifdef RT_CFG80211_P2P_SUPPORT
pCfg80211_ctrl->bP2pCliPmEnable = FALSE;
pCfg80211_ctrl->bPreKeepSlient = FALSE;
pCfg80211_ctrl->bKeepSlient = FALSE;
pCfg80211_ctrl->NoAIndex = MAX_LEN_OF_MAC_TABLE;
pCfg80211_ctrl->MyGOwcid = MAX_LEN_OF_MAC_TABLE;
pCfg80211_ctrl->CTWindows= 0; /* CTWindows and OppPS parameter field */
#endif /* RT_CFG80211_P2P_SUPPORT */
}
return TRUE;
}
VOID NICInitRT3070RFRegisters(IN PRTMP_ADAPTER pAd)
{
INT i;
UCHAR RFValue;
/*
Driver must read EEPROM to get RfIcType before initial RF registers
Initialize RF register to default value
*/
if (IS_RT3070(pAd) || IS_RT3071(pAd))
{
/*
Init RF calibration
Driver should toggle RF R30 bit7 before init RF registers
*/
UINT8 RfReg = 0;
UINT32 data;
RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg);
RfReg |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
RTMPusecDelay(1000);
RfReg &= 0x7F;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
/* set default antenna as main */
if (pAd->RfIcType == RFIC_3020 || pAd->RfIcType == RFIC_2020)
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
/* Initialize RF register to default value */
for (i = 0; i < NUM_RF_3020_REG_PARMS; i++)
{
RT30xxWriteRFRegister(pAd, RT3020_RFRegTable[i].Register, RT3020_RFRegTable[i].Value);
}
RT30xxWriteRFRegister(pAd, RF_R31, 0x14);
/* add by johnli */
if (IS_RT3070(pAd))
{
/*
The DAC issue(LDO_CFG0) has been fixed in RT3070(F).
The voltage raising patch is no longer needed for RT3070(F)
*/
if ((pAd->MACVersion & 0xffff) < 0x0201)
{
/* Update MAC 0x05D4 from 01xxxxxx to 0Dxxxxxx (voltage 1.2V to 1.35V) for RT3070 to improve yield rate */
RTUSBReadMACRegister(pAd, LDO_CFG0, &data);
data = ((data & 0xF0FFFFFF) | 0x0D000000);
RTUSBWriteMACRegister(pAd, LDO_CFG0, data);
}
}
else if (IS_RT3071(pAd))
{
/* Driver should set RF R6 bit6 on before init RF registers */
RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg);
RfReg |= 0x40;
RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg);
/* RT3071 version E has fixed this issue */
if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211))
{
/* patch tx EVM issue temporarily */
RTUSBReadMACRegister(pAd, LDO_CFG0, &data);
data = ((data & 0xE0FFFFFF) | 0x0D000000);
RTUSBWriteMACRegister(pAd, LDO_CFG0, data);
}
else
{
RTMP_IO_READ32(pAd, LDO_CFG0, &data);
data = ((data & 0xE0FFFFFF) | 0x01000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
}
/* patch LNA_PE_G1 failed issue */
RTUSBReadMACRegister(pAd, GPIO_SWITCH, &data);
data &= ~(0x20);
RTUSBWriteMACRegister(pAd, GPIO_SWITCH, data);
}
/* For RF filter Calibration */
RTMPFilterCalibration(pAd);
/*
Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration()
TX to RX IQ glitch(RF_R27) has been fixed in RT3070(F).
Raising RF voltage is no longer needed for RT3070(F)
*/
if ((IS_RT3070(pAd)) && ((pAd->MACVersion & 0xffff) < 0x0201))
{
RT30xxWriteRFRegister(pAd, RF_R27, 0x3);
}
else if ((IS_RT3071(pAd)) && ((pAd->MACVersion & 0xffff) < 0x0211))
{
RT30xxWriteRFRegister(pAd, RF_R27, 0x3);
}
/* set led open drain enable */
RTUSBReadMACRegister(pAd, OPT_14, &data);
data |= 0x01;
RTUSBWriteMACRegister(pAd, OPT_14, data);
if (IS_RT3071(pAd))
{
/* RF power sequence setup, load RF normal operation-mode setup */
RT30xxLoadRFNormalModeSetup(pAd);
}
else if (IS_RT3070(pAd))
{
/* TX_LO1_en, RF R17 register Bit 3 to 0 */
RT30xxReadRFRegister(pAd, RF_R17, &RFValue);
RFValue &= (~0x08);
/* to fix rx long range issue */
if (pAd->NicConfig2.field.ExternalLNAForG == 0)
{
if ((IS_RT3071(pAd) && ((pAd->MACVersion & 0xffff) >= 0x0211)) || IS_RT3070(pAd))
{
RFValue |= 0x20;
}
}
/* set RF_R17_bit[2:0] equal to EEPROM setting at 0x48h */
if (pAd->TxMixerGain24G >= 1)
{
RFValue &= (~0x7); /* clean bit [2:0] */
RFValue |= pAd->TxMixerGain24G;
}
RT30xxWriteRFRegister(pAd, RF_R17, RFValue);
/* add by johnli, reset RF_R27 when interface down & up to fix throughput problem */
/* LDORF_VC, RF R27 register Bit 2 to 0 */
RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
/*
TX to RX IQ glitch(RF_R27) has been fixed in RT3070(F).
Raising RF voltage is no longer needed for RT3070(F)
*/
if ((pAd->MACVersion & 0xffff) < 0x0201)
RFValue = (RFValue & (~0x77)) | 0x3;
else
RFValue = (RFValue & (~0x77));
RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
/* end johnli */
}
}
}
VOID APMakeAllBssBeacon(
IN PRTMP_ADAPTER pAd)
{
INT i, j;
UINT32 regValue;
UCHAR NumOfMacs;
UCHAR NumOfBcns;
UINT8 TXWISize = pAd->chipCap.TXWISize;
/* before MakeBssBeacon, clear all beacon TxD's valid bit */
/* Note: can not use MAX_MBSSID_NUM here, or
1. when MBSS_SUPPORT is enabled;
2. MAX_MBSSID_NUM will be 8;
3. if HW_BEACON_OFFSET is 0x0200,
we will overwrite other shared memory SRAM of chip */
/* use pAd->ApCfg.BssidNum to avoid the case is best */
/* choose the Beacon number */
NumOfBcns = GetBcnNum(pAd);
for (i=0; i<HW_BEACON_MAX_COUNT(pAd); i++)
{
for (j=0; j < TXWISize; j+=4)
{
RTMP_CHIP_UPDATE_BEACON(pAd, pAd->BeaconOffset[i] + j, 0, 4);
}
}
for(i=0; i<pAd->ApCfg.BssidNum; i++)
{
APMakeBssBeacon(pAd, i);
}
RTMP_IO_READ32(pAd, MAC_BSSID_DW1, ®Value);
regValue &= 0x0000FFFF;
/*
Note:
1.The MAC address of Mesh and AP-Client link are different from Main BSSID.
2.If the Mesh link is included, its MAC address shall follow the last MBSSID's MAC by increasing 1.
3.If the AP-Client link is included, its MAC address shall follow the Mesh interface MAC by increasing 1.
*/
NumOfMacs = pAd->ApCfg.BssidNum + MAX_MESH_NUM + MAX_APCLI_NUM;
/* set Multiple BSSID mode */
if (NumOfMacs <= 1)
{
pAd->ApCfg.MacMask = ~(1-1);
/*regValue |= 0x0; */
}
else if (NumOfMacs <= 2)
{
if ((pAd->CurrentAddress[5] % 2 != 0)
)
DBGPRINT(RT_DEBUG_ERROR, ("The 2-BSSID mode is enabled, the BSSID byte5 MUST be the multiple of 2\n"));
regValue |= (1<<16);
pAd->ApCfg.MacMask = ~(2-1);
}
else if (NumOfMacs <= 4)
{
if (pAd->CurrentAddress[5] % 4 != 0)
DBGPRINT(RT_DEBUG_ERROR, ("The 4-BSSID mode is enabled, the BSSID byte5 MUST be the multiple of 4\n"));
regValue |= (2<<16);
pAd->ApCfg.MacMask = ~(4-1);
}
else if (NumOfMacs <= 8)
{
if (pAd->CurrentAddress[5] % 8 != 0)
DBGPRINT(RT_DEBUG_ERROR, ("The 8-BSSID mode is enabled, the BSSID byte5 MUST be the multiple of 8\n"));
regValue |= (3<<16);
pAd->ApCfg.MacMask = ~(8-1);
}
else if (NumOfMacs <= 16)
{
/* Set MULTI_BSSID_MODE_BIT4 in MAC register 0x1014 */
regValue |= (1<<22);
pAd->ApCfg.MacMask = ~(16-1);
}
/* set Multiple BSSID Beacon number */
if (NumOfBcns > 1)
{
if (NumOfBcns > 8)
regValue |= (((NumOfBcns - 1) >> 3) << 23);
regValue |= (((NumOfBcns - 1) & 0x7) << 18);
}
/* set as 0/1 bit-21 of MAC_BSSID_DW1(offset: 0x1014)
to disable/enable the new MAC address assignment. */
if (pAd->chipCap.MBSSIDMode >= MBSSID_MODE1)
{
regValue |= (1 << 21);
#ifdef ENHANCE_NEW_MBSSID_MODE
if (pAd->chipCap.MBSSIDMode == MBSSID_MODE2)
regValue |= (1 << 24);
else if (pAd->chipCap.MBSSIDMode == MBSSID_MODE3)
regValue |= (2 << 24);
else if (pAd->chipCap.MBSSIDMode == MBSSID_MODE4)
regValue |= (3 << 24);
else if (pAd->chipCap.MBSSIDMode == MBSSID_MODE5)
regValue |= (4 << 24);
else if (pAd->chipCap.MBSSIDMode == MBSSID_MODE6)
regValue |= (5 << 24);
#endif /* ENHANCE_NEW_MBSSID_MODE */
}
RTMP_IO_WRITE32(pAd, MAC_BSSID_DW1, regValue);
#ifdef HDR_TRANS_SUPPORT
/*
point WCID MAC table to 0x1800
This is for debug.
But HDR_TRANS doesn't work if you remove it.
Check after IC formal release.
*/
regValue |= 0x18000000;
RTMP_IO_WRITE32(pAd, HT_MAC_BSSID_DW1, regValue);
#endif /* HDR_TRANS_SUPPORT */
}
BOOLEAN RTMPFreeTXDUponTxDmaDone(
IN PRTMP_ADAPTER pAd,
IN UCHAR QueIdx)
{
PRTMP_TX_RING pTxRing;
PTXD_STRUC pTxD;
#ifdef RT_BIG_ENDIAN
PTXD_STRUC pDestTxD;
#endif
PNDIS_PACKET pPacket;
UCHAR FREE = 0;
TXD_STRUC TxD, *pOriTxD;
//ULONG IrqFlags;
BOOLEAN bReschedule = FALSE;
ASSERT(QueIdx < NUM_OF_TX_RING);
pTxRing = &pAd->TxRing[QueIdx];
RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QueIdx * RINGREG_DIFF, &pTxRing->TxDmaIdx);
while (pTxRing->TxSwFreeIdx != pTxRing->TxDmaIdx)
{
// RTMP_IRQ_LOCK(&pAd->irq_lock, IrqFlags);
#ifdef RALINK_ATE
#ifdef RALINK_QA
PHEADER_802_11 pHeader80211;
if ((ATE_ON(pAd)) && (pAd->ate.bQATxStart == TRUE))
{
if (pAd->ate.QID == QueIdx)
{
pAd->ate.TxDoneCount++;
pAd->RalinkCounters.KickTxCount++;
/* always use QID_AC_BE and FIFO_EDCA */
ASSERT(pAd->ate.QID == 0);
pAd->ate.TxAc0++;
FREE++;
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pTxD;
NdisMoveMemory(&TxD, pTxD, sizeof(TXD_STRUC));
pTxD = &TxD;
#else
pDestTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pDestTxD ;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
pTxD->DMADONE = 0;
pHeader80211 = pTxRing->Cell[pTxRing->TxSwFreeIdx].DmaBuf.AllocVa + sizeof(TXWI_STRUC);
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader80211, DIR_READ, FALSE);
#endif
pHeader80211->Sequence = ++pAd->ate.seq;
#ifdef RT_BIG_ENDIAN
RTMPFrameEndianChange(pAd, (PUCHAR)pHeader80211, DIR_WRITE, FALSE);
#endif
if ((pAd->ate.bQATxStart == TRUE) && (pAd->ate.Mode & ATE_TXFRAME) && (pAd->ate.TxDoneCount < pAd->ate.TxCount))
{
pAd->RalinkCounters.TransmittedByteCount.QuadPart += (pTxD->SDLen1 + pTxD->SDLen0);
pAd->RalinkCounters.OneSecTransmittedByteCount += (pTxD->SDLen1 + pTxD->SDLen0);
pAd->RalinkCounters.OneSecDmaDoneCount[QueIdx] ++;
INC_RING_INDEX(pTxRing->TxSwFreeIdx, TX_RING_SIZE);
/* get TX_DTX_IDX again */
RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QueIdx * RINGREG_DIFF , &pTxRing->TxDmaIdx);
goto kick_out;
}
else if ((pAd->ate.TxStatus == 1)/* or (pAd->ate.bQATxStart == TRUE) ??? */ && (pAd->ate.TxDoneCount == pAd->ate.TxCount))
{
DBGPRINT(RT_DEBUG_TRACE,("all Tx is done\n"));
// Tx status enters idle mode.
pAd->ate.TxStatus = 0;
}
else if (!(pAd->ate.Mode & ATE_TXFRAME))
{
/* not complete sending yet, but someone press the Stop TX botton */
DBGPRINT(RT_DEBUG_INFO,("not complete sending yet, but someone pressed the Stop TX bottom\n"));
DBGPRINT(RT_DEBUG_INFO,("pAd->ate.Mode = 0x%02x\n", pAd->ate.Mode));
}
else
{
DBGPRINT(RT_DEBUG_OFF,("pTxRing->TxSwFreeIdx = %d\n", pTxRing->TxSwFreeIdx));
}
#ifndef RT_BIG_ENDIAN
NdisMoveMemory(pOriTxD, pTxD, sizeof(TXD_STRUC));
#else
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
*pDestTxD = TxD;
#endif // RT_BIG_ENDIAN //
INC_RING_INDEX(pTxRing->TxSwFreeIdx, TX_RING_SIZE);
continue;
}
}
#endif // RALINK_QA //
#endif // RALINK_ATE //
// static rate also need NICUpdateFifoStaCounters() function.
//if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED))
#ifdef VENDOR_FEATURE1_SUPPORT
/*
Note:
Can not take off the NICUpdateFifoStaCounters(); Or the
FIFO overflow rate will be high, i.e. > 3%
(see the rate by "iwpriv ra0 show stainfo")
Based on different platform, try to find the best value to
replace '4' here (overflow rate target is about 0%).
*/
if (++pAd->FifoUpdateRx >= 4)
{
NICUpdateFifoStaCounters(pAd);
pAd->FifoUpdateRx = 0;
}
#else
NICUpdateFifoStaCounters(pAd);
#endif // VENDOR_FEATURE1_SUPPORT //
/* Note : If (pAd->ate.bQATxStart == TRUE), we will never reach here. */
FREE++;
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pTxD;
NdisMoveMemory(&TxD, pTxD, sizeof(TXD_STRUC));
pTxD = &TxD;
#else
pDestTxD = (PTXD_STRUC) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
pOriTxD = pDestTxD ;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
pTxD->DMADONE = 0;
#ifdef CONFIG_AP_SUPPORT
#ifdef UAPSD_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
UAPSD_SP_PacketCheck(pAd,
pTxRing->Cell[pTxRing->TxSwFreeIdx].pNdisPacket,
((UCHAR *)pTxRing->Cell[\
pTxRing->TxSwFreeIdx].DmaBuf.AllocVa)+TXWI_SIZE);
}
#endif // UAPSD_AP_SUPPORT //
#endif // CONFIG_AP_SUPPORT //
#ifdef RALINK_ATE
/* Execution of this block is not allowed when ATE is running. */
if (!(ATE_ON(pAd)))
#endif // RALINK_ATE //
{
pPacket = pTxRing->Cell[pTxRing->TxSwFreeIdx].pNdisPacket;
if (pPacket)
{
#ifdef CONFIG_5VT_ENHANCE
if (RTMP_GET_PACKET_5VT(pPacket))
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, 16, PCI_DMA_TODEVICE);
else
#endif // CONFIG_5VT_ENHANCE //
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
//Always assign pNdisPacket as NULL after clear
pTxRing->Cell[pTxRing->TxSwFreeIdx].pNdisPacket = NULL;
pPacket = pTxRing->Cell[pTxRing->TxSwFreeIdx].pNextNdisPacket;
if (pPacket)
{
#ifdef CONFIG_5VT_ENHANCE
if (RTMP_GET_PACKET_5VT(pPacket))
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, 16, PCI_DMA_TODEVICE);
else
#endif // CONFIG_5VT_ENHANCE //
PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE);
RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
}
//Always assign pNextNdisPacket as NULL after clear
pTxRing->Cell[pTxRing->TxSwFreeIdx].pNextNdisPacket = NULL;
}
pAd->RalinkCounters.TransmittedByteCount.QuadPart += (pTxD->SDLen1 + pTxD->SDLen0);
pAd->RalinkCounters.OneSecTransmittedByteCount += (pTxD->SDLen1 + pTxD->SDLen0);
pAd->RalinkCounters.OneSecDmaDoneCount[QueIdx] ++;
INC_RING_INDEX(pTxRing->TxSwFreeIdx, TX_RING_SIZE);
/* get tx_tdx_idx again */
RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QueIdx * RINGREG_DIFF , &pTxRing->TxDmaIdx);
#ifdef RT_BIG_ENDIAN
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
*pDestTxD = TxD;
#else
NdisMoveMemory(pOriTxD, pTxD, sizeof(TXD_STRUC));
#endif
#ifdef RALINK_ATE
#ifdef RALINK_QA
kick_out:
#endif // RALINK_QA //
/*
ATE_TXCONT mode also need to send some normal frames, so let it in.
ATE_STOP must be changed not to be 0xff
to prevent it from running into this block.
*/
if ((pAd->ate.Mode & ATE_TXFRAME) && (pAd->ate.QID == QueIdx))
{
// TxDoneCount++ has been done if QA is used.
if (pAd->ate.bQATxStart == FALSE)
{
pAd->ate.TxDoneCount++;
}
if (((pAd->ate.TxCount - pAd->ate.TxDoneCount + 1) >= TX_RING_SIZE))
{
/* Note : We increase TxCpuIdx here, not TxSwFreeIdx ! */
INC_RING_INDEX(pAd->TxRing[QueIdx].TxCpuIdx, TX_RING_SIZE);
#ifndef RT_BIG_ENDIAN
pTxD = (PTXD_STRUC) (pTxRing->Cell[pAd->TxRing[QueIdx].TxCpuIdx].AllocVa);
pOriTxD = pTxD;
NdisMoveMemory(&TxD, pTxD, sizeof(TXD_STRUC));
pTxD = &TxD;
#else
pDestTxD = (PTXD_STRUC) (pTxRing->Cell[pAd->TxRing[QueIdx].TxCpuIdx].AllocVa);
pOriTxD = pDestTxD ;
TxD = *pDestTxD;
pTxD = &TxD;
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
#endif
pTxD->DMADONE = 0;
#ifndef RT_BIG_ENDIAN
NdisMoveMemory(pOriTxD, pTxD, sizeof(TXD_STRUC));
#else
RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD);
*pDestTxD = TxD;
#endif
// kick Tx-Ring
RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QueIdx * RINGREG_DIFF, pAd->TxRing[QueIdx].TxCpuIdx);
pAd->RalinkCounters.KickTxCount++;
}
}
#endif // RALINK_ATE //
// RTMP_IRQ_UNLOCK(&pAd->irq_lock, IrqFlags);
}
return bReschedule;
}
int RtmpAsicSendCommandToSwMcu(
IN RTMP_ADAPTER *pAd,
IN UCHAR Command,
IN UCHAR Token,
IN UCHAR Arg0,
IN UCHAR Arg1,
IN BOOLEAN FlgIsNeedLocked)
{
BBP_CSR_CFG_STRUC BbpCsr, BbpCsr2;
int j, k;
#ifdef LED_CONTROL_SUPPORT
UINT16 Temp;
PSWMCU_LED_CONTROL pSWMCULedCntl = &pAd->LedCntl.SWMCULedCntl;
#endif /* LED_CONTROL_SUPPORT */
switch(Command)
{
case 0x80:
RTMP_IO_READ32(pAd, H2M_BBP_AGENT, &BbpCsr.word);
if ((BbpCsr.field.Busy != 1) || (BbpCsr.field.BBP_RW_MODE != 1))
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_ERROR, ("error read write BBP 1\n"));
for (j=0; j<MAX_BUSY_COUNT; j++)
{
RTMP_IO_READ32(pAd, BBP_CSR_CFG, &BbpCsr2.word);
if (BbpCsr2.field.Busy == BUSY)
{
continue;
}
BbpCsr2.word = BbpCsr.word;
RTMP_IO_WRITE32(pAd, BBP_CSR_CFG, BbpCsr2.word);
if (BbpCsr.field.fRead == 1)
{
/* read*/
for (k=0; k<MAX_BUSY_COUNT; k++)
{
RTMP_IO_READ32(pAd, BBP_CSR_CFG, &BbpCsr2.word);
if (BbpCsr2.field.Busy == IDLE)
break;
}
if (k == MAX_BUSY_COUNT)
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_ERROR, ("error read write BBP 2\n"));
if ((BbpCsr2.field.Busy == IDLE) && (BbpCsr2.field.RegNum == BbpCsr.field.RegNum))
{
BbpCsr.field.Value = BbpCsr2.field.Value;
BbpCsr.field.Busy = IDLE;
RTMP_IO_WRITE32(pAd, H2M_BBP_AGENT, BbpCsr.word);
break;
}
}
else
{
/*write*/
BbpCsr.field.Busy = IDLE;
RTMP_IO_WRITE32(pAd, H2M_BBP_AGENT, BbpCsr.word);
pAd->BbpWriteLatch[BbpCsr.field.RegNum] = BbpCsr2.field.Value;
break;
}
}
if (j == MAX_BUSY_COUNT)
{
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_ERROR, ("error read write BBP 3\n"));
if (BbpCsr.field.Busy != IDLE)
{
BbpCsr.field.Busy = IDLE;
RTMP_IO_WRITE32(pAd, H2M_BBP_AGENT, BbpCsr.word);
}
}
break;
case 0x30:
break;
case 0x31:
break;
#ifdef LED_CONTROL_SUPPORT
#if defined(CONFIG_WIFI_LED_SHARE) || defined(__ECOS)
case MCU_SET_WPS_LED_MODE:
pSWMCULedCntl->LedParameter.LedMode = Arg0;
pSWMCULedCntl->LinkStatus = Arg1;
SetWPSLinkStatus(pAd);
break;
#endif /* CONFIG_WIFI_LED_SHARE || __ECOS */
case MCU_SET_LED_MODE:
pSWMCULedCntl->LedParameter.LedMode = Arg0;
pSWMCULedCntl->LinkStatus = Arg1;
SetLedLinkStatus(pAd);
break;
case MCU_SET_LED_GPIO_SIGNAL_CFG:
pSWMCULedCntl->GPIOPolarity = Arg1;
pSWMCULedCntl->SignalStrength = Arg0;
break;
case MCU_SET_LED_AG_CFG:
Temp = ((UINT16)Arg1 << 8) | (UINT16)Arg0;
NdisMoveMemory(&pSWMCULedCntl->LedParameter.LedAgCfg, &Temp, 2);
break;
case MCU_SET_LED_ACT_CFG:
Temp = ((UINT16)Arg1 << 8) | (UINT16)Arg0;
NdisMoveMemory(&pSWMCULedCntl->LedParameter.LedActCfg, &Temp, 2);
break;
case MCU_SET_LED_POLARITY:
Temp = ((UINT16)Arg1 << 8) | (UINT16)Arg0;
NdisMoveMemory(&pSWMCULedCntl->LedParameter.LedPolarityCfg, &Temp, 2);
break;
#endif /* LED_CONTROL_SUPPORT */
default:
break;
}
return 0;
}
RTMP_BUILD_DRV_OPS_FUNCTION_BODY
#endif /* OS_ABL_FUNC_SUPPORT */
#endif /* LINUX */
int rt28xx_init(
IN VOID *pAdSrc,
IN PSTRING pDefaultMac,
IN PSTRING pHostName)
{
PRTMP_ADAPTER pAd = (PRTMP_ADAPTER)pAdSrc;
UINT index;
UCHAR TmpPhy;
NDIS_STATUS Status;
if (pAd == NULL)
return FALSE;
#ifdef CONFIG_STA_SUPPORT
#ifdef PCIE_PS_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
{
/* If dirver doesn't wake up firmware here,*/
/* NICLoadFirmware will hang forever when interface is up again.*/
if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE) &&
OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE))
{
AUTO_WAKEUP_STRUC AutoWakeupCfg;
AsicForceWakeup(pAd, TRUE);
AutoWakeupCfg.word = 0;
RTMP_IO_WRITE32(pAd, AUTO_WAKEUP_CFG, AutoWakeupCfg.word);
OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE);
}
}
#endif /* PCIE_PS_SUPPORT */
#endif /* CONFIG_STA_SUPPORT */
/* reset Adapter flags*/
RTMP_CLEAR_FLAGS(pAd);
/* Init BssTab & ChannelInfo tabbles for auto channel select.*/
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
/*#ifdef AUTO_CH_SELECT_ENHANCE*/
AutoChBssTableInit(pAd);
ChannelInfoInit(pAd);
/*#endif AUTO_CH_SELECT_ENHANCE */
}
#endif /* CONFIG_AP_SUPPORT */
#ifdef DOT11_N_SUPPORT
/* Allocate BA Reordering memory*/
if (ba_reordering_resource_init(pAd, MAX_REORDERING_MPDU_NUM) != TRUE)
goto err1;
#endif /* DOT11_N_SUPPORT */
/* Make sure MAC gets ready.*/
index = 0;
if (WaitForAsicReady(pAd) != TRUE)
goto err1;
DBGPRINT(RT_DEBUG_TRACE, ("MAC[Ver:Rev=0x%08x]\n", pAd->MACVersion));
if (MAX_LEN_OF_MAC_TABLE > MAX_AVAILABLE_CLIENT_WCID(pAd))
{
DBGPRINT(RT_DEBUG_ERROR, ("MAX_LEN_OF_MAC_TABLE can not be larger than MAX_AVAILABLE_CLIENT_WCID!!!!\n"));
goto err1;
}
#ifdef RTMP_MAC_PCI
/* To fix driver disable/enable hang issue when radio off*/
RTMP_IO_WRITE32(pAd, PWR_PIN_CFG, 0x2);
#endif /* RTMP_MAC_PCI */
/* Disable DMA*/
RT28XXDMADisable(pAd);
/* Load 8051 firmware*/
Status = NICLoadFirmware(pAd);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("NICLoadFirmware failed, Status[=0x%08x]\n", Status));
goto err1;
}
NICLoadRateSwitchingParams(pAd);
/* Disable interrupts here which is as soon as possible*/
/* This statement should never be true. We might consider to remove it later*/
#ifdef RTMP_MAC_PCI
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE))
{
RTMP_ASIC_INTERRUPT_DISABLE(pAd);
}
#endif /* RTMP_MAC_PCI */
#ifdef RESOURCE_PRE_ALLOC
Status = RTMPInitTxRxRingMemory(pAd);
#else
Status = RTMPAllocTxRxRingMemory(pAd);
#endif /* RESOURCE_PRE_ALLOC */
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("RTMPAllocTxRxMemory failed, Status[=0x%08x]\n", Status));
goto err2;
}
RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE);
/* initialize MLME*/
#ifdef RT6352
pAd->bCalibrationDone = FALSE;
#endif /* RT6352 */
Status = RtmpMgmtTaskInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
goto err3;
Status = MlmeInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("MlmeInit failed, Status[=0x%08x]\n", Status));
goto err4;
}
#ifdef RMTP_RBUS_SUPPORT
#ifdef VIDEO_TURBINE_SUPPORT
VideoConfigInit(pAd);
#endif /* VIDEO_TURBINE_SUPPORT */
#endif /* RMTP_RBUS_SUPPORT */
/* Initialize pAd->StaCfg, pAd->ApCfg, pAd->CommonCfg to manufacture default*/
UserCfgInit(pAd);
Status = RtmpNetTaskInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
goto err5;
/* COPY_MAC_ADDR(pAd->ApCfg.MBSSID[apidx].Bssid, netif->hwaddr);*/
/* pAd->bForcePrintTX = TRUE;*/
CfgInitHook(pAd);
#ifdef CONFIG_AP_SUPPORT
if ((pAd->OpMode == OPMODE_AP)
#ifdef P2P_SUPPORT
|| TRUE
#endif /* P2P_SUPPORT */
)
APInitialize(pAd);
#endif /* CONFIG_AP_SUPPORT */
#ifdef BLOCK_NET_IF
initblockQueueTab(pAd);
#endif /* BLOCK_NET_IF */
Status = MeasureReqTabInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("MeasureReqTabInit failed, Status[=0x%08x]\n",Status));
goto err6;
}
Status = TpcReqTabInit(pAd);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("TpcReqTabInit failed, Status[=0x%08x]\n",Status));
goto err6;
}
/* Init the hardware, we need to init asic before read registry, otherwise mac register will be reset*/
Status = NICInitializeAdapter(pAd, TRUE);
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("NICInitializeAdapter failed, Status[=0x%08x]\n", Status));
if (Status != NDIS_STATUS_SUCCESS)
goto err6;
}
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
}
#endif /* CONFIG_AP_SUPPORT */
/* Read parameters from Config File */
/* unknown, it will be updated in NICReadEEPROMParameters */
pAd->RfIcType = RFIC_UNKNOWN;
Status = RTMPReadParametersHook(pAd);
if(pAd->CommonCfg.Channel==0)
{
RTMPSetDefaultChannel(pAd);
}
#ifdef CONFIG_STA_SUPPORT
#ifdef CREDENTIAL_STORE
RecoverConnectInfo(pAd);
#endif /* CREDENTIAL_STORE */
#endif /* CONFIG_STA_SUPPORT */
DBGPRINT(RT_DEBUG_OFF, ("1. Phy Mode = %d\n", pAd->CommonCfg.PhyMode));
if (Status != NDIS_STATUS_SUCCESS)
{
DBGPRINT_ERR(("RTMPReadParametersHook failed, Status[=0x%08x]\n",Status));
goto err6;
}
#ifdef DOT11_N_SUPPORT
/*Init Ba Capability parameters.*/
/* RT28XX_BA_INIT(pAd);*/
pAd->CommonCfg.DesiredHtPhy.MpduDensity = (UCHAR)pAd->CommonCfg.BACapability.field.MpduDensity;
pAd->CommonCfg.DesiredHtPhy.AmsduEnable = (USHORT)pAd->CommonCfg.BACapability.field.AmsduEnable;
pAd->CommonCfg.DesiredHtPhy.AmsduSize = (USHORT)pAd->CommonCfg.BACapability.field.AmsduSize;
pAd->CommonCfg.DesiredHtPhy.MimoPs = (USHORT)pAd->CommonCfg.BACapability.field.MMPSmode;
/* UPdata to HT IE*/
pAd->CommonCfg.HtCapability.HtCapInfo.MimoPs = (USHORT)pAd->CommonCfg.BACapability.field.MMPSmode;
pAd->CommonCfg.HtCapability.HtCapInfo.AMsduSize = (USHORT)pAd->CommonCfg.BACapability.field.AmsduSize;
pAd->CommonCfg.HtCapability.HtCapParm.MpduDensity = (UCHAR)pAd->CommonCfg.BACapability.field.MpduDensity;
#endif /* DOT11_N_SUPPORT */
/* after reading Registry, we now know if in AP mode or STA mode*/
/* Load 8051 firmware; crash when FW image not existent*/
/* Status = NICLoadFirmware(pAd);*/
/* if (Status != NDIS_STATUS_SUCCESS)*/
/* break;*/
DBGPRINT(RT_DEBUG_OFF, ("2. Phy Mode = %d\n", pAd->CommonCfg.PhyMode));
/* We should read EEPROM for all cases. rt2860b*/
NICReadEEPROMParameters(pAd, (PSTRING)pDefaultMac);
#ifdef CONFIG_STA_SUPPORT
#endif /* CONFIG_STA_SUPPORT */
DBGPRINT(RT_DEBUG_OFF, ("3. Phy Mode = %d\n", pAd->CommonCfg.PhyMode));
#ifdef LED_CONTROL_SUPPORT
/* Send LED Setting to MCU */
RTMPInitLEDMode(pAd);
#endif /* LED_CONTROL_SUPPORT */
NICInitAsicFromEEPROM(pAd); /* rt2860b */
#ifdef RT6352
if (IS_RT6352(pAd))
{
RtmpKickOutHwNullFrame(pAd, TRUE, FALSE);
#if defined(RT6352_EP_SUPPORT) || defined(RT6352_EL_SUPPORT)
{
ULONG SysRegValue;
RTMP_SYS_IO_READ32(0xb0000060, &SysRegValue);
if ((SysRegValue & 0x100000) == 0x0)
{
SysRegValue |= 0x100000;
RTMP_SYS_IO_WRITE32(0xb0000060, SysRegValue);
DBGPRINT(RT_DEBUG_ERROR,("Change as GPIO Mode(0x%x)\n", SysRegValue));
}
}
#endif /* defined(RT6352_EP_SUPPORT) || defined(RT6352_EL_SUPPORT) */
/* Do R-Calibration */
R_Calibration(pAd);
#ifdef RTMP_TEMPERATURE_CALIBRATION
/* Temperature Init */
RT6352_Temperature_Init(pAd);
RT6352_TemperatureCalibration(pAd);
#endif /* RTMP_TEMPERATURE_CALIBRATION */
#ifdef RTMP_TEMPERATURE_COMPENSATION
/*
read out tempature reference value (0x80 ~ 0x7F)
TssiPlusBoundaryG [7] [6] [5] [4] [3] [2] [1] [0] (smaller) +
TssiMinusBoundaryG[0] [1] [2] [3] [4] [5] [6] [7] (larger)
*/
RT6352_EEPROM_TSSI_24G_READ(pAd);
/*
pAd->TssiCalibratedOffset:
reference temperature(e2p[D1h])
*/
/* adjust the boundary table by pAd->TssiCalibratedOffset */
RT6352_TssiTableAdjust(pAd);
/* ATE temperature(e2p[77h]) */
RT6352_TssiMpAdjust(pAd);
DBGPRINT(RT_DEBUG_OFF,("E2PROM: G Tssi[-7 .. +7] = %d %d %d %d %d %d %d - %d - %d %d %d %d %d %d %d, offset=%d, tuning=%d\n",
pAd->TssiMinusBoundaryG[7], pAd->TssiMinusBoundaryG[6], pAd->TssiMinusBoundaryG[5],
pAd->TssiMinusBoundaryG[4], pAd->TssiMinusBoundaryG[3], pAd->TssiMinusBoundaryG[2], pAd->TssiMinusBoundaryG[1],
pAd->TssiRefG,
pAd->TssiPlusBoundaryG[1], pAd->TssiPlusBoundaryG[2], pAd->TssiPlusBoundaryG[3], pAd->TssiPlusBoundaryG[4],
pAd->TssiPlusBoundaryG[5], pAd->TssiPlusBoundaryG[6], pAd->TssiPlusBoundaryG[7],
pAd->TssiCalibratedOffset, pAd->bAutoTxAgcG));
#endif /* RTMP_TEMPERATURE_COMPENSATION */
AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, TRUE);
AsicLockChannel(pAd, pAd->CommonCfg.Channel);
/* RF Self TX DC Calibration */
RF_SELF_TXDC_CAL(pAd);
/* Rx DCOC Calibration */
RxDCOC_Calibration(pAd);
/* BandWidth Filter Calibration */
BW_Filter_Calibration(pAd,TRUE);
BW_Filter_Calibration(pAd,FALSE);
/* Do LOFT and IQ Calibration */
LOFT_IQ_Calibration(pAd);
/* DPD_Calibration */
#ifdef RT6352_EP_SUPPORT
if (pAd->bExtPA == FALSE)
#endif /* RT6352_EP_SUPPORT */
{
DoDPDCalibration(pAd);
pAd->DoDPDCurrTemperature = 0x7FFFFFFF;
}
/* Rx DCOC Calibration */
RxDCOC_Calibration(pAd);
/* Do RXIQ Calibration */
RXIQ_Calibration(pAd);
#if defined(RT6352_EP_SUPPORT) || defined(RT6352_EL_SUPPORT)
RT6352_Init_ExtPA_ExtLNA(pAd, FALSE);
#endif /* defined(RT6352_EP_SUPPORT) || defined(RT6352_EL_SUPPORT) */
}
#endif /* RT6352 */
#ifdef RALINK_ATE
if (ATEInit(pAd) != NDIS_STATUS_SUCCESS)
{
DBGPRINT(RT_DEBUG_ERROR, ("%s(): ATE initialization failed !\n", __FUNCTION__));
goto err6;
}
#endif /* RALINK_ATE */
#ifdef RTMP_INTERNAL_TX_ALC
/* Initialize the desired TSSI table*/
RTMP_CHIP_ASIC_TSSI_TABLE_INIT(pAd);
#endif /* RTMP_INTERNAL_TX_ALC */
InitRfPaModeTable(pAd);
#ifdef RTMP_TEMPERATURE_COMPENSATION
/* Temperature compensation, initialize the lookup table */
DBGPRINT(RT_DEBUG_OFF, ("bAutoTxAgcG = %d\n", pAd->bAutoTxAgcG));
if (pAd->chipCap.bTempCompTxALC && pAd->bAutoTxAgcG)
InitLookupTable(pAd);
#endif /* RTMP_TEMPERATURE_COMPENSATION */
/* Set PHY to appropriate mode*/
TmpPhy = pAd->CommonCfg.PhyMode;
pAd->CommonCfg.PhyMode = 0xff;
RTMPSetPhyMode(pAd, TmpPhy);
#ifdef DOT11_N_SUPPORT
SetCommonHT(pAd);
#endif /* DOT11_N_SUPPORT */
/* No valid channels.*/
if (pAd->ChannelListNum == 0)
{
DBGPRINT(RT_DEBUG_ERROR, ("Wrong configuration. No valid channel found. Check \"ContryCode\" and \"ChannelGeography\" setting.\n"));
goto err6;
}
#ifdef DOT11_N_SUPPORT
DBGPRINT(RT_DEBUG_OFF, ("MCS Set = %02x %02x %02x %02x %02x\n", pAd->CommonCfg.HtCapability.MCSSet[0],
pAd->CommonCfg.HtCapability.MCSSet[1], pAd->CommonCfg.HtCapability.MCSSet[2],
pAd->CommonCfg.HtCapability.MCSSet[3], pAd->CommonCfg.HtCapability.MCSSet[4]));
#endif /* DOT11_N_SUPPORT */
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
#ifdef AP_QLOAD_SUPPORT
/* init QBSS Element */
QBSS_LoadInit(pAd);
#endif /* AP_QLOAD_SUPPORT */
}
#endif /* CONFIG_AP_SUPPORT */
/* APInitialize(pAd);*/
#ifdef IKANOS_VX_1X0
VR_IKANOS_FP_Init(pAd->ApCfg.BssidNum, pAd->PermanentAddress);
#endif /* IKANOS_VX_1X0 */
#ifdef RALINK_ATE
#endif /* RALINK_ATE */
#ifdef CONFIG_AP_SUPPORT
/* Initialize RF register to default value*/
if (pAd->OpMode == OPMODE_AP)
{
AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE);
AsicLockChannel(pAd, pAd->CommonCfg.Channel);
}
#endif /* CONFIG_AP_SUPPORT */
#ifdef RTMP_INTERNAL_TX_ALC
#ifdef RT6352
if (IS_RT6352(pAd) && (pAd->TxPowerCtrl.bInternalTxALC == TRUE))
{
RT635xTssiDcCalibration(pAd);
}
#endif /* RT6352 */
#endif /* RTMP_INTERNAL_TX_ALC */
/*
Some modules init must be called before APStartUp().
Or APStartUp() will make up beacon content and call
other modules API to get some information to fill.
*/
if (pAd && (Status != NDIS_STATUS_SUCCESS))
{
/* Undo everything if it failed*/
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE))
{
/* NdisMDeregisterInterrupt(&pAd->Interrupt);*/
RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE);
}
/* RTMPFreeAdapter(pAd); we will free it in disconnect()*/
}
else if (pAd)
{
/* Microsoft HCT require driver send a disconnect event after driver initialization.*/
OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED);
OPSTATUS_CLEAR_FLAG(pAd, fOP_AP_STATUS_MEDIA_STATE_CONNECTED);
RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_MEDIA_STATE_CHANGE);
DBGPRINT(RT_DEBUG_TRACE, ("NDIS_STATUS_MEDIA_DISCONNECT Event B!\n"));
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
if (pAd->ApCfg.bAutoChannelAtBootup || (pAd->CommonCfg.Channel == 0))
{
UINT8 BBPValue = 0;
/* Enable Interrupt first due to we need to scan channel to receive beacons.*/
RTMP_IRQ_ENABLE(pAd);
/* Now Enable RxTx*/
RTMPEnableRxTx(pAd);
RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_START_UP);
/* Let BBP register at 20MHz to do scan */
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
BBPValue &= (~0x18);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
DBGPRINT(RT_DEBUG_ERROR, ("SYNC - BBP R4 to 20MHz.l\n"));
/* Now we can receive the beacon and do the listen beacon*/
/* use default BW to select channel*/
pAd->CommonCfg.Channel = AP_AUTO_CH_SEL(pAd, pAd->ApCfg.AutoChannelAlg);
pAd->ApCfg.bAutoChannelAtBootup = FALSE;
}
#ifdef DOT11_N_SUPPORT
/* If phymode > PHY_11ABGN_MIXED and BW=40 check extension channel, after select channel */
N_ChannelCheck(pAd);
#ifdef DOT11N_DRAFT3
/*
We only do this Overlapping BSS Scan when system up, for the
other situation of channel changing, we depends on station's
report to adjust ourself.
*/
if (pAd->CommonCfg.bForty_Mhz_Intolerant == TRUE)
{
DBGPRINT(RT_DEBUG_TRACE, ("Disable 20/40 BSSCoex Channel Scan(BssCoex=%d, 40MHzIntolerant=%d)\n",
pAd->CommonCfg.bBssCoexEnable,
pAd->CommonCfg.bForty_Mhz_Intolerant));
}
else if(pAd->CommonCfg.bBssCoexEnable == TRUE)
{
DBGPRINT(RT_DEBUG_TRACE, ("Enable 20/40 BSSCoex Channel Scan(BssCoex=%d)\n",
pAd->CommonCfg.bBssCoexEnable));
APOverlappingBSSScan(pAd);
}
RTMP_11N_D3_TimerInit(pAd);
/* RTMPInitTimer(pAd, &pAd->CommonCfg.Bss2040CoexistTimer, GET_TIMER_FUNCTION(Bss2040CoexistTimeOut), pAd, FALSE);*/
#endif /* DOT11N_DRAFT3 */
#endif /* DOT11_N_SUPPORT */
APStartUp(pAd);
DBGPRINT(RT_DEBUG_OFF, ("Main bssid = %02x:%02x:%02x:%02x:%02x:%02x\n",
PRINT_MAC(pAd->ApCfg.MBSSID[BSS0].Bssid)));
}
#endif /* CONFIG_AP_SUPPORT */
#ifdef RT6352
pAd->bCalibrationDone = TRUE;
if (IS_RT6352(pAd))
{
#ifdef DYNAMIC_VGA_SUPPORT
if (pAd->CommonCfg.MO_Cfg.bDyncVGAEnable)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R195, 0x83);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R196, 0x70);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R195, 0x86);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R196, 0x70);
}
#endif /* DYNAMIC_VGA_SUPPORT */
}
#endif /* RT6352 */
}/* end of else*/
/* Set up the Mac address*/
#ifdef CONFIG_AP_SUPPORT
#ifndef P2P_APCLI_SUPPORT
RtmpOSNetDevAddrSet(pAd->OpMode, pAd->net_dev, &pAd->CurrentAddress[0], NULL);
#endif /* P2P_APCLI_SUPPORT */
#endif /* CONFIG_AP_SUPPORT */
#ifdef CONFIG_STA_SUPPORT
RtmpOSNetDevAddrSet(pAd->OpMode, pAd->net_dev, &pAd->CurrentAddress[0], (PUCHAR)(pAd->StaCfg.dev_name));
#endif /* CONFIG_STA_SUPPORT */
/* Various AP function init*/
#ifdef CONFIG_AP_SUPPORT
#ifdef P2P_SUPPORT
#else
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
#endif /* P2P_SUPPORT */
{
#ifdef MBSS_SUPPORT
/* the function can not be moved to RT2860_probe() even register_netdev()
is changed as register_netdevice().
Or in some PC, kernel will panic (Fedora 4) */
/* RT28xx_MBSS_Init(pAd, pAd->net_dev); os abl move to rt_main_dev.c*/
#endif /* MBSS_SUPPORT */
#ifdef WDS_SUPPORT
/* RT28xx_WDS_Init(pAd, pAd->net_dev);*/
#endif /* WDS_SUPPORT */
#ifdef APCLI_SUPPORT
/* RT28xx_ApCli_Init(pAd, pAd->net_dev);*/
#endif /* APCLI_SUPPORT */
}
#endif /* CONFIG_AP_SUPPORT */
#ifdef UAPSD_SUPPORT
UAPSD_Init(pAd);
#endif /* UAPSD_SUPPORT */
/* assign function pointers*/
#ifdef MAT_SUPPORT
/* init function pointers, used in OS_ABL */
RTMP_MATOpsInit(pAd);
#endif /* MAT_SUPPORT */
#ifdef RTMP_RBUS_SUPPORT
if (pAd->infType == RTMP_DEV_INF_RBUS)
{
#ifdef VIDEO_TURBINE_SUPPORT
VideoTurbineDynamicTune(pAd);
#endif /* VIDEO_TURBINE_SUPPORT */
#ifdef RT3XXX_ANTENNA_DIVERSITY_SUPPORT
RT3XXX_AntDiversity_Init(pAd);
#endif /* RT3XXX_ANTENNA_DIVERSITY_SUPPORT */
}
#endif /* RTMP_RBUS_SUPPORT */
#ifdef P2P_SUPPORT
/* RTMP_P2P_Init(pAd, pAd->net_dev); */
#endif /* P2P_SUPPORT */
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
#ifdef MAT_SUPPORT
MATEngineInit(pAd);
#endif /* MAT_SUPPORT */
#ifdef CLIENT_WDS
CliWds_ProxyTabInit(pAd);
#endif /* CLIENT_WDS */
}
#endif /* CONFIG_AP_SUPPORT */
#ifdef CONFIG_STA_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
{
#ifdef DOT11Z_TDLS_SUPPORT
TDLS_Table_Init(pAd);
#endif /* DOT11Z_TDLS_SUPPORT */
#ifdef WPA_SUPPLICANT_SUPPORT
#ifndef NATIVE_WPA_SUPPLICANT_SUPPORT
/* send wireless event to wpa_supplicant for infroming interface up.*/
RtmpOSWrielessEventSend(pAd->net_dev, RT_WLAN_EVENT_CUSTOM, RT_INTERFACE_UP, NULL, NULL, 0);
#endif /* NATIVE_WPA_SUPPLICANT_SUPPORT */
#endif /* WPA_SUPPLICANT_SUPPORT */
}
#endif /* CONFIG_STA_SUPPORT */
/* auto-fall back settings */
RTMP_IO_WRITE32(pAd, HT_FBK_CFG1, 0xedcba980); /* Fallback MCS8->MCS0 */
#ifdef DOT11N_SS3_SUPPORT
if (pAd->CommonCfg.TxStream >= 3)
{
RTMP_IO_WRITE32(pAd, TX_FBK_CFG_3S_0, 0x12111008);
RTMP_IO_WRITE32(pAd, TX_FBK_CFG_3S_1, 0x16151413);
}
#endif /* DOT11N_SS3_SUPPORT */
#ifdef STREAM_MODE_SUPPORT
RtmpStreamModeInit(pAd);
#endif /* STREAM_MODE_SUPPORT */
#if defined(RT2883) || defined(RT3883)
if (IS_RT2883(pAd) || IS_RT3883(pAd))
{
UINT8 BBPValue = 0;
BBP_IO_READ8_BY_REG_ID(pAd, BBP_R65, &BBPValue);
if (pAd->CommonCfg.FineAGC)
BBPValue |= 0x40; /* turn on fine AGC*/
else
BBPValue &= ~0x40; /* turn off fine AGC*/
BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R65, BBPValue);
}
#endif /* defined(RT2883) || defined(RT3883) */
#ifdef DOT11_N_SUPPORT
#ifdef TXBF_SUPPORT
if (pAd->CommonCfg.ITxBfTimeout)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R179, 0x02);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R180, 0);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R182, pAd->CommonCfg.ITxBfTimeout & 0xFF);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R180, 1);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R182, (pAd->CommonCfg.ITxBfTimeout>>8) & 0xFF);
}
/*
========================================================================
Routine Description: Read RT30xx RF register through MAC
Arguments:
Return Value:
IRQL =
Note:
========================================================================
*/
NDIS_STATUS RT30xxReadRFRegister(
IN PRTMP_ADAPTER pAd,
IN UCHAR regID,
IN PUCHAR pValue)
{
RF_CSR_CFG_STRUC rfcsr = { { 0 } };
UINT i=0, k=0;
#ifdef RTMP_MAC_PCI
if ((pAd->bPCIclkOff == TRUE) || (pAd->LastMCUCmd == SLEEP_MCU_CMD))
{
DBGPRINT_ERR(("RT30xxReadRFRegister. Not allow to read RF 0x%x : fail\n", regID));
return STATUS_UNSUCCESSFUL;
}
#endif /* RTMP_MAC_PCI */
ASSERT((regID <= pAd->chipCap.MaxNumOfRfId));
for (i=0; i<MAX_BUSY_COUNT; i++)
{
if(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
return STATUS_UNSUCCESSFUL;
RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word);
if (rfcsr.field.RF_CSR_KICK == BUSY)
continue;
rfcsr.word = 0;
rfcsr.field.RF_CSR_WR = 0;
rfcsr.field.RF_CSR_KICK = 1;
rfcsr.field.TESTCSR_RFACC_REGNUM = regID;
RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
for (k=0; k<MAX_BUSY_COUNT; k++)
{
if(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
return STATUS_UNSUCCESSFUL;
RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word);
if (rfcsr.field.RF_CSR_KICK == IDLE)
break;
}
if ((rfcsr.field.RF_CSR_KICK == IDLE) &&
(rfcsr.field.TESTCSR_RFACC_REGNUM == regID))
{
*pValue = (UCHAR)(rfcsr.field.RF_CSR_DATA);
break;
}
}
if (rfcsr.field.RF_CSR_KICK == BUSY)
{
DBGPRINT_ERR(("RF read R%d=0x%X fail, i[%d], k[%d]\n", regID, rfcsr.word,i,k));
return STATUS_UNSUCCESSFUL;
}
return STATUS_SUCCESS;
}
BOOLEAN CFG80211DRV_OpsBeaconAdd(VOID *pAdOrg, VOID *pData)
{
PRTMP_ADAPTER pAd = (PRTMP_ADAPTER)pAdOrg;
CMD_RTPRIV_IOCTL_80211_BEACON *pBeacon;
UINT32 rx_filter_flag;
BOOLEAN Cancelled;
INT i;
PMULTISSID_STRUCT pMbss = &pAd->ApCfg.MBSSID[MAIN_MBSSID];
struct wifi_dev *wdev = &pMbss->wdev;
CFG80211DBG(RT_DEBUG_TRACE, ("80211> %s ==>\n", __FUNCTION__));
pBeacon = (CMD_RTPRIV_IOCTL_80211_BEACON *)pData;
#ifdef UAPSD_SUPPORT
pAd->ApCfg.MBSSID[0].UapsdInfo.bAPSDCapable = TRUE;
wdev->UapsdInfo.bAPSDCapable = TRUE;
pMbss->CapabilityInfo |= 0x0800;
#endif /* UAPSD_SUPPORT */
CFG80211DRV_UpdateApSettingFromBeacon(pAd, MAIN_MBSSID, pBeacon);
rx_filter_flag = APNORMAL;
RTMP_IO_WRITE32(pAd, RX_FILTR_CFG, rx_filter_flag); /* enable RX of DMA block */
pAd->ApCfg.BssidNum = 1;
pAd->MacTab.MsduLifeTime = 20; /* default 5 seconds */
/* CFG_TODO */
pAd->ApCfg.MBSSID[MAIN_MBSSID].BcnBufIdx = 0 ;
for(i = 0; i < WLAN_MAX_NUM_OF_TIM; i++)
pAd->ApCfg.MBSSID[MAIN_MBSSID].TimBitmaps[i] = 0;
pMbss->bBcnSntReq = TRUE;
/* For GO Timeout */
pAd->ApCfg.StaIdleTimeout = 300;
pMbss->StationKeepAliveTime = 0;
AsicDisableSync(pAd);
if (pAd->CommonCfg.Channel > 14)
pAd->CommonCfg.PhyMode = (WMODE_A | WMODE_AN);
else
pAd->CommonCfg.PhyMode = (WMODE_B | WMODE_G |WMODE_GN);
/* cfg_todo */
wdev->bWmmCapable = TRUE;
wdev->wdev_type = WDEV_TYPE_AP;
wdev->tx_pkt_allowed = ApAllowToSendPacket;
wdev->allow_data_tx = TRUE;
wdev->func_dev = (void *)&pAd->ApCfg.MBSSID[MAIN_MBSSID];
wdev->sys_handle = (void *)pAd;
#ifdef RT_CFG80211_P2P_CONCURRENT_DEVICE
/* Using netDev ptr from VifList if VifDevList Exist */
PNET_DEV pNetDev = NULL;
if ((pAd->cfg80211_ctrl.Cfg80211VifDevSet.vifDevList.size > 0) &&
((pNetDev = RTMP_CFG80211_FindVifEntry_ByType(pAd, RT_CMD_80211_IFTYPE_P2P_GO)) != NULL))
{
pMbss->MSSIDDev = pNetDev;
wdev->if_dev = pNetDev;
COPY_MAC_ADDR(wdev->bssid, pNetDev->dev_addr);
COPY_MAC_ADDR(wdev->if_addr, pNetDev->dev_addr);
RTMP_OS_NETDEV_SET_WDEV(pNetDev, wdev);
}
else
#endif /* RT_CFG80211_P2P_CONCURRENT_DEVICE */
{
pMbss->MSSIDDev = pAd->net_dev;
wdev->if_dev = pAd->net_dev;
COPY_MAC_ADDR(wdev->bssid, pAd->CurrentAddress);
COPY_MAC_ADDR(wdev->if_addr, pAd->CurrentAddress);
/* assoc to MBSSID's wdev */
RTMP_OS_NETDEV_SET_WDEV(pAd->net_dev, wdev);
}
DBGPRINT(RT_DEBUG_TRACE, ("New AP BSSID %02x:%02x:%02x:%02x:%02x:%02x (%d)\n",
PRINT_MAC(wdev->bssid), pAd->CommonCfg.PhyMode));
RTMPSetPhyMode(pAd, pAd->CommonCfg.PhyMode);
#ifdef DOT11_N_SUPPORT
if (WMODE_CAP_N(pAd->CommonCfg.PhyMode) && (pAd->Antenna.field.TxPath == 2))
bbp_set_txdac(pAd, 2);
else
#endif /* DOT11_N_SUPPORT */
bbp_set_txdac(pAd, 0);
/* Receiver Antenna selection */
bbp_set_rxpath(pAd, pAd->Antenna.field.RxPath);
if(!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED))
{
if (WMODE_CAP_N(pAd->CommonCfg.PhyMode) || wdev->bWmmCapable)
{
/* EDCA parameters used for AP's own transmission */
if (pAd->CommonCfg.APEdcaParm.bValid == FALSE)
set_default_ap_edca_param(pAd);
/* EDCA parameters to be annouced in outgoing BEACON, used by WMM STA */
if (pAd->ApCfg.BssEdcaParm.bValid == FALSE)
set_default_sta_edca_param(pAd);
AsicSetEdcaParm(pAd, &pAd->CommonCfg.APEdcaParm);
}
else
AsicSetEdcaParm(pAd, NULL);
}
#ifdef DOT11_N_SUPPORT
AsicSetRDG(pAd, pAd->CommonCfg.bRdg);
AsicSetRalinkBurstMode(pAd, pAd->CommonCfg.bRalinkBurstMode);
#endif /* DOT11_N_SUPPORT */
AsicSetBssid(pAd, pAd->CurrentAddress);
mgmt_tb_set_mcast_entry(pAd);
DBGPRINT(RT_DEBUG_TRACE, ("%s():Reset WCID Table\n", __FUNCTION__));
AsicDelWcidTab(pAd, WCID_ALL);
pAd->MacTab.Content[0].Addr[0] = 0x01;
pAd->MacTab.Content[0].HTPhyMode.field.MODE = MODE_OFDM;
pAd->MacTab.Content[0].HTPhyMode.field.MCS = 3;
pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel;
AsicBBPAdjust(pAd);
//MlmeSetTxPreamble(pAd, (USHORT)pAd->CommonCfg.TxPreamble);
#ifdef RT_CFG80211_P2P_CONCURRENT_DEVICE
/* P2P_GO */
MlmeUpdateTxRates(pAd, FALSE, MAIN_MBSSID + MIN_NET_DEVICE_FOR_CFG80211_VIF_P2P_GO);
#endif /* RT_CFG80211_P2P_CONCURRENT_DEVICE */
/*AP */
#ifdef RT_CFG80211_P2P_SUPPORT
if (!RTMP_CFG80211_VIF_P2P_GO_ON(pAd))
#endif
MlmeUpdateTxRates(pAd, FALSE, MIN_NET_DEVICE_FOR_MBSSID);
#ifdef DOT11_N_SUPPORT
if (WMODE_CAP_N(pAd->CommonCfg.PhyMode))
MlmeUpdateHtTxRates(pAd, MIN_NET_DEVICE_FOR_MBSSID);
#endif /* DOT11_N_SUPPORT */
/* Disable Protection first. */
if (!INFRA_ON(pAd))
AsicUpdateProtect(pAd, 0, (ALLN_SETPROTECT|CCKSETPROTECT|OFDMSETPROTECT), TRUE, FALSE);
APUpdateCapabilityAndErpIe(pAd);
#ifdef DOT11_N_SUPPORT
APUpdateOperationMode(pAd);
#endif /* DOT11_N_SUPPORT */
CFG80211_UpdateBeacon(pAd, pBeacon->beacon_head, pBeacon->beacon_head_len,
pBeacon->beacon_tail, pBeacon->beacon_tail_len,
TRUE);
/* Enable BSS Sync*/
AsicEnableApBssSync(pAd);
//pAd->P2pCfg.bSentProbeRSP = TRUE;
AsicSetPreTbtt(pAd, TRUE);
OPSTATUS_SET_FLAG(pAd, fOP_AP_STATUS_MEDIA_STATE_CONNECTED);
RTMP_IndicateMediaState(pAd, NdisMediaStateConnected);
#ifdef RT_CFG80211_SUPPORT
#ifdef RT_CFG80211_P2P_SUPPORT
if (!RTMP_CFG80211_VIF_P2P_GO_ON(pAd))
#endif /*RT_CFG80211_P2P_SUPPORT*/
wdev->Hostapd=Hostapd_CFG;
#endif /*RT_CFG80211_SUPPORT*/
return TRUE;
}
/*
==========================================================================
Description:
Load RF sleep-mode setup
==========================================================================
*/
VOID RT30xxLoadRFSleepModeSetup(
IN PRTMP_ADAPTER pAd)
{
UCHAR RFValue;
UINT32 MACValue;
if(!IS_RT3572(pAd))
{
#ifdef RT53xx
if (IS_RT5390(pAd))
{
UCHAR rfreg;
RT30xxReadRFRegister(pAd, RF_R01, &rfreg);
rfreg = ((rfreg & ~0x01) | 0x00); // vco_en
RT30xxWriteRFRegister(pAd, RF_R01, rfreg);
RT30xxReadRFRegister(pAd, RF_R06, &rfreg);
rfreg = ((rfreg & ~0xC0) | 0x00); // vco_ic (VCO bias current control, 00: off)
RT30xxWriteRFRegister(pAd, RF_R06, rfreg);
RT30xxReadRFRegister(pAd, RF_R22, &rfreg);
rfreg = ((rfreg & ~0xE0) | 0x00); // cp_ic (reference current control, 000: 0.25 mA)
RT30xxWriteRFRegister(pAd, RF_R22, rfreg);
RT30xxReadRFRegister(pAd, RF_R42, &rfreg);
rfreg = ((rfreg & ~0x40) | 0x00); // rx_ctb_en
RT30xxWriteRFRegister(pAd, RF_R42, rfreg);
/*
RT30xxReadRFRegister(pAd, RF_R20, &rfreg);
rfreg = ((rfreg & ~0x77) | 0x77); // ldo_pll_vc and ldo_rf_vc (111: -0.15)
RT30xxWriteRFRegister(pAd, RF_R20, rfreg);
*/
}
else
#endif // RT53xx //
{
// RF_BLOCK_en. RF R1 register Bit 0 to 0
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue &= (~0x01);
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
// VCO_IC, RF R7 register Bit 4 & Bit 5 to 0
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue &= (~0x30);
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
// Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0
RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
RFValue &= (~0x0E);
RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
// RX_CTB_en, RF R21 register Bit 7 to 0
RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
RFValue &= (~0x80);
RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
}
}
// Don't touch LDO_CFG0 for 3090F & 3593, possibly the board is single power scheme
if (IS_RT3090(pAd) || // IS_RT3090 including RT309x and RT3071/72
IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT5390(pAd) ||
(IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201)))
{
if (!IS_RT3572(pAd) && !IS_RT3390(pAd) && !IS_RT5390(pAd) && !IS_RT3090(pAd))
{
RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
RFValue |= 0x77;
RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
MACValue |= 0x1D000000;
RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
}
}
}
/*
========================================================================
Routine Description: Read RF register through MAC
Arguments:
Return Value:
IRQL =
Note:
========================================================================
*/
NDIS_STATUS rlt_rf_read(
IN RTMP_ADAPTER *pAd,
IN UCHAR bank,
IN UCHAR regID,
IN UCHAR *pValue)
{
RF_CSR_CFG_STRUC rfcsr = { { 0 } };
UINT i=0, k=0;
BOOLEAN rf_status;
NDIS_STATUS ret = STATUS_UNSUCCESSFUL;
#ifdef MT76x0
if (IS_MT7610U(pAd)) {
BANK_RF_REG_PAIR reg;
reg.Bank = bank;
reg.Register = regID;
RF_RANDOM_READ(pAd, ®, 1);
*pValue = reg.Value;
return NDIS_STATUS_SUCCESS;
}
#endif /* MT76x0 */
#ifdef RTMP_MAC_PCI
if ((pAd->bPCIclkOff == TRUE) || (pAd->LastMCUCmd == SLEEP_MCU_CMD))
{
DBGPRINT_ERR(("RT30xxReadRFRegister. Not allow to read RF 0x%x : fail\n", regID));
return STATUS_UNSUCCESSFUL;
}
#endif /* RTMP_MAC_PCI */
#ifdef RTMP_MAC_USB
if (IS_USB_INF(pAd)) {
RTMP_SEM_EVENT_WAIT(&pAd->reg_atomic, i);
if (i != 0) {
DBGPRINT(RT_DEBUG_ERROR, ("reg_atomic get failed(ret=%d)\n", i));
return STATUS_UNSUCCESSFUL;
}
}
#endif /* RTMP_MAC_USB */
ASSERT((regID <= pAd->chipCap.MaxNumOfRfId));
rfcsr.word = 0;
for (i=0; i<MAX_BUSY_COUNT; i++)
{
if(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
goto done;
rf_status = rf_csr_poll_idle(pAd, &rfcsr.word);
if ( rf_status == BUSY)
break;
rfcsr.word = 0;
#ifdef RT6352
if (IS_RT6352(pAd))
{
rfcsr.bank_6352.RF_CSR_WR = 0;
rfcsr.bank_6352.RF_CSR_KICK = 1;
rfcsr.bank_6352.TESTCSR_RFACC_REGNUM = (regID | (bank << 6));
}
else
#endif /* RT6352 */
#ifdef RT65xx
if (IS_RT65XX(pAd)) {
rfcsr.bank_65xx.RF_CSR_WR = 0;
rfcsr.bank_65xx.RF_CSR_KICK = 1;
rfcsr.bank_65xx.RF_CSR_REG_ID = regID;
rfcsr.bank_65xx.RF_CSR_REG_BANK = bank;
}
else
#endif /* RT65xx */
{
DBGPRINT_ERR(("RF[%d] read function for non-supported chip[0x%x]\n", regID, pAd->MACVersion));
break;
}
RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
rf_status = rf_csr_poll_idle(pAd, &rfcsr.word);
if (rf_status == IDLE)
{
#ifdef RT6352
if (IS_RT6352(pAd) && ((rfcsr.bank_6352.TESTCSR_RFACC_REGNUM & 0x3F) == regID))
{
*pValue = (UCHAR)(rfcsr.bank_6352.RF_CSR_DATA);
break;
}
#endif /* RT6352 */
#ifdef RT65xx
if (IS_RT65XX(pAd) && (rfcsr.bank_65xx.RF_CSR_REG_ID == regID) &&
(rfcsr.bank_65xx.RF_CSR_REG_BANK == bank))
{
*pValue = (UCHAR)(rfcsr.bank_65xx.RF_CSR_DATA);
break;
}
#endif /* RT65xx */
}
}
if (rf_status == BUSY)
{
DBGPRINT_ERR(("RF read R%d=0x%X fail, i[%d], k[%d]\n", regID, rfcsr.word,i,k));
goto done;
}
ret = STATUS_SUCCESS;
#if 0
if (bank >= RF_BANK4)
{
printk("TESTCSR_RFACC_REGNUM = %x, RF_CSR_DATA = %x !!!\n", rfcsr.field.TESTCSR_RFACC_REGNUM, rfcsr.field.RF_CSR_DATA);
}
#endif
done:
#ifdef RTMP_MAC_USB
if (IS_USB_INF(pAd)) {
RTMP_SEM_EVENT_UP(&pAd->reg_atomic);
}
#endif /* RTMP_MAC_USB */
return ret;
}
// Antenna divesity use GPIO3 and EESK pin for control
// Antenna and EEPROM access are both using EESK pin,
// Therefor we should avoid accessing EESK at the same time
// Then restore antenna after EEPROM access
// The original name of this function is AsicSetRxAnt(), now change to
//VOID AsicSetRxAnt(
VOID RT30xxSetRxAnt(
IN PRTMP_ADAPTER pAd,
IN UCHAR Ant)
{
UINT32 Value;
#ifdef RTMP_MAC_PCI
UINT32 x;
#endif // RTMP_MAC_PCI //
if (//(!pAd->NicConfig2.field.AntDiversity) ||
(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS)) ||
(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)) ||
(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF)) ||
(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)))
{
return;
}
#ifdef RT53xx
if (IS_RT5390(pAd)
#ifdef RT5390
#endif // RT5390 //
)
{
UCHAR BbpValue = 0;
if (Ant == 0) // 0: Main antenna
{
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R152, &BbpValue);
BbpValue = ((BbpValue & ~0x80) | (0x80));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R152, BbpValue);
DBGPRINT(RT_DEBUG_TRACE, ("AsicSetRxAnt, switch to main antenna\n"));
}
else // 1: Aux. antenna
{
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R152, &BbpValue);
BbpValue = ((BbpValue & ~0x80) | (0x00));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R152, BbpValue);
DBGPRINT(RT_DEBUG_TRACE, ("AsicSetRxAnt, switch to aux. antenna\n"));
}
}
else
#endif // RT53xx //
{
// the antenna selection is through firmware and MAC register(GPIO3)
if (Ant == 0)
{
// Main antenna
// E2PROM_CSR only in PCI bus Reg., USB Bus need MCU commad to control the EESK pin.
#ifdef RTMP_MAC_PCI
#ifdef RT5390
#endif // RT5390 //
{
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
x |= (EESK);
RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
}
#endif // RTMP_MAC_PCI //
RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value);
Value &= ~(0x0808);
RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value);
DBGPRINT_RAW(RT_DEBUG_TRACE, ("AsicSetRxAnt, switch to main antenna\n"));
}
else
{
// Aux antenna
// E2PROM_CSR only in PCI bus Reg., USB Bus need MCU commad to control the EESK pin.
#ifdef RTMP_MAC_PCI
#ifdef RT5390
#endif // RT5390 //
{
RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
x &= ~(EESK);
RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
}
#endif // RTMP_MAC_PCI //
RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value);
Value &= ~(0x0808);
Value |= 0x08;
RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value);
DBGPRINT_RAW(RT_DEBUG_TRACE, ("AsicSetRxAnt, switch to aux antenna\n"));
}
}
}
NDIS_STATUS rlt_rf_write(
IN PRTMP_ADAPTER pAd,
IN UCHAR bank,
IN UCHAR regID,
IN UCHAR value)
{
RF_CSR_CFG_STRUC rfcsr = { { 0 } };
NDIS_STATUS ret;
#ifdef RTMP_MAC_PCI
if ((pAd->bPCIclkOff == TRUE) || (pAd->LastMCUCmd == SLEEP_MCU_CMD))
{
DBGPRINT_ERR(("rlt_rf_write. Not allow to write RF 0x%x : fail\n", regID));
return STATUS_UNSUCCESSFUL;
}
#endif /* RTMP_MAC_PCI */
#ifdef RLT_MAC
// TODO: shiang-usw, why we need to check this for MT7601?? Get these code from MT7601!
if (pAd->chipCap.hif_type == HIF_RLT) {
if (pAd->WlanFunCtrl.field.WLAN_EN == 0)
{
DBGPRINT_ERR(("rlt_rf_write. Not allow to write RF 0x%x : fail\n", regID));
return STATUS_UNSUCCESSFUL;
}
}
#endif /* RLT_MAC */
#ifdef RTMP_MAC_USB
if (IS_USB_INF(pAd)) {
RTMP_SEM_EVENT_WAIT(&pAd->reg_atomic, ret);
if (ret != 0) {
DBGPRINT(RT_DEBUG_ERROR, ("reg_atomic get failed(ret=%d)\n", ret));
return STATUS_UNSUCCESSFUL;
}
}
#endif /* RTMP_MAC_USB */
ASSERT((regID <= pAd->chipCap.MaxNumOfRfId));
ret = STATUS_UNSUCCESSFUL;
if (rf_csr_poll_idle(pAd, &rfcsr.word) != IDLE)
goto done;
#ifdef RT6352
if (IS_RT6352(pAd))
{
rfcsr.bank_6352.RF_CSR_WR = 1;
rfcsr.bank_6352.RF_CSR_KICK = 1;
rfcsr.bank_6352.TESTCSR_RFACC_REGNUM = (regID | (bank << 6));
rfcsr.bank_6352.RF_CSR_DATA = value;
}
else
#endif /* RT6352 */
#ifdef RT65xx
if (IS_RT65XX(pAd)) {
rfcsr.bank_65xx.RF_CSR_WR = 1;
rfcsr.bank_65xx.RF_CSR_KICK = 1;
rfcsr.bank_65xx.RF_CSR_REG_BANK = bank;
rfcsr.bank_65xx.RF_CSR_REG_ID = regID;
rfcsr.bank_65xx.RF_CSR_DATA = value;
}
else
#endif /* RT65xx */
{
DBGPRINT_ERR(("%s():RF write with wrong handler!\n", __FUNCTION__));
goto done;
}
RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
ret = NDIS_STATUS_SUCCESS;
done:
#ifdef RTMP_MAC_USB
if (IS_USB_INF(pAd)) {
RTMP_SEM_EVENT_UP(&pAd->reg_atomic);
}
#endif /* RTMP_MAC_USB */
return ret;
}
/*
==========================================================================
Description:
Set RT28xx/RT2880 ATE RF BW
Return:
TRUE if all parameters are OK, FALSE otherwise
==========================================================================
*/
INT RT28xx_Set_ATE_TX_BW_Proc(
IN PRTMP_ADAPTER pAd,
IN PSTRING arg)
{
PATE_INFO pATEInfo = &(pAd->ate);
INT powerIndex;
UCHAR value = 0;
UCHAR BBPCurrentBW;
BBPCurrentBW = simple_strtol(arg, 0, 10);
if (BBPCurrentBW == 0)
{
pATEInfo->TxWI.BW = BW_20;
}
else
{
pATEInfo->TxWI.BW = BW_40;
}
#ifdef RELEASE_EXCLUDE
/* Fix the error spectrum of CCK-40MHZ. */
/* Turn on BBP 20MHz mode by request here. */
#endif /* RELEASE_EXCLUDE */
if ((pATEInfo->TxWI.TXWI_O.PHYMODE == MODE_CCK) && (pATEInfo->TxWI.TXWI_O.BW == BW_40))
{
DBGPRINT_ERR(("Set_ATE_TX_BW_Proc!! Warning!! CCK only supports 20MHZ!!\n"));
DBGPRINT_ERR(("Bandwidth switch to 20!!\n"));
pATEInfo->TxWI.BW = BW_20;
}
if (pATEInfo->TxWI.BW == BW_20)
{
if (pATEInfo->Channel <= 14)
{
/* BW=20;G band */
for (powerIndex=0; powerIndex<MAX_TXPOWER_ARRAY_SIZE; powerIndex++)
{
if (pAd->Tx20MPwrCfgGBand[powerIndex] == 0xffffffff)
continue;
/* TX_PWR_CFG_0 ~ TX_PWR_CFG_4 */
RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + powerIndex*4, pAd->Tx20MPwrCfgGBand[powerIndex]);
RtmpOsMsDelay(5);
}
}
else
{
/* BW=20;A band */
for (powerIndex=0; powerIndex<MAX_TXPOWER_ARRAY_SIZE; powerIndex++)
{
if (pAd->Tx20MPwrCfgABand[powerIndex] == 0xffffffff)
continue;
/* TX_PWR_CFG_0 ~ TX_PWR_CFG_4 */
RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + powerIndex*4, pAd->Tx20MPwrCfgABand[powerIndex]);
RtmpOsMsDelay(5);
}
}
/* set BW = 20 MHz */
/* Set BBP R4 bit[4:3]=0:0 */
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value);
value &= (~0x18);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value);
/* Set BBP R66=0x3C */
value = 0x3C;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, value);
/* set BW = 20 MHz */
pAd->LatchRfRegs.R4 &= ~0x00200000;
RtmpRfIoWrite(pAd);
/* BW = 20 MHz */
/* Set BBP R68=0x0B to improve Rx sensitivity. */
value = 0x0B;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R68, value);
/* Set BBP R69=0x16 */
value = 0x16;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, value);
/* Set BBP R70=0x08 */
value = 0x08;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, value);
/* Set BBP R73=0x11 */
value = 0x11;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, value);
#ifdef RELEASE_EXCLUDE
/*
If Channel=14, Bandwidth=20M and Mode=CCK, Set BBP R4 bit5=1
(to set Japan filter coefficients).
This segment of code will only works when ATETXMODE and ATECHANNEL
were set to MODE_CCK and 14 respectively before ATETXBW is set to 0.
*/
/*
Please don't move this block backward.
BBP_R4 should be overwritten for every chip if the condition matched.
*/
#endif /* RELEASE_EXCLUDE */
if (pATEInfo->Channel == 14)
{
INT TxMode = pATEInfo->TxWI.TXWI_O.PHYMODE;
if (TxMode == MODE_CCK)
{
/* when Channel==14 && Mode==CCK && BandWidth==20M, BBP R4 bit5=1 */
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value);
value |= 0x20; /* set bit5=1 */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value);
}
}
}
/* If bandwidth = 40M, set RF Reg4 bit 21 = 0. */
else if (pATEInfo->TxWI.TXWI_O.BW == BW_40)
{
if (pATEInfo->Channel <= 14)
{
/* BW=40;G band */
for (powerIndex=0; powerIndex<MAX_TXPOWER_ARRAY_SIZE; powerIndex++)
{
if (pAd->Tx40MPwrCfgGBand[powerIndex] == 0xffffffff)
continue;
/* TX_PWR_CFG_0 ~ TX_PWR_CFG_4 */
RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + powerIndex*4, pAd->Tx40MPwrCfgGBand[powerIndex]);
RtmpOsMsDelay(5);
}
}
else
{
/* BW=40;A band */
for (powerIndex=0; powerIndex<MAX_TXPOWER_ARRAY_SIZE; powerIndex++)
{
if (pAd->Tx40MPwrCfgABand[powerIndex] == 0xffffffff)
continue;
/* TX_PWR_CFG_0 ~ TX_PWR_CFG_4 */
RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + powerIndex*4, pAd->Tx40MPwrCfgABand[powerIndex]);
RtmpOsMsDelay(5);
}
if ((pATEInfo->TxWI.TXWI_O.PHYMODE >= 2) && (pATEInfo->TxWI.TXWI_O.MCS == 7))
{
value = 0x28;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R67, value);
}
}
/* Set BBP R4 bit[4:3]=1:0 */
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value);
value &= (~0x18);
value |= 0x10;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value);
/* Set BBP R66=0x3C */
value = 0x3C;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, value);
/* set BW = 40 MHz */
pAd->LatchRfRegs.R4 |= 0x00200000;
RtmpRfIoWrite(pAd);
/* BW = 40 MHz */
/* Set BBP R68=0x0C to improve Rx sensitivity. */
value = 0x0C;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R68, value);
/* Set BBP R69=0x1A */
value = 0x1A;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, value);
/* Set BBP R70=0x0A */
value = 0x0A;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, value);
/* Set BBP R73=0x16 */
value = 0x16;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, value);
}
return TRUE;
}
VOID NICInitRT3370RFRegisters(IN PRTMP_ADAPTER pAd)
{
INT i;
// Driver must read EEPROM to get RfIcType before initial RF registers
// Initialize RF register to default value
if (IS_RT3090(pAd)||IS_RT3390(pAd)||IS_RT3572(pAd))
{
// Init RF calibration
// Driver should toggle RF R30 bit7 before init RF registers
UINT32 RfReg = 0, data;
RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg);
RfReg |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
RTMPusecDelay(1000);
RfReg &= 0x7F;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
// init R24, R31
RT30xxWriteRFRegister(pAd, RF_R24, 0x0F);
RT30xxWriteRFRegister(pAd, RF_R31, 0x0F);
if (IS_RT3390(pAd))
{
// patch LNA_PE_G1 failed issue
RTMP_IO_READ32(pAd, GPIO_SWITCH, &data);
data &= ~(0x20);
RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data);
// RF registers initialization
for (i = 0; i < NUM_RF_REG_PARMS_OVER_RT3390; i++)
{
RT30xxWriteRFRegister(pAd, RFRegTableOverRT3390[i].Register, RFRegTableOverRT3390[i].Value);
}
}
// patch LNA_PE_G1 failed issue
RTMP_IO_READ32(pAd, GPIO_SWITCH, &data);
data &= ~(0x20);
RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data);
// Initialize RF register to default value
for (i = 0; i < NUM_RF_REG_PARMS_OVER_RT3390; i++)
{
RT30xxWriteRFRegister(pAd, RT30xx_RFRegTable[i].Register, RT30xx_RFRegTable[i].Value);
}
// Driver should set RF R6 bit6 on before calibration
RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg);
RfReg |= 0x40;
RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg);
//For RF filter Calibration
RTMPFilterCalibration(pAd);
// Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration()
if ((pAd->MACVersion & 0xffff) < 0x0211)
RT30xxWriteRFRegister(pAd, RF_R27, 0x3);
// set led open drain enable
RTMP_IO_READ32(pAd, OPT_14, &data);
data |= 0x01;
RTMP_IO_WRITE32(pAd, OPT_14, data);
// set default antenna as main
if (pAd->RfIcType == RFIC_3020)
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
// add by johnli, RF power sequence setup, load RF normal operation-mode setup
RT30xxLoadRFNormalModeSetup(pAd);
}
}
/* this abstract layer is to hide these difference. */
static void ChgMacLedCfg(
IN PRTMP_ADAPTER pAd)
{
LED_CFG_T LedCfgBuf;
BYTE DataTxActivity, BeaconTxActivity;
PSWMCU_LED_CONTROL pSWMCULedCntl = &pAd->LedCntl.SWMCULedCntl;
PLED_OPERATION_MODE pCurrentLedCfg = &pAd->LedCntl.SWMCULedCntl.CurrentLedCfg;
/*
** MCU_INT_STA (offset: 0x0414)
** bit 1: MTX2_INT, TX2Q to MAC frame transfer complete interrupt.
** bit 2: MTX1_INT, TX1Q to MAC frame transfer complete interrupt.
** bit 3: MTX0_INT, TX0Q to MAC frame transfer complete interrupt.
*/
if (TX_TRAFFIC_EXIST(pAd)) /* Check if there is Tx Traffic */
DataTxActivity = 1;
else
DataTxActivity = 0;
/* Check if there are beacon */
BeaconTxActivity = BEN_TC_ACT(pAd);
/* Clear Tx and beacon Tx complete interrupt */
RTMP_IO_WRITE32(pAd, MCU_INT_STATUS, 0x1e);
RTMP_IO_READ32(pAd, MAC_LED_CFG, &LedCfgBuf.word);
/* For backward compatible issue,
* LedActMode: 0: None, 1: Solid ON, 2: Blink (data/mgr), 3: Blink (data,mgr,beacon)
* =>Solid off = solid on + high polarity
*/
#ifdef RT5350
//#if defined(RT5350) || defined(RT6352)
LedCfgBuf.field.LED_POL = !pCurrentLedCfg->field.LedActPolarity;
#else
LedCfgBuf.field.LED_POL = pCurrentLedCfg->field.LedActPolarity;
#endif
if(pSWMCULedCntl->LedBlinkTimer!=0)
pSWMCULedCntl->LedBlinkTimer--;
else
pSWMCULedCntl->LedBlinkTimer = 0xff;
/* LED Act. connect to G_LED. */
if (pSWMCULedCntl->LedParameter.LedMode == LED_MODE_8SEC_SCAN && pSWMCULedCntl->BlinkFor8sTimer)
{
UINT8 LedPolarity = pCurrentLedCfg->field.LedActPolarity ? 0 : 3;
LedCfgBuf.field.G_LED_MODE = GetBitX(pSWMCULedCntl->LedBlinkTimer, 0) ? LedPolarity : ~LedPolarity;
pSWMCULedCntl->BlinkFor8sTimer--;
}
else if (pCurrentLedCfg->field.LedActMode == MCU_LED_ACT_OFF)
{
LedCfgBuf.field.G_LED_MODE =
pCurrentLedCfg->field.LedActPolarity ? MAC_LED_ON : MAC_LED_OFF;
}
else if (pCurrentLedCfg->field.LedActMode == MCU_LED_ACT_SOLID_ON)
{
LedCfgBuf.field.G_LED_MODE =
pCurrentLedCfg->field.LedActPolarity ? MAC_LED_OFF : MAC_LED_ON;
}
else if ((DataTxActivity && pCurrentLedCfg->field.LedActMode > MCU_LED_ACT_SOLID_ON) /* Data packet transmited. */
|| (BeaconTxActivity && pCurrentLedCfg->field.LedActMode == MCU_LED_ACT_BLINK_UPON_TX_DATA_MNG_BEN)) /* Beacon frame transmited. */
{
LedCfgBuf.field.G_LED_MODE = GetBitX(pSWMCULedCntl->LedBlinkTimer, 0) ? MAC_LED_ON : MAC_LED_OFF;
}
else if (!DataTxActivity && !BeaconTxActivity)
{
if (pCurrentLedCfg->field.LedActModeNoTx == 0) /* solid on when no tx. */
LedCfgBuf.field.G_LED_MODE =
pCurrentLedCfg->field.LedActPolarity ? MAC_LED_OFF : MAC_LED_ON;
else /* slow blink. */
LedCfgBuf.field.G_LED_MODE = GetBitX(pSWMCULedCntl->LedBlinkTimer, 4) ? MAC_LED_ON : MAC_LED_OFF;
}
/* LED G. connect to Y_LED. */
if (pCurrentLedCfg->field.LedGMode == MCU_LED_G_FAST_BLINK)
LedCfgBuf.field.Y_LED_MODE = GetBitX(pSWMCULedCntl->LedBlinkTimer, 0) ? MAC_LED_ON : MAC_LED_OFF;
else if (pCurrentLedCfg->field.LedGMode == MCU_LED_G_SLOW_BLINK)
LedCfgBuf.field.Y_LED_MODE = GetBitX(pSWMCULedCntl->LedBlinkTimer, 4) ? MAC_LED_ON : MAC_LED_OFF;
else if (pCurrentLedCfg->field.LedGMode == MCU_LED_G_SOLID_ON)
LedCfgBuf.field.Y_LED_MODE =
pCurrentLedCfg->field.LedGPolarity ? MAC_LED_OFF : MAC_LED_ON;
else /* dark */
LedCfgBuf.field.Y_LED_MODE =
pCurrentLedCfg->field.LedGPolarity ? MAC_LED_ON : MAC_LED_OFF;
/* LED A. connect to R_LED. */
if (pCurrentLedCfg->field.LedAMode == MCU_LED_A_FAST_BLINK)
LedCfgBuf.field.R_LED_MODE = GetBitX(pSWMCULedCntl->LedBlinkTimer, 0) ? MAC_LED_ON : MAC_LED_OFF;
else if (pCurrentLedCfg->field.LedAMode == MCU_LED_A_SLOW_BLINK)
LedCfgBuf.field.R_LED_MODE = GetBitX(pSWMCULedCntl->LedBlinkTimer, 4) ? MAC_LED_ON : MAC_LED_OFF;
else if (pCurrentLedCfg->field.LedAMode == MCU_LED_A_SOLID_ON)
LedCfgBuf.field.R_LED_MODE =
pCurrentLedCfg->field.LedAPolarity ? MAC_LED_OFF : MAC_LED_ON;
else
LedCfgBuf.field.R_LED_MODE =
pCurrentLedCfg->field.LedAPolarity ? MAC_LED_ON : MAC_LED_OFF;
if ((pSWMCULedCntl->bWlanLed) && !RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF))
{
RTMP_IO_WRITE32(pAd, MAC_LED_CFG, LedCfgBuf.word);
}
else
{
{
RTMP_IO_WRITE32(pAd, MAC_LED_CFG, 0);
}
}
return;
}
/*
==========================================================================
Description:
This routine is executed every second -
1. Decide the overall channel quality
2. Check if need to upgrade the TX rate to any client
3. perform MAC table maintenance, including ageout no-traffic clients,
and release packet buffer in PSQ is fail to TX in time.
==========================================================================
*/
VOID APMlmePeriodicExec(
PRTMP_ADAPTER pAd)
{
/*
Reqeust by David 2005/05/12
It make sense to disable Adjust Tx Power on AP mode, since we can't
take care all of the client's situation
ToDo: need to verify compatibility issue with WiFi product.
*/
#ifdef CARRIER_DETECTION_SUPPORT
if (isCarrierDetectExist(pAd) == TRUE)
{
PCARRIER_DETECTION_STRUCT pCarrierDetect = &pAd->CommonCfg.CarrierDetect;
if (pCarrierDetect->OneSecIntCount < pCarrierDetect->CarrierGoneThreshold)
{
pCarrierDetect->CD_State = CD_NORMAL;
pCarrierDetect->recheck = pCarrierDetect->recheck1;
if (pCarrierDetect->Debug != RT_DEBUG_TRACE)
{
DBGPRINT(RT_DEBUG_TRACE, ("Carrier gone\n"));
/* start all TX actions. */
APMakeAllBssBeacon(pAd);
APUpdateAllBeaconFrame(pAd);
AsicEnableBssSync(pAd);
}
else
{
printk("Carrier gone\n");
}
}
pCarrierDetect->OneSecIntCount = 0;
}
#endif /* CARRIER_DETECTION_SUPPORT */
RTMP_CHIP_HIGH_POWER_TUNING(pAd, &pAd->ApCfg.RssiSample);
/* Disable Adjust Tx Power for WPA WiFi-test. */
/* Because high TX power results in the abnormal disconnection of Intel BG-STA. */
/*#ifndef WIFI_TEST */
/* if (pAd->CommonCfg.bWiFiTest == FALSE) */
/* for SmartBit 64-byte stream test */
/* removed based on the decision of Ralink congress at 2011/7/06 */
/* if (pAd->MacTab.Size > 0) */
AsicAdjustTxPower(pAd);
/*#endif // WIFI_TEST */
#ifdef RTMP_TEMPERATURE_COMPENSATION
MT76x0_TemperatureCompensation(pAd);
#endif /* RTMP_TEMPERATURE_COMPENSATION */
/* BBP TUNING: dynamic tune BBP R66 to find a balance between sensibility
and noise isolation */
/* AsicBbpTuning2(pAd); */
/* walk through MAC table, see if switching TX rate is required */
/* MAC table maintenance */
if (pAd->Mlme.PeriodicRound % MLME_TASK_EXEC_MULTIPLE == 0)
{
/* one second timer */
MacTableMaintenance(pAd);
#ifdef FPGA_MODE
if (pAd->fpga_tr_stop)
{
UINT32 mac_val;
/* enable/disable tx/rx*/
RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &mac_val);
switch (pAd->fpga_tr_stop)
{
case 3: //stop tx + rx
mac_val &= (~0xc);
break;
case 2: // stop rx
mac_val &= (~0x8);
break;
case 1: // stop tx
mac_val &= (~0x4);
break;
case 4:
default:
mac_val |= 0x0c;
break;
}
RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, mac_val);
}
#endif /* FGPA_MODE */
RTMPMaintainPMKIDCache(pAd);
#ifdef WDS_SUPPORT
WdsTableMaintenance(pAd);
#endif /* WDS_SUPPORT */
#ifdef CLIENT_WDS
CliWds_ProxyTabMaintain(pAd);
#endif /* CLIENT_WDS */
}
APUpdateCapabilityAndErpIe(pAd);
#ifdef APCLI_SUPPORT
if (pAd->Mlme.OneSecPeriodicRound % 2 == 0)
ApCliIfMonitor(pAd);
if (pAd->Mlme.OneSecPeriodicRound % 2 == 1)
ApCliIfUp(pAd);
{
INT loop;
ULONG Now32;
UINT32 MaxWcidNum = MAX_LEN_OF_MAC_TABLE;
#ifdef MAC_REPEATER_SUPPORT
if (pAd->ApCfg.bMACRepeaterEn)
{
MaxWcidNum = MAX_MAC_TABLE_SIZE_WITH_REPEATER;
#ifdef APCLI_AUTO_CONNECT_SUPPORT
RTMPRepeaterReconnectionCheck(pAd);
#endif /* APCLI_AUTO_CONNECT_SUPPORT */
}
#endif /* MAC_REPEATER_SUPPORT */
NdisGetSystemUpTime(&Now32);
for (loop = 0; loop < MAX_APCLI_NUM; loop++)
{
PAPCLI_STRUCT pApCliEntry = &pAd->ApCfg.ApCliTab[loop];
if ((pApCliEntry->Valid == TRUE)
&& (pApCliEntry->MacTabWCID < MaxWcidNum))
{
/* update channel quality for Roaming and UI LinkQuality display */
MlmeCalculateChannelQuality(pAd,
&pAd->MacTab.Content[pApCliEntry->MacTabWCID], Now32);
}
}
}
#endif /* APCLI_SUPPORT */
#ifdef DOT11_N_SUPPORT
if (pAd->CommonCfg.bHTProtect)
{
/*APUpdateCapabilityAndErpIe(pAd); */
APUpdateOperationMode(pAd);
if (pAd->CommonCfg.IOTestParm.bRTSLongProtOn == FALSE)
{
AsicUpdateProtect(pAd, (USHORT)pAd->CommonCfg.AddHTInfo.AddHtInfo2.OperaionMode, ALLN_SETPROTECT, FALSE, pAd->MacTab.fAnyStationNonGF);
}
}
#endif /* DOT11_N_SUPPORT */
#ifdef A_BAND_SUPPORT
if ( (pAd->CommonCfg.Channel > 14)
&& (pAd->CommonCfg.bIEEE80211H == 1)
)
{
#ifdef DFS_SUPPORT
ApRadarDetectPeriodic(pAd);
#else
pAd->Dot11_H.InServiceMonitorCount++;
if (pAd->Dot11_H.RDMode == RD_SILENCE_MODE)
{
if (pAd->Dot11_H.RDCount++ > pAd->Dot11_H.ChMovingTime)
{
AsicEnableBssSync(pAd);
pAd->Dot11_H.RDMode = RD_NORMAL_MODE;
}
}
#endif /* !DFS_SUPPORT */
}
#endif /* A_BAND_SUPPORT */
/* resume Improved Scanning*/
if ((pAd->ApCfg.bImprovedScan) &&
(!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS)) &&
(pAd->Mlme.ApSyncMachine.CurrState == AP_SCAN_PENDING))
{
MLME_SCAN_REQ_STRUCT ScanReq;
AsicDisableSync(pAd);
RTMPZeroMemory(ScanReq.Ssid, MAX_LEN_OF_SSID);
ScanReq.SsidLen = pAd->MlmeAux.SsidLen;
NdisMoveMemory(ScanReq.Ssid, pAd->MlmeAux.Ssid, ScanReq.SsidLen);
ScanReq.BssType = BSS_ANY;
#ifdef APCLI_CONNECTION_TRIAL
ScanReq.ScanType = FAST_SCAN_ACTIVE;
#else
ScanReq.ScanType = SCAN_ACTIVE;
#endif /* APCLI_CONNECTION_TRIAL */
MlmeEnqueue(pAd, AP_SYNC_STATE_MACHINE, APMT2_MLME_SCAN_REQ, sizeof(MLME_SCAN_REQ_STRUCT), &ScanReq, 0);
RTMP_MLME_HANDLER(pAd);
DBGPRINT(RT_DEBUG_TRACE, ("bImprovedScan ............. Resume for bImprovedScan, SCAN_PENDING .............. \n"));
}
}
void NICInitRT3090RFRegisters(struct rt_rtmp_adapter *pAd)
{
int i;
/* Driver must read EEPROM to get RfIcType before initial RF registers */
/* Initialize RF register to default value */
if (IS_RT3090(pAd)) {
/* Init RF calibration */
/* Driver should toggle RF R30 bit7 before init RF registers */
u32 RfReg = 0, data;
RT30xxReadRFRegister(pAd, RF_R30, (u8 *)&RfReg);
RfReg |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R30, (u8)RfReg);
RTMPusecDelay(1000);
RfReg &= 0x7F;
RT30xxWriteRFRegister(pAd, RF_R30, (u8)RfReg);
/* init R24, R31 */
RT30xxWriteRFRegister(pAd, RF_R24, 0x0F);
RT30xxWriteRFRegister(pAd, RF_R31, 0x0F);
/* RT309x version E has fixed this issue */
if ((pAd->NicConfig2.field.DACTestBit == 1)
&& ((pAd->MACVersion & 0xffff) < 0x0211)) {
/* patch tx EVM issue temporarily */
RTMP_IO_READ32(pAd, LDO_CFG0, &data);
data = ((data & 0xE0FFFFFF) | 0x0D000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
} else {
RTMP_IO_READ32(pAd, LDO_CFG0, &data);
data = ((data & 0xE0FFFFFF) | 0x01000000);
RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
}
/* patch LNA_PE_G1 failed issue */
RTMP_IO_READ32(pAd, GPIO_SWITCH, &data);
data &= ~(0x20);
RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data);
/* Initialize RF register to default value */
for (i = 0; i < NUM_RF_REG_PARMS; i++) {
RT30xxWriteRFRegister(pAd,
RT30xx_RFRegTable[i].Register,
RT30xx_RFRegTable[i].Value);
}
/* Driver should set RF R6 bit6 on before calibration */
RT30xxReadRFRegister(pAd, RF_R06, (u8 *)&RfReg);
RfReg |= 0x40;
RT30xxWriteRFRegister(pAd, RF_R06, (u8)RfReg);
/*For RF filter Calibration */
RTMPFilterCalibration(pAd);
/* Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration() */
if ((pAd->MACVersion & 0xffff) < 0x0211)
RT30xxWriteRFRegister(pAd, RF_R27, 0x3);
/* set led open drain enable */
RTMP_IO_READ32(pAd, OPT_14, &data);
data |= 0x01;
RTMP_IO_WRITE32(pAd, OPT_14, data);
/* set default antenna as main */
if (pAd->RfIcType == RFIC_3020)
AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
/* add by johnli, RF power sequence setup, load RF normal operation-mode setup */
RT30xxLoadRFNormalModeSetup(pAd);
}
}
VOID RT35xx_ChipBBPAdjust(
IN RTMP_ADAPTER *pAd)
{
UINT32 Value;
UCHAR byteValue = 0;
#ifdef RT3593
/* 3x3 device will not run AsicEvaluateRxAnt*/
if (IS_RT3593(pAd))
{
UCHAR BBPValue = 0;
/* Receiver Antenna Selection*/
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BBPValue);
if(pAd->Antenna.field.RxPath == 3)
{
BBPValue |= (0x10);
}
else if(pAd->Antenna.field.RxPath == 2)
{
BBPValue |= (0x8);
}
else if(pAd->Antenna.field.RxPath == 1)
{
BBPValue |= (0x0);
}
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBPValue);
/*Number of transmitter chains*/
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BBPValue);
BBPValue &= (~0x18);
if (pAd->Antenna.field.TxPath == 3)
BBPValue |= 0x10;
else if (pAd->Antenna.field.TxPath == 2)
BBPValue |= 0x08;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BBPValue);
}
#endif /* RT3593 */
#ifdef DOT11_N_SUPPORT
if ((pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth == BW_40) &&
(pAd->CommonCfg.RegTransmitSetting.field.EXTCHA == EXTCHA_ABOVE))
{
pAd->CommonCfg.BBPCurrentBW = BW_40;
pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel + 2;
/* TX : control channel at lower */
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x1);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* RX : control channel at lower */
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &byteValue);
byteValue &= (~0x20);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, byteValue);
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue);
byteValue &= (~0x18);
byteValue |= 0x10;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue);
if (pAd->CommonCfg.Channel > 14)
{ /* request by Gary 20070208 for middle and long range A Band*/
if (IS_RT3572(pAd))
AsicBBPWriteWithRxChain(pAd, BBP_R66, 0x48, RX_CHAIN_ALL);
}
else
{ /* request by Gary 20070208 for middle and long range G Band*/
if (IS_RT3572(pAd))
AsicBBPWriteWithRxChain(pAd, BBP_R66, 0x38, RX_CHAIN_ALL);
}
if (pAd->MACVersion == 0x28600100)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x1A);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x16);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10);
}
DBGPRINT(RT_DEBUG_TRACE, ("ApStartUp : ExtAbove, ChannelWidth=%d, Channel=%d, ExtChanOffset=%d(%d) \n",
pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth,
pAd->CommonCfg.Channel,
pAd->CommonCfg.RegTransmitSetting.field.EXTCHA,
pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset));
}
else if ((pAd->CommonCfg.Channel > 2) &&
(pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth == BW_40) &&
(pAd->CommonCfg.RegTransmitSetting.field.EXTCHA == EXTCHA_BELOW))
{
pAd->CommonCfg.BBPCurrentBW = BW_40;
if (pAd->CommonCfg.Channel == 14)
pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel - 1;
else
pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel - 2;
/* TX : control channel at upper */
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value |= (0x1);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* RX : control channel at upper */
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &byteValue);
byteValue |= (0x20);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, byteValue);
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue);
byteValue &= (~0x18);
byteValue |= 0x10;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue);
if (pAd->CommonCfg.Channel > 14)
{ /* request by Gary 20070208 for middle and long range A Band*/
if (IS_RT3572(pAd))
AsicBBPWriteWithRxChain(pAd, BBP_R66, 0x48, RX_CHAIN_ALL);
}
else
{ /* request by Gary 20070208 for middle and long range G band*/
if (IS_RT3572(pAd))
AsicBBPWriteWithRxChain(pAd, BBP_R66, 0x38, RX_CHAIN_ALL);
}
if (pAd->MACVersion == 0x28600100)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x1A);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x16);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10);
}
DBGPRINT(RT_DEBUG_TRACE, ("ApStartUp : ExtBlow, ChannelWidth=%d, Channel=%d, ExtChanOffset=%d(%d) \n",
pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth,
pAd->CommonCfg.Channel,
pAd->CommonCfg.RegTransmitSetting.field.EXTCHA,
pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset));
}
else
#endif /* DOT11_N_SUPPORT */
{
pAd->CommonCfg.BBPCurrentBW = BW_20;
pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel;
/* TX : control channel at lower */
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x1);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue);
byteValue &= (~0x18);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue);
/* 20 MHz bandwidth*/
if (pAd->CommonCfg.Channel > 14)
{ /* request by Gary 20070208*/
if (IS_RT3572(pAd))
AsicBBPWriteWithRxChain(pAd, BBP_R66, 0x40, RX_CHAIN_ALL);
}
else
{ /* request by Gary 20070208*/
/*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, 0x30);*/
/* request by Brian 20070306*/
if (IS_RT3572(pAd))
AsicBBPWriteWithRxChain(pAd, BBP_R66, 0x38, RX_CHAIN_ALL);
}
if (pAd->MACVersion == 0x28600100)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x08);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x11);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0a);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10);
}
#ifdef DOT11_N_SUPPORT
DBGPRINT(RT_DEBUG_TRACE, ("ApStartUp : 20MHz, ChannelWidth=%d, Channel=%d, ExtChanOffset=%d(%d) \n",
pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth,
pAd->CommonCfg.Channel,
pAd->CommonCfg.RegTransmitSetting.field.EXTCHA,
pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset));
#endif /* DOT11_N_SUPPORT */
}
if (pAd->CommonCfg.Channel > 14)
{ /* request by Gary 20070208 for middle and long range A Band*/
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, 0x1D);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, 0x1D);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, 0x1D);
/*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x1D);*/
}
else
{ /* request by Gary 20070208 for middle and long range G band*/
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, 0x2D);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, 0x2D);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, 0x2D);
/*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x2D);*/
}
}