void WSwan_InterruptWrite(uint32 A, uint8 V)
{
//printf("Write: %04x %02x\n", A, V);
switch(A)
{
case 0xB0: IVectorBase = V; RecalcInterrupt(); break;
case 0xB2: IEnable = V; IStatus &= IEnable; RecalcInterrupt(); break;
case 0xB6: /*printf("IStatus: %02x\n", V);*/ IStatus &= ~V; RecalcInterrupt(); break;
}
}
void WSwan_InterruptReset(void)
{
IEnable = 0x00;
IStatus = 0x00;
IVectorBase = 0x00;
RecalcInterrupt();
}
void WSwan_Interrupt(int which)
{
if(IEnable & (1 << which))
IStatus |= 1 << which;
//printf("Interrupt: %d\n", which);
RecalcInterrupt();
}
void WSwan_InterruptSetRegister(const std::string &oname, uint32 value)
{
if(oname == "IStatus")
IStatus = value;
if(oname == "IEnable")
IEnable = value;
if(oname == "IVectorBase")
IVectorBase = value;
RecalcInterrupt();
}
void WSwan_InterruptAssert(unsigned which, bool asserted)
{
const uint8 prev_IAsserted = IAsserted;
IAsserted &= ~(1U << which);
IAsserted |= (unsigned)asserted << which;
IStatus |= ((prev_IAsserted ^ IAsserted) & IAsserted) & IEnable;
RecalcInterrupt();
}
int WSwan_InterruptStateAction(StateMem *sm, int load, int data_only)
{
SFORMAT StateRegs[] =
{
SFVAR(IStatus),
SFVAR(IEnable),
SFVAR(IVectorBase),
SFEND
};
if(!MDFNSS_StateAction(sm, load, data_only, StateRegs, "INTR"))
return(0);
if(load)
RecalcInterrupt();
return(1);
}
void WSwan_Interrupt(unsigned which)
{
IStatus |= (1U << which) & IEnable;
RecalcInterrupt();
}