INT WaitForAsicReady(
IN RTMP_ADAPTER *pAd)
{
UINT32 mac_val = 0, reg = MAC_CSR0;
int idx = 0;
#ifdef RT3290
if (IS_RT3290(pAd))
reg = ASIC_VERSION;
#endif /* RT3290 */
do
{
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
return FALSE;
RTMP_IO_READ32(pAd, reg, &mac_val);
if ((mac_val != 0x00) && (mac_val != 0xFFFFFFFF))
return TRUE;
RtmpOsMsDelay(5);
} while (idx++ < 500);
DBGPRINT(RT_DEBUG_ERROR,
("%s(0x%x):AsicNotReady!\n",
__FUNCTION__, mac_val));
return FALSE;
}
VOID RtmpDmaEnable(
IN PRTMP_ADAPTER pAd,
IN INT Enable)
{
BOOLEAN value;
ULONG WaitCnt;
WPDMA_GLO_CFG_STRUC GloCfg;
value = Enable > 0 ? 1 : 0;
/* check if DMA is in busy mode or not. */
WaitCnt = 0;
while (TxDmaBusy(pAd) || RxDmaBusy(pAd))
{
RTMPusecDelay(10);
if (WaitCnt++ > 100)
break;
}
RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word); /* disable DMA */
GloCfg.field.EnableTxDMA = value;
GloCfg.field.EnableRxDMA = value;
RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, GloCfg.word); /* abort all TX rings */
RtmpOsMsDelay(5);
return;
}
INT WaitForAsicReady(RTMP_ADAPTER *pAd)
{
UINT32 mac_val = 0, reg;
int idx = 0;
// TODO: shiang-7603
return TRUE;
if (pAd->chipCap.hif_type == HIF_MT) {
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_OFF, ("%s(%d): Not support for HIF_MT yet!\n",
__FUNCTION__, __LINE__));
return TRUE;
}
#if defined(RTMP_MAC) || defined(RLT_MAC)
reg = MAC_CSR0;
do
{
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
return FALSE;
RTMP_IO_READ32(pAd, reg, &mac_val);
if ((mac_val != 0x00) && (mac_val != 0xFFFFFFFF))
return TRUE;
RtmpOsMsDelay(5);
} while (idx++ < 500);
#endif /* defined(RTMP_MAC) || defined(RLT_MAC) */
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_ERROR,
("%s(0x%x):AsicNotReady!\n",
__FUNCTION__, mac_val));
return FALSE;
}
VOID RtmpDmaEnable(
IN PRTMP_ADAPTER pAd,
IN INT Enable)
{
BOOLEAN value;
ULONG WaitCnt;
USB_DMA_CFG_STRUC UsbCfg;
value = Enable > 0 ? 1 : 0;
/* check DMA is in busy mode. */
WaitCnt = 0;
while (TxDmaBusy(pAd) || RxDmaBusy(pAd))
{
RTMPusecDelay(10);
if (WaitCnt++ > 100)
break;
}
RTMP_IO_READ32(pAd, USB_DMA_CFG, &UsbCfg.word); /* disable DMA */
UsbCfg.field.TxBulkEn = value;
UsbCfg.field.RxBulkEn = value;
RTMP_IO_WRITE32(pAd, USB_DMA_CFG, UsbCfg.word); /* abort all TX rings */
RtmpOsMsDelay(5);
return;
}
/*
========================================================================
Routine Description: Write RT30xx RF register through MAC
Arguments:
Return Value:
IRQL =
Note:
========================================================================
*/
NDIS_STATUS RT30xxWriteRFRegister(
IN PRTMP_ADAPTER pAd,
IN UCHAR regID,
IN UCHAR value)
{
RF_CSR_CFG_STRUC rfcsr = { { 0 } };
UINT i = 0;
ASSERT((regID <= pAd->chipCap.MaxNumOfRfId));
do
{
RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word);
if (!rfcsr.field.RF_CSR_KICK)
break;
i++;
}
while ((i < MAX_BUSY_COUNT) && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)));
if ((i == MAX_BUSY_COUNT) || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)))
{
DBGPRINT_RAW(RT_DEBUG_ERROR, ("Retry count exhausted or device removed!!!\n"));
return STATUS_UNSUCCESSFUL;
}
rfcsr.field.RF_CSR_WR = 1;
rfcsr.field.RF_CSR_KICK = 1;
rfcsr.field.TESTCSR_RFACC_REGNUM = regID;
if ((pAd->chipCap.RfReg17WtMethod == RF_REG_WT_METHOD_STEP_ON) && (regID == RF_R17))
{
UCHAR IdRf;
UCHAR RfValue;
BOOLEAN beAdd;
RT30xxReadRFRegister(pAd, RF_R17, &RfValue);
beAdd = (RfValue < value) ? TRUE : FALSE;
IdRf = RfValue;
while(IdRf != value)
{
if (beAdd)
IdRf++;
else
IdRf--;
rfcsr.field.RF_CSR_DATA = IdRf;
RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
RtmpOsMsDelay(1);
}
}
rfcsr.field.RF_CSR_DATA = value;
RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
return NDIS_STATUS_SUCCESS;
}
/*
========================================================================
Routine Description:
Arguments:
Return Value:
None
Note:
========================================================================
*/
VOID ATEResetBulkIn(
IN PRTMP_ADAPTER pAd)
{
if ((pAd->PendingRx > 0) && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)))
{
DBGPRINT_ERR(("ATE : BulkIn IRP Pending!!!\n"));
ATE_RTUSBCancelPendingBulkInIRP(pAd);
RtmpOsMsDelay(100);
pAd->PendingRx = 0;
}
return;
}
/*
==========================================================================
Description:
Set RT28xx/RT2880 ATE RF BW
Return:
TRUE if all parameters are OK, FALSE otherwise
==========================================================================
*/
INT RT28xx_Set_ATE_TX_BW_Proc(
IN PRTMP_ADAPTER pAd,
IN PSTRING arg)
{
PATE_INFO pATEInfo = &(pAd->ate);
INT powerIndex;
UCHAR value = 0;
UCHAR BBPCurrentBW;
BBPCurrentBW = simple_strtol(arg, 0, 10);
if (BBPCurrentBW == 0)
{
pATEInfo->TxWI.BW = BW_20;
}
else
{
pATEInfo->TxWI.BW = BW_40;
}
#ifdef RELEASE_EXCLUDE
/* Fix the error spectrum of CCK-40MHZ. */
/* Turn on BBP 20MHz mode by request here. */
#endif /* RELEASE_EXCLUDE */
if ((pATEInfo->TxWI.TXWI_O.PHYMODE == MODE_CCK) && (pATEInfo->TxWI.TXWI_O.BW == BW_40))
{
DBGPRINT_ERR(("Set_ATE_TX_BW_Proc!! Warning!! CCK only supports 20MHZ!!\n"));
DBGPRINT_ERR(("Bandwidth switch to 20!!\n"));
pATEInfo->TxWI.BW = BW_20;
}
if (pATEInfo->TxWI.BW == BW_20)
{
if (pATEInfo->Channel <= 14)
{
/* BW=20;G band */
for (powerIndex=0; powerIndex<MAX_TXPOWER_ARRAY_SIZE; powerIndex++)
{
if (pAd->Tx20MPwrCfgGBand[powerIndex] == 0xffffffff)
continue;
/* TX_PWR_CFG_0 ~ TX_PWR_CFG_4 */
RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + powerIndex*4, pAd->Tx20MPwrCfgGBand[powerIndex]);
RtmpOsMsDelay(5);
}
}
else
{
/* BW=20;A band */
for (powerIndex=0; powerIndex<MAX_TXPOWER_ARRAY_SIZE; powerIndex++)
{
if (pAd->Tx20MPwrCfgABand[powerIndex] == 0xffffffff)
continue;
/* TX_PWR_CFG_0 ~ TX_PWR_CFG_4 */
RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + powerIndex*4, pAd->Tx20MPwrCfgABand[powerIndex]);
RtmpOsMsDelay(5);
}
}
/* set BW = 20 MHz */
/* Set BBP R4 bit[4:3]=0:0 */
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value);
value &= (~0x18);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value);
/* Set BBP R66=0x3C */
value = 0x3C;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, value);
/* set BW = 20 MHz */
pAd->LatchRfRegs.R4 &= ~0x00200000;
RtmpRfIoWrite(pAd);
/* BW = 20 MHz */
/* Set BBP R68=0x0B to improve Rx sensitivity. */
value = 0x0B;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R68, value);
/* Set BBP R69=0x16 */
value = 0x16;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, value);
/* Set BBP R70=0x08 */
value = 0x08;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, value);
/* Set BBP R73=0x11 */
value = 0x11;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, value);
#ifdef RELEASE_EXCLUDE
/*
If Channel=14, Bandwidth=20M and Mode=CCK, Set BBP R4 bit5=1
(to set Japan filter coefficients).
This segment of code will only works when ATETXMODE and ATECHANNEL
were set to MODE_CCK and 14 respectively before ATETXBW is set to 0.
*/
/*
Please don't move this block backward.
BBP_R4 should be overwritten for every chip if the condition matched.
*/
#endif /* RELEASE_EXCLUDE */
if (pATEInfo->Channel == 14)
{
INT TxMode = pATEInfo->TxWI.TXWI_O.PHYMODE;
if (TxMode == MODE_CCK)
{
/* when Channel==14 && Mode==CCK && BandWidth==20M, BBP R4 bit5=1 */
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value);
value |= 0x20; /* set bit5=1 */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value);
}
}
}
/* If bandwidth = 40M, set RF Reg4 bit 21 = 0. */
else if (pATEInfo->TxWI.TXWI_O.BW == BW_40)
{
if (pATEInfo->Channel <= 14)
{
/* BW=40;G band */
for (powerIndex=0; powerIndex<MAX_TXPOWER_ARRAY_SIZE; powerIndex++)
{
if (pAd->Tx40MPwrCfgGBand[powerIndex] == 0xffffffff)
continue;
/* TX_PWR_CFG_0 ~ TX_PWR_CFG_4 */
RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + powerIndex*4, pAd->Tx40MPwrCfgGBand[powerIndex]);
RtmpOsMsDelay(5);
}
}
else
{
/* BW=40;A band */
for (powerIndex=0; powerIndex<MAX_TXPOWER_ARRAY_SIZE; powerIndex++)
{
if (pAd->Tx40MPwrCfgABand[powerIndex] == 0xffffffff)
continue;
/* TX_PWR_CFG_0 ~ TX_PWR_CFG_4 */
RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + powerIndex*4, pAd->Tx40MPwrCfgABand[powerIndex]);
RtmpOsMsDelay(5);
}
if ((pATEInfo->TxWI.TXWI_O.PHYMODE >= 2) && (pATEInfo->TxWI.TXWI_O.MCS == 7))
{
value = 0x28;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R67, value);
}
}
/* Set BBP R4 bit[4:3]=1:0 */
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value);
value &= (~0x18);
value |= 0x10;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value);
/* Set BBP R66=0x3C */
value = 0x3C;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, value);
/* set BW = 40 MHz */
pAd->LatchRfRegs.R4 |= 0x00200000;
RtmpRfIoWrite(pAd);
/* BW = 40 MHz */
/* Set BBP R68=0x0C to improve Rx sensitivity. */
value = 0x0C;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R68, value);
/* Set BBP R69=0x1A */
value = 0x1A;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, value);
/* Set BBP R70=0x0A */
value = 0x0A;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, value);
/* Set BBP R73=0x16 */
value = 0x16;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, value);
}
return TRUE;
}
/*
==========================================================================
Description:
AsicSwitchChannel() dedicated for RT28xx ATE.
==========================================================================
*/
VOID RT28xxATEAsicSwitchChannel(
IN PRTMP_ADAPTER pAd)
{
PATE_INFO pATEInfo = &(pAd->ate);
UINT32 Value = 0;
CHAR TxPwer = 0, TxPwer2 = 0;
UCHAR index = 0, BbpValue = 0, Channel = 0;
UINT32 R2 = 0, R3 = DEFAULT_RF_TX_POWER, R4 = 0;
RTMP_RF_REGS *RFRegTable = NULL;
SYNC_CHANNEL_WITH_QA(pATEInfo, &Channel);
/* fill Tx power value */
TxPwer = pATEInfo->TxPower0;
TxPwer2 = pATEInfo->TxPower1;
RFRegTable = RF2850RegTable;
switch (pAd->RfIcType)
{
/* But only 2850 and 2750 support 5.5GHz band... */
case RFIC_2820:
case RFIC_2850:
case RFIC_2720:
case RFIC_2750:
for (index = 0; index < NUM_OF_2850_CHNL; index++)
{
if (Channel == RFRegTable[index].Channel)
{
R2 = RFRegTable[index].R2;
/* If TX path is 1, bit 14 = 1. */
if (pAd->Antenna.field.TxPath == 1)
{
R2 |= 0x4000;
}
if (pAd->Antenna.field.TxPath == 2)
{
if (pATEInfo->TxAntennaSel == 1)
{
/* If TX Antenna select is 1 , bit 14 = 1; Disable Ant 2 */
R2 |= 0x4000;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpValue);
BbpValue &= 0xE7; /* 11100111B */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpValue);
}
else if (pATEInfo->TxAntennaSel == 2)
{
/* If TX Antenna select is 2 , bit 15 = 1; Disable Ant 1 */
R2 |= 0x8000;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpValue);
BbpValue &= 0xE7;
BbpValue |= 0x08;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpValue);
}
else
{
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpValue);
BbpValue &= 0xE7;
BbpValue |= 0x10;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpValue);
}
}
if (pAd->Antenna.field.RxPath == 2)
{
switch (pATEInfo->RxAntennaSel)
{
case 1:
R2 |= 0x20040;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
BbpValue |= 0x00;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
case 2:
R2 |= 0x10040;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
BbpValue |= 0x01;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
default:
R2 |= 0x40;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
/* Only enable two Antenna to receive. */
BbpValue |= 0x08;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
}
}
else if (pAd->Antenna.field.RxPath == 1)
{
/* write 1 to off RxPath */
R2 |= 0x20040;
}
if (pAd->Antenna.field.RxPath == 3)
{
switch (pATEInfo->RxAntennaSel)
{
case 1:
R2 |= 0x20040;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
BbpValue |= 0x00;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
case 2:
R2 |= 0x10040;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
BbpValue |= 0x01;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
case 3:
R2 |= 0x30000;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
BbpValue |= 0x02;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
default:
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
BbpValue |= 0x10;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
}
}
if (Channel > 14)
{
/* initialize R3, R4 */
R3 = (RFRegTable[index].R3 & 0xffffc1ff);
R4 = (RFRegTable[index].R4 & (~0x001f87c0)) | (pATEInfo->RFFreqOffset << 15);
/*
According the Rory's suggestion to solve the middle range issue.
5.5G band power range : 0xF9~0X0F, TX0 Reg3 bit9/TX1 Reg4 bit6="0"
means the TX power reduce 7dB.
*/
/* R3 */
if ((TxPwer >= -7) && (TxPwer < 0))
{
TxPwer = (7+TxPwer);
R3 |= (TxPwer << 10);
DBGPRINT(RT_DEBUG_TRACE, ("ATEAsicSwitchChannel: TxPwer=%d \n", TxPwer));
}
else
{
TxPwer = (TxPwer > 0xF) ? (0xF) : (TxPwer);
R3 |= (TxPwer << 10) | (1 << 9);
}
/* R4 */
if ((TxPwer2 >= -7) && (TxPwer2 < 0))
{
TxPwer2 = (7+TxPwer2);
R4 |= (TxPwer2 << 7);
DBGPRINT(RT_DEBUG_TRACE, ("ATEAsicSwitchChannel: TxPwer2=%d \n", TxPwer2));
}
else
{
TxPwer2 = (TxPwer2 > 0xF) ? (0xF) : (TxPwer2);
R4 |= (TxPwer2 << 7) | (1 << 6);
}
}
else
{
/* Set TX power0. */
R3 = (RFRegTable[index].R3 & 0xffffc1ff) | (TxPwer << 9);
/* Set frequency offset and TX power1. */
R4 = (RFRegTable[index].R4 & (~0x001f87c0)) | (pATEInfo->RFFreqOffset << 15) | (TxPwer2 <<6);
}
/* based on BBP current mode before changing RF channel */
if (pATEInfo->TxWI.BW == BW_40)
{
R4 |=0x200000;
}
/* Update variables. */
pAd->LatchRfRegs.Channel = Channel;
pAd->hw_cfg.lan_gain = GET_LNA_GAIN(pAd);
pAd->LatchRfRegs.R1 = RFRegTable[index].R1;
pAd->LatchRfRegs.R2 = R2;
pAd->LatchRfRegs.R3 = R3;
pAd->LatchRfRegs.R4 = R4;
RtmpRfIoWrite(pAd);
break;
}
}
break;
default:
break;
}
/* Change BBP setting during switch from a->g, g->a */
if (Channel <= 14)
{
UINT32 TxPinCfg = 0x00050F0A;/* 2007.10.09 by Brian : 0x0005050A ==> 0x00050F0A */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - pAd->hw_cfg.lan_gain));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - pAd->hw_cfg.lan_gain));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - pAd->hw_cfg.lan_gain));
/* According the Rory's suggestion to solve the middle range issue. */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);
/* Rx High power VGA offset for LNA select */
if (pAd->NicConfig2.field.ExternalLNAForG)
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
/* 2.4 G band selection PIN */
rtmp_mac_set_band(pAd, BAND_24G);
/* Turn off unused PA or LNA when only 1T or 1R. */
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
/* calibration power unbalance issues */
if (pAd->Antenna.field.TxPath == 2)
{
if (pATEInfo->TxAntennaSel == 1)
{
TxPinCfg &= 0xFFFFFFF7;
}
else if (pATEInfo->TxAntennaSel == 2)
{
TxPinCfg &= 0xFFFFFFFD;
}
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
/* channel > 14 */
else
{
UINT32 TxPinCfg = 0x00050F05;/* 2007.10.09 by Brian : 0x00050505 ==> 0x00050F05 */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - pAd->hw_cfg.lan_gain));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - pAd->hw_cfg.lan_gain));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - pAd->hw_cfg.lan_gain));
/* According the Rory's suggestion to solve the middle range issue. */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0xF2);
/* Rx High power VGA offset for LNA select */
if (pAd->NicConfig2.field.ExternalLNAForA)
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R91, &BbpValue);
ASSERT((BbpValue == 0x04));
/* 5 G band selection PIN, bit1 and bit2 are complement */
rtmp_mac_set_band(pAd, BAND_5G);
/* Turn off unused PA or LNA when only 1T or 1R. */
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
ATE_CHIP_RX_VGA_GAIN_INIT(pAd);
#ifdef RELEASE_EXCLUDE
/*
On 11A, We should delay and wait RF/BBP to be stable
and the appropriate time should be 1000 micro seconds.
2005/06/05 - On 11G, We also need this delay time.
Otherwise it's difficult to pass the WHQL.
*/
#endif /* RELEASE_EXCLUDE */
RtmpOsMsDelay(1);
#ifndef RTMP_RF_RW_SUPPORT
if (Channel > 14)
{
/* When 5.5GHz band the LSB of TxPwr will be used to reduced 7dB or not. */
DBGPRINT(RT_DEBUG_TRACE, ("RT28xx:SwitchChannel#%d(RF=%d, %dT) to , R1=0x%08x, R2=0x%08x, R3=0x%08x, R4=0x%08x\n",
Channel,
pAd->RfIcType,
pAd->Antenna.field.TxPath,
pAd->LatchRfRegs.R1,
pAd->LatchRfRegs.R2,
pAd->LatchRfRegs.R3,
pAd->LatchRfRegs.R4));
}
else
{
DBGPRINT(RT_DEBUG_TRACE, ("RT28xx:SwitchChannel#%d(RF=%d, Pwr0=%u, Pwr1=%u, %dT) to , R1=0x%08x, R2=0x%08x, R3=0x%08x, R4=0x%08x\n",
Channel,
pAd->RfIcType,
(R3 & 0x00003e00) >> 9,
(R4 & 0x000007c0) >> 6,
pAd->Antenna.field.TxPath,
pAd->LatchRfRegs.R1,
pAd->LatchRfRegs.R2,
pAd->LatchRfRegs.R3,
pAd->LatchRfRegs.R4));
}
#endif /* !RTMP_RF_RW_SUPPORT */
}
int rt28xx_close(IN PNET_DEV dev)
{
struct net_device * net_dev = (struct net_device *)dev;
RTMP_ADAPTER *pAd = NULL;
UINT32 i = 0;
BOOLEAN Cancelled;
GET_PAD_FROM_NET_DEV(pAd, net_dev);
DBGPRINT(RT_DEBUG_TRACE, ("===> rt28xx_close\n"));
#ifdef CONFIG_AP_SUPPORT
#ifdef BG_FT_SUPPORT
BG_FTPH_Remove();
#endif // BG_FT_SUPPORT //
#endif // CONFIG_AP_SUPPORT //
Cancelled = FALSE;
// Sanity check for pAd
if (pAd == NULL)
return 0; // close ok
#ifdef WMM_ACM_SUPPORT
/* must call first */
ACMP_Release(pAd);
#endif // WMM_ACM_SUPPORT //
#ifdef RTMP_RBUS_SUPPORT
#ifdef RT3XXX_ANTENNA_DIVERSITY_SUPPORT
RT3XXX_AntDiversity_Fini(pAd);
#endif // RT3XXX_ANTENNA_DIVERSITY_SUPPORT //
#endif // RTMP_RBUS_SUPPORT //
#ifdef WDS_SUPPORT
WdsDown(pAd);
#endif // WDS_SUPPORT //
#ifdef CONFIG_STA_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
{
#ifdef PCIE_PS_SUPPORT
RTMPPCIeLinkCtrlValueRestore(pAd, RESTORE_CLOSE);
#endif // PCIE_PS_SUPPORT //
// If dirver doesn't wake up firmware here,
// NICLoadFirmware will hang forever when interface is up again.
if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE))
{
AsicForceWakeup(pAd, TRUE);
}
//MlmeRadioOff(pAd);
#ifdef RTMP_MAC_PCI
pAd->bPCIclkOff = FALSE;
#endif // RTMP_MAC_PCI //
}
#endif // CONFIG_STA_SUPPORT //
RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS);
RtmpOsMsDelay(20); /* wait for disconnect requests transmitted */
for (i = 0 ; i < NUM_OF_TX_RING; i++)
{
while (pAd->DeQueueRunning[i] == TRUE)
{
DBGPRINT(RT_DEBUG_TRACE, ("Waiting for TxQueue[%d] done..........\n", i));
RTMPusecDelay(1000);
}
}
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
#ifdef DOT11N_DRAFT3
if (pAd->CommonCfg.Bss2040CoexistFlag & BSS_2040_COEXIST_TIMER_FIRED)
{
RTMPCancelTimer(&pAd->CommonCfg.Bss2040CoexistTimer, &Cancelled);
pAd->CommonCfg.Bss2040CoexistFlag = 0;
}
#endif // DOT11N_DRAFT3 //
// PeriodicTimer already been canceled by MlmeHalt() API.
//RTMPCancelTimer(&pAd->PeriodicTimer, &Cancelled);
}
#endif // CONFIG_AP_SUPPORT //
// Stop Mlme state machine
MlmeHalt(pAd);
// Close net tasklets
RtmpNetTaskExit(pAd);
#ifdef CONFIG_STA_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
{
MacTableReset(pAd);
#ifdef MAT_SUPPORT
MATEngineExit(pAd);
#endif // MAT_SUPPORT //
#ifdef LED_CONTROL_SUPPORT
RTMPSetLED(pAd, LED_LINK_DOWN);
#endif // LED_CONTROL_SUPPORT //
MlmeRadioOff(pAd);
}
#endif // CONFIG_STA_SUPPORT //
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
#ifdef MAT_SUPPORT
MATEngineExit(pAd);
#endif // MAT_SUPPORT //
#ifdef CLIENT_WDS
CliWds_ProxyTabDestory(pAd);
#endif // CLIENT_WDS //
// Shutdown Access Point function, release all related resources
APShutdown(pAd);
// Free BssTab & ChannelInfo tabbles.
AutoChBssTableDestroy(pAd);
ChannelInfoDestroy(pAd);
}
#endif // CONFIG_AP_SUPPORT //
MeasureReqTabExit(pAd);
TpcReqTabExit(pAd);
#ifdef WSC_INCLUDED
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
{
INT ap_idx;
for (ap_idx = 0; ap_idx < pAd->ApCfg.BssidNum; ap_idx++)
WscStop(pAd, FALSE, &pAd->ApCfg.MBSSID[ap_idx].WscControl);
#ifdef APCLI_SUPPORT
WscStop(pAd, TRUE, &pAd->ApCfg.ApCliTab[BSS0].WscControl);
#endif // APCLI_SUPPORT //
}
#endif // CONFIG_AP_SUPPORT //
#ifdef CONFIG_STA_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
WscStop(pAd,
#ifdef CONFIG_AP_SUPPORT
FALSE,
#endif // CONFIG_AP_SUPPORT //
&pAd->StaCfg.WscControl);
#endif // CONFIG_STA_SUPPORT //
#ifdef OLD_DH_KEY
#ifdef CONFIG_AP_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_AP(pAd)
WSC_VFREE_KEY_MEM(pAd->ApCfg.MBSSID[0].WscControl.pPubKeyMem, pAd->ApCfg.MBSSID[0].WscControl.pSecKeyMem);
#endif // CONFIG_AP_SUPPORT //
#ifdef CONFIG_STA_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
WSC_VFREE_KEY_MEM(pAd->StaCfg.WscControl.pPubKeyMem, pAd->StaCfg.WscControl.pSecKeyMem);
#endif // CONFIG_STA_SUPPORT //
#endif // OLD_DH_KEY //
/* WSC hardware push button function 0811 */
WSC_HDR_BTN_Stop(pAd);
#endif // WSC_INCLUDED //
// Close kernel threads
RtmpMgmtTaskExit(pAd);
#ifdef RTMP_MAC_PCI
{
#ifdef RTMP_PCI_SUPPORT
BOOLEAN brc;
#endif
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE))
{
RTMP_ASIC_INTERRUPT_DISABLE(pAd);
}
// Receive packets to clear DMA index after disable interrupt.
//RTMPHandleRxDoneInterrupt(pAd);
// put to radio off to save power when driver unload. After radiooff, can't write /read register. So need to finish all
// register access before Radio off.
#ifdef RTMP_PCI_SUPPORT
brc=RT28xxPciAsicRadioOff(pAd, RTMP_HALT, 0);
//In solution 3 of 3090F, the bPCIclkOff will be set to TRUE after calling RT28xxPciAsicRadioOff
#ifdef PCIE_PS_SUPPORT
pAd->bPCIclkOff = FALSE;
#endif // PCIE_PS_SUPPORT //
if (brc==FALSE)
{
DBGPRINT(RT_DEBUG_ERROR,("%s call RT28xxPciAsicRadioOff fail !!\n", __FUNCTION__));
}
#endif // RTMP_PCI_SUPPORT //
}
/*
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE))
{
RTMP_ASIC_INTERRUPT_DISABLE(pAd);
}
// Disable Rx, register value supposed will remain after reset
NICIssueReset(pAd);
*/
#endif // RTMP_MAC_PCI //
// Free IRQ
if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE))
{
#ifdef RTMP_MAC_PCI
// Deregister interrupt function
RtmpOSIRQRelease(net_dev);
#endif // RTMP_MAC_PCI //
RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE);
}
#ifdef RESOURCE_PRE_ALLOC
RTMPResetTxRxRingMemory(pAd);
#else
// Free Ring or USB buffers
RTMPFreeTxRxRingMemory(pAd);
#endif // RESOURCE_PRE_ALLOC //
RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS);
#ifdef DOT11_N_SUPPORT
// Free BA reorder resource
ba_reordering_resource_release(pAd);
#endif // DOT11_N_SUPPORT //
#ifdef CONFIG_STA_SUPPORT
#endif // CONFIG_STA_SUPPORT //
RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_START_UP);
/*+++Modify by woody to solve the bulk fail+++*/
#ifdef CONFIG_STA_SUPPORT
IF_DEV_CONFIG_OPMODE_ON_STA(pAd)
{
#ifdef DOT11Z_TDLS_SUPPORT
TDLS_Table_Destory(pAd);
#endif // DOT11Z_TDLS_SUPPORT //
}
#endif // CONFIG_STA_SUPPORT //
#ifdef VENDOR_FEATURE2_SUPPORT
printk("Number of Packet Allocated = %d\n", pAd->NumOfPktAlloc);
printk("Number of Packet Freed = %d\n", pAd->NumOfPktFree);
#endif // VENDOR_FEATURE2_SUPPORT //
DBGPRINT(RT_DEBUG_TRACE, ("<=== rt28xx_close\n"));
return 0; // close ok
} /* End of rt28xx_close */
/*
========================================================================
Routine Description: Write RT30xx RF register through MAC
Arguments:
Return Value:
IRQL =
Note:
========================================================================
*/
NDIS_STATUS RT30xxWriteRFRegister(
IN PRTMP_ADAPTER pAd,
IN UCHAR regID,
IN UCHAR value)
{
RF_CSR_CFG_STRUC rfcsr = { { 0 } };
UINT i = 0;
#ifdef RTMP_MAC_PCI
if ((pAd->bPCIclkOff == TRUE) || (pAd->LastMCUCmd == SLEEP_MCU_CMD))
{
DBGPRINT_ERR(("RT30xxWriteRFRegister. Not allow to write RF 0x%x : fail\n", regID));
return STATUS_UNSUCCESSFUL;
}
#endif /* RTMP_MAC_PCI */
{
ASSERT((regID <= pAd->chipCap.MaxNumOfRfId)); /* R0~R31 or R63*/
do
{
RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word);
if (!rfcsr.field.RF_CSR_KICK)
break;
i++;
}
while ((i < RETRY_LIMIT) && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)));
if ((i == RETRY_LIMIT) || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)))
{
DBGPRINT_RAW(RT_DEBUG_ERROR, ("Retry count exhausted or device removed!!!\n"));
return STATUS_UNSUCCESSFUL;
}
if ((pAd->chipCap.RfReg17WtMethod == RF_REG_WT_METHOD_STEP_ON) &&
(regID == RF_R17))
{
UCHAR IdRf;
UCHAR RfValue;
RT30xxReadRFRegister(pAd, RF_R17, &RfValue);
rfcsr.field.RF_CSR_WR = 1;
rfcsr.field.RF_CSR_KICK = 1;
rfcsr.field.TESTCSR_RFACC_REGNUM = regID; /* R0~R31*/
if (RfValue <= value)
{
for(IdRf=RfValue; IdRf<=value; IdRf++)
{
rfcsr.field.RF_CSR_DATA = IdRf;
RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
RtmpOsMsDelay(1);
}
}
else
{
for(IdRf=RfValue; IdRf>value; IdRf--)
{
rfcsr.field.RF_CSR_DATA = IdRf;
RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
RtmpOsMsDelay(1);
}
rfcsr.field.RF_CSR_DATA = value;
RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
}
}
else
{
rfcsr.field.RF_CSR_WR = 1;
rfcsr.field.RF_CSR_KICK = 1;
rfcsr.field.TESTCSR_RFACC_REGNUM = regID; /* R0~R31*/
rfcsr.field.RF_CSR_DATA = value;
RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
}
}
return NDIS_STATUS_SUCCESS;
}
/*
==========================================================================
Description:
Set RT28xx/RT2880 ATE RF BW
Return:
TRUE if all parameters are OK, FALSE otherwise
==========================================================================
*/
int RT28xx_Set_ATE_TX_BW_Proc(
IN PRTMP_ADAPTER pAd,
IN PSTRING arg)
{
PATE_INFO pATEInfo = &(pAd->ate);
int powerIndex;
UCHAR value = 0;
UCHAR BBPCurrentBW;
BBPCurrentBW = simple_strtol(arg, 0, 10);
if (BBPCurrentBW == 0)
{
pATEInfo->TxWI.BW = BW_20;
}
else
{
pATEInfo->TxWI.BW = BW_40;
}
if ((pATEInfo->TxWI.PHYMODE == MODE_CCK) && (pATEInfo->TxWI.BW == BW_40))
{
DBGPRINT_ERR(("Set_ATE_TX_BW_Proc!! Warning!! CCK only supports 20MHZ!!\n"));
DBGPRINT_ERR(("Bandwidth switch to 20!!\n"));
pATEInfo->TxWI.BW = BW_20;
}
if (pATEInfo->TxWI.BW == BW_20)
{
if (pATEInfo->Channel <= 14)
{
/* BW=20;G band */
for (powerIndex=0; powerIndex<MAX_TXPOWER_ARRAY_SIZE; powerIndex++)
{
if (pAd->Tx20MPwrCfgGBand[powerIndex] == 0xffffffff)
continue;
/* TX_PWR_CFG_0 ~ TX_PWR_CFG_4 */
RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + powerIndex*4, pAd->Tx20MPwrCfgGBand[powerIndex]);
RtmpOsMsDelay(5);
}
}
else
{
/* BW=20;A band */
for (powerIndex=0; powerIndex<MAX_TXPOWER_ARRAY_SIZE; powerIndex++)
{
if (pAd->Tx20MPwrCfgABand[powerIndex] == 0xffffffff)
continue;
/* TX_PWR_CFG_0 ~ TX_PWR_CFG_4 */
RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + powerIndex*4, pAd->Tx20MPwrCfgABand[powerIndex]);
RtmpOsMsDelay(5);
}
}
/* set BW = 20 MHz */
/* Set BBP R4 bit[4:3]=0:0 */
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value);
value &= (~0x18);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value);
/* Set BBP R66=0x3C */
value = 0x3C;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, value);
/* set BW = 20 MHz */
pAd->LatchRfRegs.R4 &= ~0x00200000;
RtmpRfIoWrite(pAd);
/* BW = 20 MHz */
/* Set BBP R68=0x0B to improve Rx sensitivity. */
value = 0x0B;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R68, value);
/* Set BBP R69=0x16 */
value = 0x16;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, value);
/* Set BBP R70=0x08 */
value = 0x08;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, value);
/* Set BBP R73=0x11 */
value = 0x11;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, value);
if (pATEInfo->Channel == 14)
{
int TxMode = pATEInfo->TxWI.PHYMODE;
if (TxMode == MODE_CCK)
{
/* when Channel==14 && Mode==CCK && BandWidth==20M, BBP R4 bit5=1 */
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value);
value |= 0x20; /* set bit5=1 */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value);
}
}
}
/* If bandwidth = 40M, set RF Reg4 bit 21 = 0. */
else if (pATEInfo->TxWI.BW == BW_40)
{
if (pATEInfo->Channel <= 14)
{
/* BW=40;G band */
for (powerIndex=0; powerIndex<MAX_TXPOWER_ARRAY_SIZE; powerIndex++)
{
if (pAd->Tx40MPwrCfgGBand[powerIndex] == 0xffffffff)
continue;
/* TX_PWR_CFG_0 ~ TX_PWR_CFG_4 */
RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + powerIndex*4, pAd->Tx40MPwrCfgGBand[powerIndex]);
RtmpOsMsDelay(5);
}
}
else
{
/* BW=40;A band */
for (powerIndex=0; powerIndex<MAX_TXPOWER_ARRAY_SIZE; powerIndex++)
{
if (pAd->Tx40MPwrCfgABand[powerIndex] == 0xffffffff)
continue;
/* TX_PWR_CFG_0 ~ TX_PWR_CFG_4 */
RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + powerIndex*4, pAd->Tx40MPwrCfgABand[powerIndex]);
RtmpOsMsDelay(5);
}
if ((pATEInfo->TxWI.PHYMODE >= 2) && (pATEInfo->TxWI.MCS == 7))
{
value = 0x28;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R67, value);
}
}
/* Set BBP R4 bit[4:3]=1:0 */
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value);
value &= (~0x18);
value |= 0x10;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value);
/* Set BBP R66=0x3C */
value = 0x3C;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, value);
/* set BW = 40 MHz */
pAd->LatchRfRegs.R4 |= 0x00200000;
RtmpRfIoWrite(pAd);
/* BW = 40 MHz */
/* Set BBP R68=0x0C to improve Rx sensitivity. */
value = 0x0C;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R68, value);
/* Set BBP R69=0x1A */
value = 0x1A;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, value);
/* Set BBP R70=0x0A */
value = 0x0A;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, value);
/* Set BBP R73=0x16 */
value = 0x16;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, value);
}
return TRUE;
}
/*
========================================================================
Routine Description: Write RF register through MAC
Arguments:
Return Value:
IRQL =
Note:
========================================================================
*/
NDIS_STATUS RT30xxWriteRFRegister(RTMP_ADAPTER *pAd, UCHAR regID, UCHAR value)
{
RF_CSR_CFG_STRUC rfcsr = { { 0 } };
UINT i = 0;
NDIS_STATUS ret;
#ifdef RTMP_MAC_PCI
if ((pAd->bPCIclkOff == TRUE) || (pAd->LastMCUCmd == SLEEP_MCU_CMD))
{
DBGPRINT_ERR(("RT30xxWriteRFRegister. Not allow to write RF 0x%x : fail\n", regID));
return STATUS_UNSUCCESSFUL;
}
#endif /* RTMP_MAC_PCI */
ASSERT((regID <= pAd->chipCap.MaxNumOfRfId));
ret = STATUS_UNSUCCESSFUL;
do
{
RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word);
if (!rfcsr.non_bank.RF_CSR_KICK)
break;
i++;
}
while ((i < MAX_BUSY_COUNT) && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)));
if ((i == MAX_BUSY_COUNT) || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)))
{
DBGPRINT_RAW(RT_DEBUG_ERROR, ("%s():RF Write failed(RetryCnt=%d, DevNotExistFlag=%d)\n",
__FUNCTION__, i, RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)));
goto done;
}
rfcsr.non_bank.RF_CSR_WR = 1;
rfcsr.non_bank.RF_CSR_KICK = 1;
rfcsr.non_bank.TESTCSR_RFACC_REGNUM = regID;
if ((pAd->chipCap.RfReg17WtMethod == RF_REG_WT_METHOD_STEP_ON) && (regID == RF_R17))
{
UCHAR IdRf;
UCHAR RfValue;
BOOLEAN beAdd;
RT30xxReadRFRegister(pAd, RF_R17, &RfValue);
beAdd = (RfValue < value) ? TRUE : FALSE;
IdRf = RfValue;
while(IdRf != value)
{
if (beAdd)
IdRf++;
else
IdRf--;
rfcsr.non_bank.RF_CSR_DATA = IdRf;
RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
RtmpOsMsDelay(1);
}
}
rfcsr.non_bank.RF_CSR_DATA = value;
RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
ret = NDIS_STATUS_SUCCESS;
done:
return ret;
}
VOID RT30xxATEAsicSwitchChannel(
IN PRTMP_ADAPTER pAd)
{
CHAR TxPwer = 0, TxPwer2 = 0;
UCHAR index = 0, Channel = 0;
UINT32 Value = 0;
#ifdef A_BAND_SUPPORT
UCHAR BbpValue = 0;
#endif /* A_BAND_SUPPORT */
#ifdef RTMP_RF_RW_SUPPORT
/* Added to prevent RF register reading error */
UCHAR RFValue = 0;
#endif /* RTMP_RF_RW_SUPPORT */
#ifdef RALINK_QA
/* For QA mode, TX power values are passed from UI */
if ((pAd->ate.bQATxStart == TRUE) || (pAd->ate.bQARxStart == TRUE))
{
if (pAd->ate.Channel != pAd->LatchRfRegs.Channel)
{
pAd->ate.Channel = pAd->LatchRfRegs.Channel;
}
return;
}
else
#endif /* RALINK_QA */
Channel = pAd->ate.Channel;
/* Fill Tx power value */
TxPwer = pAd->ate.TxPower0;
TxPwer2 = pAd->ate.TxPower1;
/*
The RF programming sequence is difference between 3xxx and 2xxx.
The 3070 is 1T1R. Therefore, we don't need to set the number of Tx/Rx path
and the only job is to set the parameters of channels.
*/
if ((IS_RT30xx(pAd)) &&
((pAd->RfIcType == RFIC_3020) || (pAd->RfIcType == RFIC_2020) ||
(pAd->RfIcType == RFIC_3021) || (pAd->RfIcType == RFIC_3022) || (pAd->RfIcType == RFIC_3320)))
{
for (index = 0; index < NUM_OF_3020_CHNL; index++)
{
if (Channel == FreqItems3020[index].Channel)
{
/* Programming channel parameters. */
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R02, FreqItems3020[index].N);
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R03, (PUCHAR)&RFValue);
RFValue = (RFValue & 0xF0) | (FreqItems3020[index].K&(~0xF0));
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R03, (UCHAR)RFValue);
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R06, (PUCHAR)&RFValue);
RFValue = (RFValue & 0xFC) | FreqItems3020[index].R;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R06, (UCHAR)RFValue);
/* Set Tx Power. */
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R12, (PUCHAR)&RFValue);
RFValue = (RFValue & 0xE0) | TxPwer;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R12, (UCHAR)RFValue);
/* Set RF offset. */
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R23, (PUCHAR)&RFValue);
RFValue = (RFValue & 0x80) | pAd->ate.RFFreqOffset;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R23, (UCHAR)RFValue);
/* Set BW. */
if (pAd->ate.TxWI.BW == BW_40)
{
RFValue = pAd->Mlme.CaliBW40RfR24;
}
else
{
RFValue = pAd->Mlme.CaliBW20RfR24;
}
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R24, (UCHAR)RFValue);
/* Enable RF tuning */
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R07, (PUCHAR)&RFValue);
RFValue = RFValue | 0x1;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R07, (UCHAR)RFValue);
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R30, (PUCHAR)&RFValue);
RFValue |= 0x80;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R30, (UCHAR)RFValue);
RTMPusecDelay(1000);
RFValue &= 0x7F;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R30, (UCHAR)RFValue);
/* Latch channel for future usage */
pAd->LatchRfRegs.Channel = Channel;
ATEAsicSetTxRxPath(pAd);
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R30, (PUCHAR)&RFValue);
RFValue |= 0x80;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R30, (UCHAR)RFValue);
RTMPusecDelay(1000);
RFValue &= 0x7F;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R30, (UCHAR)RFValue);
break;
}
}
DBGPRINT(RT_DEBUG_TRACE, ("%s::SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n",
__FUNCTION__,
Channel,
pAd->RfIcType,
TxPwer,
TxPwer2,
pAd->Antenna.field.TxPath,
FreqItems3020[index].N,
FreqItems3020[index].K,
FreqItems3020[index].R));
}
/* Change BBP setting during switch from a->g, g->a */
if (Channel <= 14)
{
UINT32 TxPinCfg = 0x00050F0A; /* 2007.10.09 by Brian : 0x0005050A ==> 0x00050F0A */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
if (IS_RT3352(pAd) || IS_RT5350(pAd))
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x38);
}
else
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);
}
/* Rx High power VGA offset for LNA select */
if (pAd->NicConfig2.field.ExternalLNAForG)
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
/* 2.4 G band selection PIN */
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x04);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* Turn off unused PA or LNA when only 1T or 1R. */
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
/* Calibration power unbalance issues */
if (pAd->Antenna.field.TxPath == 2)
{
if (pAd->ate.TxAntennaSel == 1)
{
TxPinCfg &= 0xFFFFFFF7;
}
else if (pAd->ate.TxAntennaSel == 2)
{
TxPinCfg &= 0xFFFFFFFD;
}
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
#ifdef A_BAND_SUPPORT
else
{
UINT32 TxPinCfg = 0x00050F05; /* 2007.10.09 by Brian : 0x00050505 ==> 0x00050F05 */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
/* According the Rory's suggestion to solve the middle range issue. */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0xF2);
/* Rx High power VGA offset for LNA select */
if (pAd->NicConfig2.field.ExternalLNAForA)
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R91, &BbpValue);
ASSERT((BbpValue == 0x04));
/* 5 G band selection PIN, bit1 and bit2 are complement */
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x02);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* Turn off unused PA or LNA when only 1T or 1R. */
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
#endif /* A_BAND_SUPPORT */
ATE_CHIP_RX_VGA_GAIN_INIT(pAd);
RtmpOsMsDelay(1);
#ifndef RTMP_RF_RW_SUPPORT
if (Channel <= 14)
{
DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%u, Pwr1=%u, %dT) to , R1=0x%08x, R2=0x%08x, R3=0x%08x, R4=0x%08x\n",
Channel,
pAd->RfIcType,
(pAd->LatchRfRegs.R3 & 0x00003e00) >> 9,
(pAd->LatchRfRegs.R4 & 0x000007c0) >> 6,
pAd->Antenna.field.TxPath,
pAd->LatchRfRegs.R1,
pAd->LatchRfRegs.R2,
pAd->LatchRfRegs.R3,
pAd->LatchRfRegs.R4));
}
