void board_console_init(void)
{
uint64_t syscfg;
int plldiv;
syscfg = SBREADCSR(A_SCD_SYSTEM_CFG);
cpu_revision = (unsigned int) (SBREADCSR(A_SCD_SYSTEM_REVISION) &
(M_SYS_PART | M_SYS_REVISION));
cpu_pass = G_SYS_REVISION(cpu_revision);
/* Console */
#if defined(_CSWARM_DIAG_CFG_) || defined(_CSWARM_DIAG3E_CFG_)
cfe_add_device(&promice_uart,PROMICE_BASE,PROMICE_WORDSIZE,0);
cfe_set_console("promice0");
#else
cfe_add_device(&sb1250_uart,A_DUART,0,0);
cfe_add_device(&promice_uart,PROMICE_BASE,PROMICE_WORDSIZE,0);
/*
* Read the config switch and decide how we are going to
* set up the console. The config switch sets
* bits 3..5 of the SYS_CONFIG field of the syscfg register.
*/
cfe_startflags = cswarm_startflags[(G_SYS_CONFIG(syscfg)/8) & 0x07];
if (cfe_startflags & CSWARM_PROMICE_CONSOLE) {
cfe_set_console("promice0");
}
else {
cfe_set_console("uart0");
}
#endif
/*
* Set variable that contains CPU speed, spit out config register
*/
plldiv = G_SYS_PLL_DIV(syscfg);
if (plldiv == 0) {
plldiv = 6;
}
#ifdef _FUNCSIM_
cfe_cpu_speed = 500000; /* wire func sim at 500KHz */
#else
cfe_cpu_speed = 50000000 * plldiv; /* use PLL divisor */
#endif
#if CFG_VGACONSOLE
vga_biosinit();
#endif
/*
* NVRAM (environment variables
*/
cfe_add_device(&sb1250_x1240eeprom,X1240_SMBUS_CHAN,X1240_SMBUS_DEV,0);
cfe_set_envdevice("eeprom0"); /* Connect NVRAM subsystem to EEPROM */
}
void board_device_init(void)
{
uint64_t syscfg;
int promice_boot;
/*
* Boot ROM
*/
syscfg = SBREADCSR(A_SCD_SYSTEM_CFG);
promice_boot = ptswarm_startflags[(G_SYS_CONFIG(syscfg)/8) & 0x07] & \
PTSWARM_PROMICE_BOOT;
/*
* Don't remap chip select 0 when using PromICE, since
* PromICE only emulates 2 Meg and we set ALT_BOOTROM
* to 2 Meg
*/
if (!promice_boot)
{
cs0_remap(); /* Expand CS0 -- this is bootrom and flash */
bootrom_add(BOOTROM_PHYS);
alt_bootrom_add(ALT_BOOTROM_PHYS);
}
else
{
cs1_remap(); /* Expand CS1 -- it's all flash */
alt_bootrom_add(BOOTROM_PHYS);
bootrom_add(ALT_BOOTROM_PHYS);
}
cfe_add_device(&sb1250_24lc128eeprom,BIGEEPROM_SMBUS_CHAN,BIGEEPROM_SMBUS_DEV,0);
/*
* MACs - must init after environment, since the hw address is stored there
*/
cfe_add_device(&sb1250_ether,A_MAC_BASE_0,0,env_getenv("ETH0_HWADDR"));
#ifndef _PTSWARM_DIAG_CFG_
cfe_add_device(&sb1250_ether,A_MAC_BASE_1,1,env_getenv("ETH1_HWADDR"));
cfe_add_device(&sb1250_ether,A_MAC_BASE_2,2,env_getenv("ETH2_HWADDR"));
#endif
/*
* Set variable that contains CPU speed, spit out config register
*/
syscfg = SBREADCSR(A_SCD_SYSTEM_CFG);
printf("Config switch: %d\n",G_SYS_CONFIG(syscfg));
/*
* Display CPU status
*/
sb1250_show_cpu_type();
}
void board_console_init(void)
{
uint64_t syscfg;
int plldiv;
syscfg = SBREADCSR(A_SCD_SYSTEM_CFG);
/* Console */
cfe_add_device(&promice_uart,PROMICE_BASE,PROMICE_WORDSIZE,0);
cfe_add_device(&sb1250_uart,A_DUART,0,0);
#if CFG_PCI
cfe_startflags = CFE_INIT_PCI;
#else
cfe_startflags = 0;
#endif
#ifdef _C3_DIAG_CFG_
cfe_set_console("promice0");
#else
cfe_set_console("uart0");
#endif
/* CPU Speed : read from PLL field of SYSCFG register */
plldiv = G_SYS_PLL_DIV(syscfg);
if (plldiv == 0) {
plldiv = 6;
}
#ifdef _FUNCSIM_
cfe_cpu_speed = 500000; /* wire func sim at 500KHz */
#else
cfe_cpu_speed = 50000000 * plldiv;
#endif
}
void board_device_init(void)
{
uint64_t syscfg;
/* Boot ROM */
#ifndef _C3_DIAG_CFG_
cfe_add_device(&newflashdrv,
BOOTROM_PHYS,
(BOOTROM_SIZE*K64) | FLASH_FLG_BUS8 | FLASH_FLG_DEV16,
NULL);
cfe_add_device(&newflashdrv,
ALT_BOOTROM_PHYS,
(ALT_BOOTROM_SIZE*K64) | FLASH_FLG_BUS8 | FLASH_FLG_DEV16,
NULL);
#endif
#ifdef _C3H_ /* Host Mode */
#if CFG_PCI
/*
* Add some sample PCI devices
*/
cfe_add_device(&pciidedrv,0,IDE_PROBE_MASTER_TYPE(IDE_DEVTYPE_DISK),NULL);
cfe_add_device(&dc21143drv,0,0,env_getenv("TULIP0_HWADDR"));
#if CFG_DOWNLOAD
/* Access to bcm1250 in PCI device mode */
cfe_add_device(&bcm1250drv,0,0,NULL);
#endif
#endif
#else /* Device Mode */
/*
* Host download interface.
*/
cfe_add_device(&sb1250_pcihost,0,0,NULL);
#endif /* _C3H_ */
syscfg = SBREADCSR(A_SCD_SYSTEM_CFG);
printf("SysCfg: %016llX [PLL_DIV: %d, IOB0_DIV: %s, IOB1_DIV: %s]\n",
syscfg,
(int)G_SYS_PLL_DIV(syscfg),
(syscfg & M_SYS_IOB0_DIV) ? "CPUCLK/3" : "CPUCLK/4",
(syscfg & M_SYS_IOB1_DIV) ? "CPUCLK/2" : "CPUCLK/3");
if (G_SYS_PLL_DIV(syscfg) == 0) {
printf("PLL_DIV of zero found, assuming 6 (300MHz)\n");
}
}
/* *********************************************************************
* temp_smbus_waitready(chan)
*
* Wait until the SMBus channel is ready. We simply poll
* the busy bit until it clears.
*
* Input parameters:
* chan - channel (0 or 1)
*
* Return value:
* nothing
********************************************************************* */
static int temp_smbus_waitready(int chan)
{
uintptr_t reg;
uint64_t status;
reg = PHYS_TO_K1(A_SMB_REGISTER(chan,R_SMB_STATUS));
for (;;) {
status = SBREADCSR(reg);
if (status & M_SMB_BUSY) continue;
break;
}
if (status & M_SMB_ERROR) {
SBWRITECSR(reg,(status & M_SMB_ERROR));
return -1;
}
return 0;
}
/*
* read from SMBus
*/
static int
bcm1250_smbus_read(int smb_chan, UINT8 slave, UINT8 *buf, int len)
{
int err;
while (len > 0) {
err = bcm1250_smbus_waitready(smb_chan);
if (err < 0) return err;
SBWRITECSR(A_SMB_REGISTER(smb_chan, R_SMB_START),
V_SMB_TT(K_SMB_TT_RD1BYTE) | ((UINT64)slave));
err = bcm1250_smbus_waitready(smb_chan);
if (err < 0) return err;
*buf++ = (UINT8) SBREADCSR(A_SMB_REGISTER(smb_chan, R_SMB_DATA));
len--;
}
return 0;
}
/*
* Wait for SMBus
*/
static int
bcm1250_smbus_waitready(int smb_chan)
{
UINT64 status = 0;
int cnt = 10000000; /* about 1 second at 1Ghz */
while (cnt > 0) {
status = SBREADCSR(A_SMB_REGISTER(smb_chan, R_SMB_STATUS));
if (status & M_SMB_BUSY) {
cnt--;
continue;
}
break;
}
if (cnt == 0) return -1;
if (status & M_SMB_ERROR) {
SBWRITECSR(A_SMB_REGISTER(smb_chan, R_SMB_STATUS), (status & M_SMB_ERROR));
return -1;
}
return 0;
}
static int temp_smbus_read(int chan,int slaveaddr,int devaddr)
{
uintptr_t reg;
int err;
/*
* Make sure the bus is idle (probably should
* ignore error here)
*/
if (temp_smbus_waitready(chan) < 0) return -1;
/*
* Write the device address to the controller. There are two
* parts, the high part goes in the "CMD" field, and the
* low part is the data field.
*/
reg = PHYS_TO_K1(A_SMB_REGISTER(chan,R_SMB_CMD));
SBWRITECSR(reg,devaddr);
/*
* Read the data byte
*/
reg = PHYS_TO_K1(A_SMB_REGISTER(chan,R_SMB_START));
SBWRITECSR(reg,V_SMB_TT(K_SMB_TT_CMD_RD1BYTE) | slaveaddr);
err = temp_smbus_waitready(chan);
if (err < 0) return err;
reg = PHYS_TO_K1(A_SMB_REGISTER(chan,R_SMB_DATA));
err = SBREADCSR(reg);
return (err & 0xFF);
}
static int ui_cmd_reset(ui_cmdline_t *cmd,int argc,char *argv[])
{
uint64_t data;
uint64_t olddata;
int confirm = 1;
char str[50];
data = SBREADCSR(A_SCD_SYSTEM_CFG) & ~M_SYS_SB_SOFTRES;
olddata = data;
if (cmd_sw_isset(cmd,"-yes")) confirm = 0;
if (cmd_sw_isset(cmd,"-softreset")) data |= M_SYS_SB_SOFTRES;
if (cmd_sw_isset(cmd,"-unicpu0")) data |= M_SYS_UNICPU0;
else if (cmd_sw_isset(cmd,"-unicpu1")) data |= M_SYS_UNICPU1;
if (cmd_sw_isset(cmd,"-sysreset")) data |= M_SYS_SYSTEM_RESET;
if (cmd_sw_isset(cmd,"-cpu")) data |= (M_SYS_CPU_RESET_0 | M_SYS_CPU_RESET_1);
if (data == olddata) { /* no changes to reset pins were specified */
return ui_showusage(cmd);
}
if (confirm) {
console_readline("Are you sure you want to reset? ",str,sizeof(str));
if ((str[0] != 'Y') && (str[0] != 'y')) return -1;
}
SBWRITECSR(A_SCD_SYSTEM_CFG,data);
/* should not return */
return -1;
}
void board_device_init(void)
{
uint64_t syscfg;
/*
* Boot ROM
*/
#if !defined(_CSWARM_DIAG_CFG_)
cfe_add_device(&newflashdrv,
BOOTROM_PHYS,
(BOOTROM_SIZE*K64) | FLASH_FLG_BUS8 | FLASH_FLG_DEV16,
NULL);
cfe_add_device(&newflashdrv,
ALT_BOOTROM_PHYS,
(ALT_BOOTROM_SIZE*K64) | FLASH_FLG_BUS8 | FLASH_FLG_DEV16,
NULL);
#endif
cfe_add_device(&sb1250_24lc128eeprom,BIGEEPROM_SMBUS_CHAN,BIGEEPROM_SMBUS_DEV,0);
/*
* MACs - must init after environment, since the hw address is stored there
*/
cfe_add_device(&sb1250_ether,A_MAC_BASE_0,0,env_getenv("ETH0_HWADDR"));
#ifndef _CSWARM_DIAG_CFG_
cfe_add_device(&sb1250_ether,A_MAC_BASE_1,1,env_getenv("ETH1_HWADDR"));
cfe_add_device(&sb1250_ether,A_MAC_BASE_2,2,env_getenv("ETH2_HWADDR"));
#endif
/*
* IDE disks and PCMCIA
*/
#if !defined(_CSWARM_DIAG_CFG_) && !defined(_CSWARM_DIAG3E_CFG_)
/*
* Uncomment to enable IDE disks
*
* cfe_add_device(&idedrv,IDE_PHYS+(0x1F0<<5),
* IDE_PROBE_MASTER_TYPE(IDE_DEVTYPE_DISK) |
* IDE_PROBE_SLAVE_TYPE(IDE_DEVTYPE_NOPROBE),
* NULL);
*/
/*
* Uncomment to enable PCMCIA support
*
* cfe_add_device(&pcmciadrv,PCMCIA_PHYS,0,NULL);
*/
#endif
#if CFG_PCI
/*
* Add some sample PCI devices
*/
if (cfe_startflags & CFE_INIT_PCI) {
cfe_add_device(&pciidedrv,0,IDE_PROBE_MASTER_TYPE(IDE_DEVTYPE_DISK),NULL);
cfe_add_device(&dc21143drv,0,0,env_getenv("TULIP0_HWADDR"));
}
#endif
/*
* Set variable that contains CPU speed, spit out config register
*/
syscfg = SBREADCSR(A_SCD_SYSTEM_CFG);
printf("Config switch: %d\n",G_SYS_CONFIG(syscfg));
#ifdef _MAGICWID_
printf("Reference Clock: %dMhz\n",(uint32_t)SB1250_REFCLK);
#endif
sb1250_show_cpu_type();
}
void board_console_init(void)
{
uint64_t syscfg;
unsigned temp;
int plldiv;
syscfg = SBREADCSR(A_SCD_SYSTEM_CFG);
/*
* External UART is device "uart0". On the PTSWARM it's the connector
* nearest the motherboard.
*/
cfe_add_device(&ns16550_uart,UART_PHYS,0,0);
/* Internal UART0 is device "uart1" */
cfe_add_device(&sb1250_uart,A_DUART,0,0);
/* Add the PromICE UART, device "promice0", for good measure */
cfe_add_device(&promice_uart,PROMICE_BASE,PROMICE_WORDSIZE,0);
/*
* Get the CFE startflags from the upper 3 bits of the "config" field
* in the sysconfig register. Only 3 bits are used, because that's
* what the CSWARM does.
*/
cfe_startflags = ptswarm_startflags[(G_SYS_CONFIG(syscfg)/8) & 0x07];
if (cfe_startflags & PTSWARM_PROMICE_CONSOLE) {
cfe_set_console("promice0");
}
else if (cfe_startflags & PTSWARM_INTERNAL_UART_CONSOLE) {
cfe_set_console("uart1");
}
else {
cfe_set_console("uart0");
}
/*
* Set variable that contains CPU speed, spit out config register
*/
plldiv = G_SYS_PLL_DIV(syscfg);
cfe_cpu_speed = 50000000 * plldiv;
/*
* NVRAM (environment variables
*/
cfe_add_device(&sb1250_x1240eeprom,X1240_SMBUS_CHAN,X1240_SMBUS_DEV,0);
/*
* Turn off the safe flag so the ethernet MAC addresses will get read
* from NVRAM
*/
temp = cfe_startflags;
cfe_startflags &= ~CFE_INIT_SAFE;
cfe_set_envdevice("eeprom0"); /* Connect NVRAM subsystem to EEPROM */
/* restore SAFE flag if it was set */
cfe_startflags = temp;
}
