static void hisi_pmic_otmp_wk_handler(struct work_struct *work)
{
struct irq_desc *desc = NULL;
PMIC_MNTN_DESC *pmic_mntn;
pmic_mntn = container_of(work, PMIC_MNTN_DESC, otmp_wk);
unsigned char reg_value = 0;
memset((void *)pmic_mntn->irq_log_show, '\0', PMIC_PRINT_BUF_SIZE);
snprintf(pmic_mntn->irq_log_show, PMIC_PRINT_BUF_SIZE, "%s", "PMIC OTMP EVENT HAPPEN.\n");
pr_info("\n%s\n", pmic_mntn->irq_log_show);
desc = irq_to_desc(pmic_mntn->otmp_irq);
if (!desc) {
pr_err("[%s]irq_to_desc err\n", __func__);
return;
}
if (NULL != desc->irq_data.chip->irq_unmask) {
desc->irq_data.chip->irq_unmask(&desc->irq_data);
}
/*hreset powerdown ctrl,if otmp_hreset_pwrdown_flag is not 0,do cold reset*/
if (0 != pmic_mntn->otmp_hreset_pwrdown_flag) {
reg_value = hisi_pmic_reg_read(pmic_mntn->otmp_hreset_pwrdown_reg.addr);
SET_REG_BIT(reg_value, pmic_mntn->otmp_hreset_pwrdown_reg.shift, pmic_mntn->otmp_hreset_pwrdown_reg.mask, pmic_mntn->otmp_hreset_pwrdown_val);
hisi_pmic_reg_write(pmic_mntn->otmp_hreset_pwrdown_reg.addr, reg_value);
}
hisi_pmic_board_reboot();
return;
}
void xge_mac_set_speed(struct xge_pdata *pdata)
{
u32 icm0, icm2, ecm0, mc2;
u32 intf_ctrl, rgmii;
icm0 = xge_rd_csr(pdata, ICM_CONFIG0_REG_0);
icm2 = xge_rd_csr(pdata, ICM_CONFIG2_REG_0);
ecm0 = xge_rd_csr(pdata, ECM_CONFIG0_REG_0);
rgmii = xge_rd_csr(pdata, RGMII_REG_0);
mc2 = xge_rd_csr(pdata, MAC_CONFIG_2);
intf_ctrl = xge_rd_csr(pdata, INTERFACE_CONTROL);
icm2 |= CFG_WAITASYNCRD_EN;
switch (pdata->phy_speed) {
case SPEED_10:
SET_REG_BITS(&mc2, INTF_MODE, 1);
SET_REG_BITS(&intf_ctrl, HD_MODE, 0);
SET_REG_BITS(&icm0, CFG_MACMODE, 0);
SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 500);
SET_REG_BIT(&rgmii, CFG_SPEED_125, 0);
break;
case SPEED_100:
SET_REG_BITS(&mc2, INTF_MODE, 1);
SET_REG_BITS(&intf_ctrl, HD_MODE, 1);
SET_REG_BITS(&icm0, CFG_MACMODE, 1);
SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 80);
SET_REG_BIT(&rgmii, CFG_SPEED_125, 0);
break;
default:
SET_REG_BITS(&mc2, INTF_MODE, 2);
SET_REG_BITS(&intf_ctrl, HD_MODE, 2);
SET_REG_BITS(&icm0, CFG_MACMODE, 2);
SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 16);
SET_REG_BIT(&rgmii, CFG_SPEED_125, 1);
break;
}
mc2 |= FULL_DUPLEX | CRC_EN | PAD_CRC;
SET_REG_BITS(&ecm0, CFG_WFIFOFULLTHR, 0x32);
xge_wr_csr(pdata, MAC_CONFIG_2, mc2);
xge_wr_csr(pdata, INTERFACE_CONTROL, intf_ctrl);
xge_wr_csr(pdata, RGMII_REG_0, rgmii);
xge_wr_csr(pdata, ICM_CONFIG0_REG_0, icm0);
xge_wr_csr(pdata, ICM_CONFIG2_REG_0, icm2);
xge_wr_csr(pdata, ECM_CONFIG0_REG_0, ecm0);
}
static int hisi_pmic_smpl_mntn_initial(struct platform_device *pdev, PMIC_MNTN_DESC *pmic_mntn)
{
struct device_node *root = NULL;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
unsigned char reg_value = 0;
s32 ret = 0;
root = of_find_compatible_node(np, NULL, "hisilicon,pmic-mntn-smpl");
if (!root) {
dev_err(dev, "[%s]no hisilicon,pmic-mntn-smpl root node\n", __func__);
return -ENODEV;
}
ret |= of_property_read_u32_array(root, "hisilicon,smpl-ctrl-en", &pmic_mntn->smpl_en_val, 0x1);
ret |= of_property_read_u32_array(root, "hisilicon,smpl-ctrl-en-reg", (u32 *)&pmic_mntn->smpl_en_reg, 0x3);
ret |= of_property_read_u32_array(root, "hisilicon,smpl-ctrl-time", &pmic_mntn->smpl_tm_val, 0x1);
ret |= of_property_read_u32_array(root, "hisilicon,smpl-ctrl-time-reg", (u32 *)&pmic_mntn->smpl_tm_reg, 0x3);
if (ret) {
dev_err(dev, "[%s]get pmic smpl attribute failed.\n", __func__);
return -ENODEV;
}
/*Set SMPL on/off*/
reg_value = hisi_pmic_reg_read(pmic_mntn->smpl_en_reg.addr);
SET_REG_BIT(reg_value, pmic_mntn->smpl_en_reg.shift, pmic_mntn->smpl_en_reg.mask, pmic_mntn->smpl_en_val);
hisi_pmic_reg_write(pmic_mntn->smpl_en_reg.addr, reg_value);
/*Set SMPL effective time*/
reg_value = hisi_pmic_reg_read(pmic_mntn->smpl_tm_reg.addr);
SET_REG_BIT(reg_value, pmic_mntn->smpl_tm_reg.shift, pmic_mntn->smpl_tm_reg.mask, pmic_mntn->smpl_tm_val);
hisi_pmic_reg_write(pmic_mntn->smpl_tm_reg.addr, reg_value);
return 0;
}
int hisi_pmic_mntn_config_smpl(bool enable)
{
unsigned int reg_value = 0;
unsigned int value = 0;
if( !g_pmic_mntn )
return 1;
//config smpl(reg:0xDC; bit 0; 0:disable, 1: enable)
if( enable ) {
value = 1;
pr_info("%s %d enable smpl in kernel\n", __func__, __LINE__);
} else {
value = 0;
pr_info("%s %d disable smpl in kernel\n", __func__, __LINE__);
}
reg_value = hisi_pmic_reg_read(g_pmic_mntn->smpl_en_reg.addr);
SET_REG_BIT(reg_value, g_pmic_mntn->smpl_en_reg.shift, g_pmic_mntn->smpl_en_reg.mask, value);
hisi_pmic_reg_write(g_pmic_mntn->smpl_en_reg.addr, reg_value);
return 0;
}
int hisi_pmic_mntn_config_vsys_pwroff_abs_pd(bool enable)
{
unsigned int reg_value = 0;
unsigned int value = 0;
if( !g_pmic_mntn )
return 1;
//config abs_pd (reg:0xDB; bit 0; 0:：自动关机(低于2.3v时间超过35us以上才能保证关机成功),
//1:不自动关机)
if( enable ) {
value = g_pmic_mntn->vsys_pwroff_abs_pd_en_val;
pr_info("%s %d enable abs_pd in kernel\n", __func__, __LINE__);
} else {
value = g_pmic_mntn->vsys_pwroff_abs_pd_dis_val;
pr_info("%s %d disable abs_pd in kernel\n", __func__, __LINE__);
}
reg_value = hisi_pmic_reg_read(g_pmic_mntn->vsys_pwroff_abs_pd_tm_reg.addr);
SET_REG_BIT(reg_value, g_pmic_mntn->vsys_pwroff_abs_pd_tm_reg.shift, g_pmic_mntn->vsys_pwroff_abs_pd_tm_reg.mask, value);
hisi_pmic_reg_write(g_pmic_mntn->vsys_pwroff_abs_pd_tm_reg.addr, reg_value);
return 0;
}
static int hisi_pmic_otmp_mntn_initial(struct platform_device *pdev, PMIC_MNTN_DESC *pmic_mntn)
{
struct device_node *root = NULL;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
unsigned char reg_value = 0;
s32 ret = 0;
root = of_find_compatible_node(np, NULL, "hisilicon,pmic-mntn-otmp");
if (!root) {
dev_err(dev, "[%s]no hisilicon,pmic-mntn-otmp root node\n", __func__);
return -ENODEV;
}
ret |= of_property_read_u32_array(root, "hisilicon,otmp-threshold-val", (u32 *)&pmic_mntn->otmp_thshd_val, 0x1);
ret |= of_property_read_u32_array(root, "hisilicon,otmp-threshold-reg", (u32 *)&pmic_mntn->otmp_thshd_reg, 0x3);
if (ret) {
dev_err(dev, "[%s]get pmic otmp attribute failed.\n", __func__);
return -ENODEV;
}
ret |= of_property_read_u32_array(root, "hisilicon,otmp-hreset-pwrdown-flag", (u32 *)&pmic_mntn->otmp_hreset_pwrdown_flag, 0x1);
ret |= of_property_read_u32_array(root, "hisilicon,otmp-hreset-pwrdown-val", (u32 *)&pmic_mntn->otmp_hreset_pwrdown_val, 0x1);
ret |= of_property_read_u32_array(root, "hisilicon,otmp-hreset-pwrdown-reg", (u32 *)&pmic_mntn->otmp_hreset_pwrdown_reg, 0x3);
if (ret) {
dev_err(dev, "[%s]get pmic otmp attribute failed.\n", __func__);
return -ENODEV;
}
root = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
if (!root) {
dev_err("%s: hisilicon,sysctrl No compatible node found\n", __func__);
return -ENODEV;
}
g_sysctrl_base = of_iomap(root, 0);
if (!g_sysctrl_base) {
dev_err("%s: hisilicon,sysctrl_base is NULL\n", __func__);
return -ENODEV;
}
/*Set the otmp threshold*/
reg_value = hisi_pmic_reg_read(pmic_mntn->otmp_thshd_reg.addr);
SET_REG_BIT(reg_value, pmic_mntn->otmp_thshd_reg.shift, pmic_mntn->otmp_thshd_reg.mask, pmic_mntn->otmp_thshd_val);
hisi_pmic_reg_write(pmic_mntn->otmp_thshd_reg.addr, reg_value);
pmic_mntn->otmp_irq = platform_get_irq_byname(pdev, "otmp");
if (pmic_mntn->ocp_irq < 0) {
dev_err(dev, "[%s]platform_get_irq_byname otmp_irq failed.\n", __func__);
return -ENODEV;
}
pmic_mntn->otmp_wq = create_singlethread_workqueue("pmic-otmp-wq");
INIT_WORK(&pmic_mntn->otmp_wk, (void *)hisi_pmic_otmp_wk_handler);
ret = devm_request_irq(dev, pmic_mntn->otmp_irq, hisi_pmic_otmp_irq_handler, IRQF_DISABLED|IRQF_NO_SUSPEND,
"pmic-otmp-irq", (void *)pmic_mntn);
if (ret) {
dev_err(dev, "[%s] request_irq otmp_irq err\n", __func__);
return -ENODEV;
}
return 0;
}
void sab8253x_init_lineS(struct sab_port *port)
{
unsigned char stat;
if(port->chip->c_cim)
{
if(port->chip->c_cim->ci_type == CIM_SP502)
{
aura_sp502_program(port, SP502_OFF_MODE);
}
}
/*
* Wait for any commands or immediate characters
*/
sab8253x_cec_wait(port);
#if 0
sab8253x_tec_wait(port); /* I have to think about this one
* should I assume the line was
* previously in async mode*/
#endif
/*
* Clear the FIFO buffers.
*/
WRITEB(port, cmdr, SAB82532_CMDR_RHR);
sab8253x_cec_wait(port);
WRITEB(port,cmdr,SAB82532_CMDR_XRES);
/*
* Clear the interrupt registers.
*/
stat = READB(port, isr0); /* acks ints */
stat = READB(port, isr1);
/*
* Now, initialize the UART
*/
WRITEB(port, ccr0, 0); /* power-down */
WRITEB(port, ccr0, getccr0configS(port));
WRITEB(port, ccr1, getccr1configS(port));
WRITEB(port, ccr2, getccr2configS(port));
WRITEB(port, ccr3, getccr3configS(port));
WRITEB(port, ccr4, getccr4configS(port)); /* 32 byte receive fifo */
WRITEB(port, mode, getmodeS(port));
WRITEB(port, tic /* really rlcr */, getrlcrconfigS(port));
/* power-up */
switch(port->ccontrol.ccr4 & SAB82532_CCR4_RF02)
{
case SAB82532_CCR4_RF32:
port->recv_fifo_size = 32;
break;
case SAB82532_CCR4_RF16:
port->recv_fifo_size = 16;
break;
case SAB82532_CCR4_RF04:
port->recv_fifo_size = 4;
break;
case SAB82532_CCR4_RF02:
port->recv_fifo_size = 2;
break;
default:
port->recv_fifo_size = 32;
port->ccontrol.ccr4 &= ~SAB82532_CCR4_RF02;
break;
}
if(port->ccontrol.ccr2 & SAB82532_CCR2_TOE)
{
RAISE(port, txclkdir);
}
else
{
LOWER(port, txclkdir);
}
SET_REG_BIT(port,ccr0,SAB82532_CCR0_PU);
if(port->chip->c_cim)
{
if(port->chip->c_cim->ci_type == CIM_SP502)
{
aura_sp502_program(port, port->sigmode);
}
}
}
