void dump_registers(conf_object_t *cpu)
{
const char* reg_names[] = {
"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
"i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
"o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
"ccr", "pc", "npc"
};
printf("Registers for %s\n", cpu->name);
printf("------------------\n");
for (int i = 0; i < (sizeof(reg_names) / sizeof(char*)); i++) {
const char* reg_name = reg_names[i];
printf(" %3s: 0x%016llx\n", reg_name, read_reg(cpu, reg_name));
if (i % 8 == 7) {
printf("\n");
}
}
int myID = SIMICS_get_proc_no(cpu);
Address myPC = SIMICS_get_program_counter(myID);
physical_address_t myPhysPC = SIMICS_translate_address(myID, myPC);
integer_t myInst = SIMICS_read_physical_memory(myID, myPhysPC, 4);
const char *myInstStr = SIMICS_disassemble_physical(myID, myPhysPC);
printf("\n *pc: 0x%llx: %s\n", myInst, myInstStr);
printf("\n\n");
}
void TransactionSimicsProcessor::processRubyWatchAddress(memory_transaction_t *mem_trans, CacheRequestType type){
if (g_system_ptr->getProfiler()->watchAddress(Address(mem_trans->s.logical_address)))
cout << m_proc << " RUBY WATCH: EVENT " << type
<< " ADDRESS: " << Address(mem_trans->s.logical_address)
<< " VALUE: " << hex << SIMICS_read_physical_memory(m_proc, mem_trans->s.physical_address, 4)
<< dec << endl;
}
/**
* Redirects Transactional store to a write buffer. Ensures that the old value remains
* in committed memory state (SIMICS memory)
*/
void TransactionSimicsProcessor::redirectStoreToWriteBuffer(memory_transaction_t *mem_trans){
assert(XACT_LAZY_VM);
assert(mem_trans->s.size > 0 && mem_trans->s.size < 256);
physical_address_t addr = mem_trans->s.physical_address;
m_oldValueBufferSize = mem_trans->s.size;
SIM_c_get_mem_op_value_buf( &(mem_trans->s), m_newValueBuffer);
Vector<uint8> data;
data.setSize(mem_trans->s.size);
for (unsigned int i = 0; i < mem_trans->s.size; i++)
data[i] = (uint8)m_newValueBuffer[i];
m_xact_mgr->getXactLazyVersionManager()->addToWriteBuffer(0, m_xact_mgr->getTransactionLevel(0), Address(mem_trans->s.physical_address), mem_trans->s.size, data);
for (unsigned int i = 0; i < mem_trans->s.size; i++)
m_oldValueBuffer[i] = SIMICS_read_physical_memory(m_proc, addr + i, 1);
SIM_c_set_mem_op_value_buf( &(mem_trans->s), m_oldValueBuffer);
if (XACT_DEBUG && XACT_DEBUG_LEVEL > 2)
cout << g_eventQueue_ptr->getTime() << " " << m_proc << " [" << m_proc / RubyConfig::numberofSMTThreads() << "," << m_proc % RubyConfig::numberofSMTThreads() << "] REDIRECTING TO STORE BUFFER" << Address(mem_trans->s.physical_address) << " " << m_oldValueBufferSize << endl;
}
