/*
** ===================================================================
** Method : SPI0_Init (component Init_SPI)
** Description :
** This method initializes registers of the SPI module
** according to the Peripheral Initialization settings.
** Call this method in user code to initialize the module. By
** default, the method is called by PE automatically; see "Call
** Init method" property of the component for more details.
** Parameters : None
** Returns : Nothing
** ===================================================================
*/
void SPI0_Init(void)
{
/* SIM_SCGC: SPI0=1 */
SIM_SCGC |= SIM_SCGC_SPI0_MASK;
/* SPI0_C1: SPIE=0,SPE=0,SPTIE=0,MSTR=0,CPOL=0,CPHA=1,SSOE=0,LSBFE=0 */
SPI0_C1 = SPI_C1_CPHA_MASK;
/* SPI0_C2: SPMIE=0,MODFEN=1,BIDIROE=0,SPISWAI=0,SPC0=0 */
SPI0_C2 = (uint8_t)((SPI0_C2 & (uint8_t)~(uint8_t)(
SPI_C2_SPMIE_MASK |
SPI_C2_BIDIROE_MASK |
SPI_C2_SPISWAI_MASK |
SPI_C2_SPC0_MASK
)) | (uint8_t)(
SPI_C2_MODFEN_MASK
));
/* SPI0_BR: ??=0,SPPR=0,SPR=0 */
SPI0_BR = (SPI_BR_SPPR(0x00) | SPI_BR_SPR(0x00));
/* SPI0_M: Bits=0 */
SPI0_M = SPI_M_Bits(0x00);
/* SPI0_C1: SPIE=0,SPE=1,SPTIE=0,MSTR=1,CPOL=0,CPHA=1,SSOE=1,LSBFE=0 */
SPI0_C1 = SPI_C1_SPE_MASK |
SPI_C1_MSTR_MASK |
SPI_C1_CPHA_MASK |
SPI_C1_SSOE_MASK;
}
/*FUNCTION**********************************************************************
*
* Function Name : SPI_HAL_SetBaud
* This function takes in the desired bitsPerSec (baud rate) and calculates the nearest
* possible baud rate without exceeding the desired baud rate, and returns the calculated
* baud rate in bits-per-second. It requires that the caller also provide the frequency of the
* module source clock (in Hertz).
*
*END**************************************************************************/
static uint32_t SPI_HAL_SetBaud(uint32_t instance, uint32_t bitsPerSec, uint32_t sourceClockInHz)
{
uint32_t prescaler, bestPrescaler;
uint32_t rateDivisor, bestDivisor;
uint32_t rateDivisorValue;
uint32_t realBaudrate, bestBaudrate;
uint32_t diff, min_diff;
uint32_t baudrate = bitsPerSec;
/* find combination of prescaler and scaler resulting in baudrate closest to the
* requested value
*/
min_diff = 0xFFFFFFFFU;
bestPrescaler = 0;
bestDivisor = 0;
bestBaudrate = 0; /* required to avoid compilation warning */
/* In all for loops, if min_diff = 0, the exit for loop*/
for (prescaler = 0; (prescaler <= 7) && min_diff; prescaler++)
{
rateDivisorValue = 2U; /* Initialize to div-by-2 */
for (rateDivisor = 0; (rateDivisor <= 8U) && min_diff; rateDivisor++)
{
/* calculate actual baud rate, note need to add 1 to prescaler */
realBaudrate = ((sourceClockInHz) /
((prescaler + 1) * rateDivisorValue));
/* calculate the baud rate difference based on the conditional statement*/
/* that states that the calculated baud rate must not exceed the desired baud rate*/
if (baudrate >= realBaudrate)
{
diff = baudrate-realBaudrate;
if (min_diff > diff)
{
/* a better match found */
min_diff = diff;
bestPrescaler = prescaler; /* Prescale divisor SPIx_BR register bit setting */
bestDivisor = rateDivisor; /* baud rate divisor SPIx_BR register bit setting */
bestBaudrate = realBaudrate;
}
}
/* Multiply by 2 for each iteration, possible divisor values: 2, 4, 8, 16, ... 512 */
rateDivisorValue *= 2U;
}
}
/* write the best prescalar and baud rate scalar */
SPI_InstanceTable[instance]->BR &= ~SPI_BR_SPR_MASK;
SPI_InstanceTable[instance]->BR &= ~SPI_BR_SPPR_MASK;
SPI_InstanceTable[instance]->BR |= SPI_BR_SPR(bestDivisor);
SPI_InstanceTable[instance]->BR |= SPI_BR_SPPR(bestPrescaler);
realBaudrate = ((sourceClockInHz) /
((bestDivisor + 1) * 128));
/* return the actual calculated baud rate*/
return bestBaudrate;
}
/*FUNCTION**********************************************************************
*
* Function Name : SPI_HAL_SetBaud
* This function takes in the desired bitsPerSec (baud rate) and calculates the nearest
* possible baud rate without exceeding the desired baud rate unless the baud rate requested is
* less than the absolute minimum in which case the minimum baud rate will be returned. The returned
* baud rate is in bits-per-second. It requires that the caller also provide the frequency of the
* module source clock (in Hertz).
*
*END**************************************************************************/
uint32_t SPI_HAL_SetBaud(SPI_Type * base, uint32_t bitsPerSec, uint32_t sourceClockInHz)
{
uint32_t prescaler, bestPrescaler;
uint32_t rateDivisor, bestDivisor;
uint32_t rateDivisorValue;
uint32_t realBaudrate, bestBaudrate;
uint32_t diff, min_diff;
uint32_t baudrate = bitsPerSec;
/* find combination of prescaler and scaler resulting in baudrate closest to the
* requested value
*/
min_diff = 0xFFFFFFFFU;
/* Set the maximum divisor bit settings for each of the following divisors */
bestPrescaler = 7;
bestDivisor = 8;
/* Set baud rate to minimum baud rate possible, adjust prescale divisor and divisor
* bit settings in acutal divisor values
*/
bestBaudrate = sourceClockInHz / ((bestPrescaler + 1) * (bestDivisor * 64));
/* In all for loops, if min_diff = 0, the exit for loop*/
for (prescaler = 0; (prescaler <= 7) && min_diff; prescaler++)
{
rateDivisorValue = 2U; /* Initialize to div-by-2 */
for (rateDivisor = 0; (rateDivisor <= 8U) && min_diff; rateDivisor++)
{
/* calculate actual baud rate, note need to add 1 to prescaler */
realBaudrate = ((sourceClockInHz) /
((prescaler + 1) * rateDivisorValue));
/* calculate the baud rate difference based on the conditional statement*/
/* that states that the calculated baud rate must not exceed the desired baud rate*/
if (baudrate >= realBaudrate)
{
diff = baudrate-realBaudrate;
if (min_diff > diff)
{
/* a better match found */
min_diff = diff;
bestPrescaler = prescaler; /* Prescale divisor SPIx_BR register bit setting */
bestDivisor = rateDivisor; /* baud rate divisor SPIx_BR register bit setting */
bestBaudrate = realBaudrate;
}
}
/* Multiply by 2 for each iteration, possible divisor values: 2, 4, 8, 16, ... 512 */
rateDivisorValue *= 2U;
}
}
/* write the best prescalar and baud rate scalar */
SPI_WR_BR(base, SPI_BR_SPR(bestDivisor) | SPI_BR_SPPR(bestPrescaler));
/* return the actual calculated baud rate*/
return bestBaudrate;
}
void spiSetBitRate(int prescaler, int divider)
{
prescaler = MIN(MAX(0, prescaler - 1), 7);
divider = 30 - __builtin_clz(divider);
divider = MIN(MAX(0, divider), 8);
SPI1_BR = SPI_BR_SPPR(prescaler) | SPI_BR_SPR(divider);
}
/* ===================================================================*/
LDD_TDeviceData* SS_SPI1_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate LDD device structure */
SS_SPI1_TDeviceDataPtr DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */
DeviceDataPrv->EnUser = FALSE; /* Disable device */
DeviceDataPrv->ErrFlag = 0x00U; /* Clear error flags */
/* SIM_SCGC4: SPI1=1 */
SIM_SCGC4 |= SIM_SCGC4_SPI1_MASK;
/* SPI1_C1: SPIE=0,SPE=0,SPTIE=0,MSTR=0,CPOL=0,CPHA=1,SSOE=0,LSBFE=0 */
SPI1_C1 = SPI_C1_CPHA_MASK; /* Clear control register */
/* PORTD_PCR6: ISF=0,MUX=2 */
PORTD_PCR6 = (uint32_t)((PORTD_PCR6 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
/* PORTD_PCR7: ISF=0,MUX=2 */
PORTD_PCR7 = (uint32_t)((PORTD_PCR7 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
/* PORTD_PCR5: ISF=0,MUX=2 */
PORTD_PCR5 = (uint32_t)((PORTD_PCR5 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
/* PORTD_PCR4: ISF=0,MUX=2 */
PORTD_PCR4 = (uint32_t)((PORTD_PCR4 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
/* SPI1_C1: SPIE=0,SPE=0,SPTIE=0,MSTR=0,CPOL=0,CPHA=1,SSOE=0,LSBFE=0 */
SPI1_C1 = SPI_C1_CPHA_MASK; /* Set Configuration register */
/* SPI1_C2: SPMIE=0,??=0,TXDMAE=0,MODFEN=0,BIDIROE=0,RXDMAE=0,SPISWAI=0,SPC0=0 */
SPI1_C2 = 0x00U; /* Set Configuration register */
/* SPI1_BR: ??=0,SPPR=0,SPR=0 */
SPI1_BR = (SPI_BR_SPPR(0x00) | SPI_BR_SPR(0x00)); /* Set baud rate register */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_SS_SPI1_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */
}
/*********************************************************
* Name: SPI_High_rate
* Desc: Change SPI baud rate to high speed
* Parameter: None
* Return: None
**********************************************************/
void SPI_High_rate(void)
{
/*Body*/
/* DSPI clock 6 MHz */
/* The system clock fsys = 68 MHz */
/* Value to be passed in SPI_Send_byte() function to DPI_CTAR0 register */
#ifdef MCU_MKL25Z4
SPI1_BR = SPI_BR_SPPR(1) | SPI_BR_SPR(1);
#else
gSPI_BaudRate = (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0x01));
/* Configure the rest of the delays */
gSPI_BeforeTransfDelay = (SPI_CTAR_CSSCK(1) | SPI_CTAR_CSSCK(0x02));
gSPI_AfterTransfDelay = (SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0x02));
gSPI_InterTransfDelay = (SPI_CTAR_PDT(1) | SPI_CTAR_DT(0x01));
#endif
}/*EndBody*/
void spiInit()
{
/* SIM_SCGC4: SPI1=1 */
SIM_SCGC4 |= SIM_SCGC4_SPI1_MASK;
/* SPI1_C1: SPIE=0,SPE=0,SPTIE=0,MSTR=0,CPOL=0,CPHA=1,SSOE=0,LSBFE=0 */
SPI1_C1 = SPI_C1_CPHA_MASK;
/* SPI1_C2: SPMIE=0,SPIMODE=0,TXDMAE=0,MODFEN=0,BIDIROE=0,RXDMAE=0,SPISWAI=0,SPC0=0 */
SPI1_C2 = 0x00U;
/* SPI1_BR: ??=0,SPPR=1,SPR=0 */
SPI1_BR = (SPI_BR_SPPR(0x01) | SPI_BR_SPR(0x00));
/* SPI1_MH: Bits=0 */
SPI1_MH = SPI_MH_Bits(0x00);
/* SPI1_ML: Bits=0 */
SPI1_ML = SPI_ML_Bits(0x00);
/* SPI1_C3: ??=0,??=0,TNEAREF_MARK=0,RNFULLF_MARK=0,INTCLR=0,TNEARIEN=0,RNFULLIEN=0,FIFOMODE=0 */
SPI1_C3 = 0x00U;
/* SPI1_C1: SPIE=0,SPE=1,SPTIE=0,MSTR=1,CPOL=0,CPHA=0,SSOE=0,LSBFE=0 */
SPI1_C1 = (SPI_C1_SPE_MASK | SPI_C1_MSTR_MASK);
SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK;
portInitialise(&portDPins);
}
/* ===================================================================*/
LDD_TDeviceData* SS1_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate LDD device structure */
SS1_TDeviceDataPtr DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */
/* Interrupt vector(s) allocation */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_SPI1__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
DeviceDataPrv->ErrFlag = 0x00U; /* Clear error flags */
/* Clear the receive counters and pointer */
DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */
/* Clear the transmit counters and pointer */
DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */
DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */
/* SIM_SCGC4: SPI1=1 */
SIM_SCGC4 |= SIM_SCGC4_SPI1_MASK;
/* SPI1_C1: SPIE=0,SPE=0,SPTIE=0,MSTR=0,CPOL=0,CPHA=1,SSOE=0,LSBFE=0 */
SPI1_C1 = SPI_C1_CPHA_MASK; /* Clear control register */
/* Interrupt vector(s) priority setting */
/* NVIC_IPR2: PRI_11=0x80 */
NVIC_IPR2 = (uint32_t)((NVIC_IPR2 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_11(0x7F)
)) | (uint32_t)(
NVIC_IP_PRI_11(0x80)
));
/* NVIC_ISER: SETENA|=0x0800 */
NVIC_ISER |= NVIC_ISER_SETENA(0x0800);
/* PORTE_PCR3: ISF=0,MUX=5 */
PORTE_PCR3 = (uint32_t)((PORTE_PCR3 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x02)
)) | (uint32_t)(
PORT_PCR_MUX(0x05)
));
/* PORTE_PCR1: ISF=0,MUX=5 */
PORTE_PCR1 = (uint32_t)((PORTE_PCR1 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x02)
)) | (uint32_t)(
PORT_PCR_MUX(0x05)
));
/* PORTE_PCR2: ISF=0,MUX=2 */
PORTE_PCR2 = (uint32_t)((PORTE_PCR2 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
/* PORTE_PCR4: ISF=0,MUX=2 */
PORTE_PCR4 = (uint32_t)((PORTE_PCR4 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
/* SPI1_C1: SPIE=0,SPE=0,SPTIE=0,MSTR=0,CPOL=0,CPHA=0,SSOE=0,LSBFE=0 */
SPI1_C1 = 0x00U; /* Set Configuration register */
/* SPI1_C2: SPMIE=0,??=0,TXDMAE=0,MODFEN=0,BIDIROE=0,RXDMAE=0,SPISWAI=0,SPC0=0 */
SPI1_C2 = 0x00U; /* Set Configuration register */
/* SPI1_BR: ??=0,SPPR=0,SPR=0 */
SPI1_BR = (SPI_BR_SPPR(0x00) | SPI_BR_SPR(0x00)); /* Set baud rate register */
/* SPI1_C1: SPE=1 */
SPI1_C1 |= SPI_C1_SPE_MASK; /* Enable device */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_SS1_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */
}
void ssd1306_init(void)
{
uint32_t i;
// init necessary io
// enable clocks for PORTA & PORTB
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
// pin 13, B5 output for rst
PORTB_PCR5 = PORT_PCR_MUX(1); // gpio
GPIOB_PCOR = (1 << 5); // low initially
GPIOB_PDDR |= (1 << 5); // output mode
// pin 6, a6 output for dc
PORTA_PCR6 = PORT_PCR_MUX(1); // gpio
GPIOA_PCOR = (1 << 6); // low initially
GPIOA_PDDR |= (1 << 6); // output mode
// init spi0
// configure io pins for spi
// PTA5, 7, PTB0
PORTA_PCR5 = PORT_PCR_MUX(3); // CS
PORTA_PCR7 = PORT_PCR_MUX(3); // MOSI
PORTB_PCR0 = PORT_PCR_MUX(3); // SCK
// enable SPI0 module
SIM_SCGC4 |= SIM_SCGC4_SPI0_MASK;
// configure as master, cs output driven automatically, CPOL=1
SPI0_C1 |= (SPI_C1_MSTR_MASK | SPI_C1_SSOE_MASK | SPI_C1_CPOL_MASK);
SPI0_C2 |= SPI_C2_MODFEN_MASK;
// select clock divider- SPPR = 0, SPR = 0 (2)
SPI0_BR = SPI_BR_SPPR(0) | SPI_BR_SPR(3);
// turn on spi
SPI0_C1 |= SPI_C1_SPE_MASK;
// do some setup on the oled display
// wait a ms after 3.3v comes up on reset
delay_ms(10);
// reset low for 10ms
CLR_RST(); // low
delay_ms(10);
SET_RST(); // now high
// give it a few ms after reset goes high
delay_ms(5);
// now initialize display controller
// Init sequence for 128x64 OLED module
ssd1306_command(SSD1306_DISPLAYOFF); // 0xAE
ssd1306_command(SSD1306_SETDISPLAYCLOCKDIV); // 0xD5
ssd1306_command(0x80); // the suggested ratio 0x80
ssd1306_command(SSD1306_SETMULTIPLEX); // 0xA8
ssd1306_command(0x3F);
ssd1306_command(SSD1306_SETDISPLAYOFFSET); // 0xD3
ssd1306_command(0x0); // no offset
ssd1306_command(SSD1306_SETSTARTLINE | 0x0); // line #0
ssd1306_command(SSD1306_CHARGEPUMP); // 0x8D
ssd1306_command(0x14); // internall VCC
ssd1306_command(SSD1306_MEMORYMODE); // 0x20
ssd1306_command(0x00); // 0x0 act like ks0108
ssd1306_command(SSD1306_SEGREMAP /*| 0x1*/);
ssd1306_command(SSD1306_COMSCANINC);
ssd1306_command(SSD1306_SETCOMPINS); // 0xDA
ssd1306_command(0x12);
ssd1306_command(SSD1306_SETCONTRAST); // 0x81
ssd1306_command(0xCF); // internal VCC
ssd1306_command(SSD1306_SETPRECHARGE); // 0xd9
ssd1306_command(0xF1); // internal VCC
ssd1306_command(SSD1306_SETVCOMDETECT); // 0xDB
ssd1306_command(0x40);
ssd1306_command(SSD1306_DISPLAYALLON_RESUME); // 0xA4
ssd1306_command(SSD1306_NORMALDISPLAY); // 0xA6
ssd1306_command(SSD1306_DISPLAYON);//--turn on oled panel
// set display to noahs face
ssd1306_command(SSD1306_SETLOWCOLUMN | 0x0); // low col = 0
ssd1306_command(SSD1306_SETHIGHCOLUMN | 0x0); // hi col = 0
ssd1306_command(SSD1306_SETSTARTLINE | 0x0); // line #0
for(i=0; i<SSD1306_SIZEOF_SCREENBUF; i++){
ssd1306_data(noahs_face[i]);
}
}
/*********************************************************
* Name: SPI_Init
* Desc: Initialize SPI2 Module
* Parameter: None
* Return: None
**********************************************************/
void SPI_Init(void)
{
/*Body*/
/* set PORTE pin 1 to DSPI1.SOUT*/
#ifdef MCU_MK70F12
/* set PORTE pin 1 to DSPI1.SOUT*/
PORTE_PCR1 = PORT_PCR_MUX(7);
/* set PORTE pin 2 to DSPI1.SCK*/
PORTE_PCR2 = PORT_PCR_MUX(2);
/* set PORTE pin 3 to DSPI1.SIN*/
PORTE_PCR3 = PORT_PCR_MUX(7);
/* set PORTE pin 4 to DSPI1.CS0*/
PORTE_PCR4 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC6 |= SIM_SCGC6_DSPI1_MASK;
#elif defined MCU_MK20D5
/* set PORTD pin 1 to SPI0.SOUT*/
PORTD_PCR2 = PORT_PCR_MUX(2);
/* set PORTD pin 1 to SPI0.SCK*/
PORTD_PCR1 = PORT_PCR_MUX(2);
/* set PORTD pin 3 to SPI0.SIN*/
PORTD_PCR3 = PORT_PCR_MUX(2);
/* set PORTD pin 0 to SPI0.CS0*/
PORTD_PCR0 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC6 |= SIM_SCGC6_SPI0_MASK;
#elif defined MCU_MK20D7
/* set PORTE pin 1 to DSPI1.SOUT*/
PORTE_PCR1 = PORT_PCR_MUX(2);
/* set PORTE pin 2 to DSPI1.SCK*/
PORTE_PCR2 = PORT_PCR_MUX(2);
/* set PORTE pin 3 to DSPI1.SIN*/
PORTE_PCR3 = PORT_PCR_MUX(2);
/* set PORTE pin 4 to DSPI1.CS0*/
PORTE_PCR4 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
#elif defined MCU_MK40D7
/* set PORTE pin 1 to DSPI1.SOUT*/
PORTE_PCR1 = PORT_PCR_MUX(2);
/* set PORTE pin 2 to DSPI1.SCK*/
PORTE_PCR2 = PORT_PCR_MUX(2);
/* set PORTE pin 3 to DSPI1.SIN*/
PORTE_PCR3 = PORT_PCR_MUX(2);
/* set PORTE pin 4 to DSPI1.CS0*/
PORTE_PCR4 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
#elif defined MCU_MK40N512VMD100
/* set PORTE pin 1 to DSPI1.SOUT*/
PORTE_PCR1 = PORT_PCR_MUX(2);
/* set PORTE pin 2 to DSPI1.SCK*/
PORTE_PCR2 = PORT_PCR_MUX(2);
/* set PORTE pin 3 to DSPI1.SIN*/
PORTE_PCR3 = PORT_PCR_MUX(2);
/* set PORTE pin 4 to DSPI1.CS0*/
PORTE_PCR4 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
#elif defined MCU_MK53N512CMD100
/* set PORTE pin 1 to DSPI1.SOUT*/
PORTE_PCR1 = PORT_PCR_MUX(2);
/* set PORTE pin 2 to DSPI1.SCK*/
PORTE_PCR2 = PORT_PCR_MUX(2);
/* set PORTE pin 3 to DSPI1.SIN*/
PORTE_PCR3 = PORT_PCR_MUX(2);
/* set PORTE pin 4 to DSPI1.CS0*/
PORTE_PCR4 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
#elif defined MCU_MK60N512VMD100
/* set PORTE pin 1 to DSPI1.SOUT*/
PORTE_PCR1 = PORT_PCR_MUX(2);
/* set PORTE pin 2 to DSPI1.SCK*/
PORTE_PCR2 = PORT_PCR_MUX(2);
/* set PORTE pin 3 to DSPI1.SIN*/
PORTE_PCR3 = PORT_PCR_MUX(2);
/* set PORTE pin 4 to DSPI1.CS0*/
PORTE_PCR4 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
#elif defined MCU_MK21D5
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
/* set PORTB pin 16 to DSPI1.SOUT*/
PORTB_PCR16 = PORT_PCR_MUX(2);
/* set PORTB pin 11 to DSPI1.SCK*/
PORTB_PCR11 = PORT_PCR_MUX(2);
/* set PORTB pin 17 to DSPI1.SIN*/
PORTB_PCR17 = PORT_PCR_MUX(2);
/* set PORTB pin 10 to DSPI1.CS0*/
PORTB_PCR10 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK | SIM_SCGC6_DMAMUX_MASK;
#elif defined MCU_MKL25Z4
/* set PORTE pin 1 to DSPI1.SOUT*/
PORTE_PCR1 = PORT_PCR_MUX(2);
/* set PORTE pin 2 to DSPI1.SCK*/
PORTE_PCR2 = PORT_PCR_MUX(2);
/* set PORTE pin 3 to DSPI1.SIN*/
PORTE_PCR3 = PORT_PCR_MUX(2);
/* set PORTE pin 4 to DSPI1.CS0*/
PORTE_PCR4 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC4 |= SIM_SCGC4_SPI1_MASK;
SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
#else
/* set PORTE pin 1 to DSPI1.SOUT*/
PORTE_PCR1 = PORT_PCR_MUX(2);
/* set PORTE pin 2 to DSPI1.SCK*/
PORTE_PCR2 = PORT_PCR_MUX(2);
/* set PORTE pin 3 to DSPI1.SIN*/
PORTE_PCR3 = PORT_PCR_MUX(2);
/* set PORTE pin 4 to DSPI1.CS0*/
PORTE_PCR4 = PORT_PCR_MUX(2);
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* Enable clock gate to DSPI1 module */
SIM_SCGC6 |= SIM_SCGC6_DMAMUX_SPI1_MASK;
#endif
/* Enable master mode, disable both transmit and receive FIFO buffers,
set the inactive state for PCS2 high, enable the module (MDIS = 0),
delay the sample point from the leading edge of the clock and halt
any transfer
*/
#ifdef MCU_MK20D5
SPI0_MCR = (SPI_MCR_MSTR_MASK |
SPI_MCR_PCSIS(1) |
SPI_MCR_SMPL_PT(2) |
SPI_MCR_HALT_MASK);
SPI0_MCR |= (SPI_MCR_CLR_RXF_MASK | SPI_MCR_CLR_TXF_MASK);
#elif defined MCU_MKL25Z4
PORTE_PCR4 = PORT_PCR_MUX(1);
GPIOE_PDDR |= (1<<4);
SPI_clr_SS();
SPI1_C2 = SPI_C2_SPISWAI_MASK;
SPI1_C1 = SPI_C1_SPE_MASK | SPI_C1_MSTR_MASK | SPI_C1_SSOE_MASK;
#else
SPI1_MCR = (SPI_MCR_MSTR_MASK |
SPI_MCR_PCSIS(1) |
SPI_MCR_SMPL_PT(2) |
SPI_MCR_HALT_MASK);
SPI1_MCR |= (SPI_MCR_CLR_RXF_MASK | SPI_MCR_CLR_TXF_MASK);
#endif
/* DSPI clock 375 KHz */
/* The system clock fsys = 68 MHz */
// K60: bus clock: 48MHz, DSPI clock: ~107 KHz
// K70: bus clock: 60MHz, DSPI clock: ~156 KHz
/* Value to be passed in SPI_Send_byte() function to DPI_CTAR0 register */
#ifdef MCU_MKL25Z4
/* 375KHz SPI clock */
SPI1_BR = SPI_BR_SPPR(7) | SPI_BR_SPR(5); /* SCK = 10us */
#else
#ifdef MCU_MK70F12
gSPI_BaudRate = (SPI_CTAR_PBR(1) | SPI_CTAR_BR(0x07));
#else
gSPI_BaudRate = (SPI_CTAR_PBR(3) | SPI_CTAR_BR(0x06));
#endif
/* Configure the rest of the delays */
gSPI_BeforeTransfDelay = (SPI_CTAR_CSSCK(1) | SPI_CTAR_CSSCK(0x04));
gSPI_AfterTransfDelay = (SPI_CTAR_PASC(3) | SPI_CTAR_ASC(0x04));
gSPI_InterTransfDelay = (SPI_CTAR_PDT(3) | SPI_CTAR_DT(0x05));
#endif
}/*EndBody*/
void spi_init( void )
{
#if 0
/* SPI Initial functions module---Open clock gating and Pin mux for spi, Close COP(watchdog) with clock gating or --- */
/**/
//SIM_SCGC4 |= SIM_SCGC4_SPI0_MASK|SIM_SCGC4_SPI1_MASK; //Enable SPI0 Clock gate
SIM_SCGC4 |= SIM_SCGC4_SPI0_MASK; //Enable SPI0 Clock gate
SIM_COPC &= (~SIM_COPC_COPT_MASK); //Disable COP Watchdog
//SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK|SIM_SCGC5_PORTB_MASK|SIM_SCGC5_PORTD_MASK|SIM_SCGC5_PORTE_MASK|SIM_SCGC5_PORTC_MASK;
// disable SPI
//SPI1_C1 &= ~SPI_C1_SPE_MASK;
SPI0_C1 &= ~SPI_C1_SPE_MASK;
PORTD_PCR0 &= ~PORT_PCR_MUX_MASK;
PORTD_PCR0 |= PORT_PCR_MUX(2)|PORT_PCR_DSE_MASK; //Use PTD0 as SPI0_SS_b
PORTD_PCR3 &= ~PORT_PCR_MUX_MASK;
PORTD_PCR3 |= PORT_PCR_MUX(2)|PORT_PCR_DSE_MASK; //Use PTD3 as SPI0_MISO
PORTD_PCR2 &= ~PORT_PCR_MUX_MASK;
PORTD_PCR2 |= PORT_PCR_MUX(2)|PORT_PCR_DSE_MASK; //Use PTD2 as SPI0_MOSI
PORTD_PCR1 &= ~PORT_PCR_MUX_MASK;
PORTD_PCR1 = PORT_PCR_MUX(2)|PORT_PCR_DSE_MASK; //Use PTD1 as SPI0_SCK
//PORTE_PCR4 &= ~PORT_PCR_MUX_MASK; //spi1_cs
//PORTE_PCR4 |= PORT_PCR_MUX(2)|PORT_PCR_DSE_MASK; //Use PTE4 as SPI1_SS_b
//PORTE_PCR1 &= ~PORT_PCR_MUX_MASK; //sin
//PORTE_PCR1 |= PORT_PCR_MUX(2)|PORT_PCR_DSE_MASK; //Use PTE1 as SPI1_MISO
//PORTE_PCR3 &= ~PORT_PCR_MUX_MASK; //dout
//PORTE_PCR3 |= PORT_PCR_MUX(2)|PORT_PCR_DSE_MASK; //Use PTE3 as SPI1_MOSI
//PORTE_PCR2 &= ~PORT_PCR_MUX_MASK; //spi1_sck
//PORTE_PCR2 = PORT_PCR_MUX(2)|PORT_PCR_DSE_MASK; //Use PTE2 as SPI1_SCK
//SPI0_C1 |= SPI_C1_MSTR_MASK; //-----master----bus clock is 12.5Mhz--0.08us--
//SPI0_BR = 0x02;
SPI0_C1 &= (~SPI_C1_MSTR_MASK);
//SPI0_BR = 0x43; //SPPR = 4, SPR = 3, bps div = (SPPR+1)*2^(SPR+1) = 80,----Tspi--6.4us
//SPI0_BR = 0x40; //bps div = 10,---------0.8us
//SPI0_BR = 0x30; //bps div = 8,----------0.64us
//SPI0_BR = 0x10; //bps div = 4,----------0.32us
//SPI0_BR = 0x00; //bps div = 2,----------0.16us----6.125Mhz
//SPI0_BR = 0x54; //bps div = 192,----------15.36us
//SPI0_BR = 0x77; //bps div = 2048,----------163.84us
// SPI0_BR = 0x00;
SPI0_C1 |= SPI_C1_SSOE_MASK; //|SPI0_C1_CPOL_MASK|SPI0_C1_LSBFE_MASK;
SPI0_C2 |= SPI_C2_MODFEN_MASK;
SPI0_C1 |= SPI_C1_CPHA_MASK;
SPI0_C1 &= (~SPI_C1_CPHA_MASK);
SPI0_C1 |= SPI_C1_CPOL_MASK;
SPI0_C1 &= (~SPI_C1_CPOL_MASK);
//SPI0_C1 |= SPI_C1_LSBFE_MASK;
SPI0_C1 &= (~SPI_C1_LSBFE_MASK);
//SPI0_C1 &= (~SPI0_C1_SPIE_MASK); //Disable RX interrrupt
//SPI0_C1 |= SPI0_C1_SPIE_MASK; //enable RX interrrupt
//SPI0_C1 &= (~SPI0_C1_SPTIE_MASK); //Disable the transmit interrupt
//SPI0_C1 |= SPI0_C1_SPTIE_MASK; //Enable the transime interrupt
//SPI1_C1 |= SPI_C1_MSTR_MASK;
//SPI1_BR = 0x02;
// SPI1_C1 &= (~SPI_C1_MSTR_MASK); //---slave----bus clock is 12.5Mhz--0.08us--
//SPI0_BR = 0x43; //SPPR = 4, SPR = 3, bps div = (SPPR+1)*2^(SPR+1) = 80,----Tspi--6.4us
//SPI0_BR = 0x40; //bps div = 10,---------0.8us
//SPI0_BR = 0x30; //bps div = 8,----------0.64us
//SPI0_BR = 0x10; //bps div = 4,----------0.32us
//SPI0_BR = 0x00; //bps div = 2,----------0.16us----6.125Mhz
//SPI0_BR = 0x54; //bps div = 192,----------15.36us
//SPI0_BR = 0x77; //bps div = 2048,----------163.84us
// SPI1_BR = 0x01;
//SPI1_C1 |= SPI_C1_SSOE_MASK;
//SPI1_C2 |= SPI_C2_MODFEN_MASK;
//SPI1_C1 |= SPI_C1_CPHA_MASK;
//SPI1_C1 &= (~SPI_C1_CPHA_MASK);
//SPI1_C1 |= SPI_C1_CPOL_MASK;
//SPI1_C1 &= (~SPI_C1_CPOL_MASK);
//SPI1_C1 |= SPI_C1_LSBFE_MASK;
//SPI1_C1 &= (~SPI_C1_LSBFE_MASK);
//SPI1_C2 |= SPI_C2_RXDMAE_MASK;
SPI0_C2 |= SPI_C2_TXDMAE_MASK;
SPI0_C2 |= SPI_C2_RXDMAE_MASK;
//SPI1_C2 |= SPI_C2_TXDMAE_MASK;
SPI0_C1 |= SPI_C1_SPE_MASK;
//SPI1_C1 |= SPI_C1_SPE_MASK;
#else
SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK; //Turn on clock to D module
SIM_SCGC4 |= SIM_SCGC4_SPI0_MASK; //Enable SPI0 clock
PORTD_PCR0 = PORT_PCR_MUX(0x1); //Set PTD0 to mux 2 [SPI0_PCS0]
PORTD_PCR1 = PORT_PCR_MUX(0x2); //Set PTD1 to mux 2 [SPI0_SCK]
PORTD_PCR2 = PORT_PCR_MUX(0x2); //Set PTD2 to mux 2 [SPI0_MOSI]
PORTD_PCR3 = PORT_PCR_MUX(0x2); //Set PTD3 to mux 2 [SPIO_MISO]
SPI0_C1 = SPI_C1_MSTR_MASK | SPI_C1_SSOE_MASK; //Set SPI0 to Master & SS pin to auto SS
SPI0_C2 = SPI_C2_MODFEN_MASK; //Master SS pin acts as slave select output
SPI0_BR = (SPI_BR_SPPR(0x02) | SPI_BR_SPR(0x08)); //Set baud rate prescale divisor to 3 & set baud rate divisor to 64 for baud rate of 15625 hz
//SPI0_BR = 0x00;
SPI0_C1 |= SPI_C1_SPE_MASK; //Enable SPI0
#endif
}
