/****************************************************************************** * FunctionName : spi_lcd_mode_init * Description : SPI master initial function for driving LCD TM035PDZV36 * Parameters : uint8 spi_no - SPI module number, Only "SPI" and "HSPI" are valid *******************************************************************************/ void spi_lcd_mode_init(uint8 spi_no) { uint32 regvalue; if(spi_no>1) return; //handle invalid input number //bit9 of PERIPHS_IO_MUX should be cleared when HSPI clock doesn't equal CPU clock //bit8 of PERIPHS_IO_MUX should be cleared when SPI clock doesn't equal CPU clock if(spi_no==SPI){ WRITE_PERI_REG(PERIPHS_IO_MUX, 0x005); //clear bit9,and bit8 PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, 1);//configure io to spi mode PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 1);//configure io to spi mode PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, 1);//configure io to spi mode PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, 1);//configure io to spi mode }else if(spi_no==HSPI){ WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105); //clear bit9 PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, 2);//configure io to spi mode PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 2);//configure io to spi mode PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, 2);//configure io to spi mode PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, 2);//configure io to spi mode } SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_CS_SETUP|SPI_CS_HOLD|SPI_USR_COMMAND); CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_FLASH_MODE); // SPI clock=CPU clock/8 WRITE_PERI_REG(SPI_CLOCK(spi_no), ((1&SPI_CLKDIV_PRE)<<SPI_CLKDIV_PRE_S)| ((3&SPI_CLKCNT_N)<<SPI_CLKCNT_N_S)| ((1&SPI_CLKCNT_H)<<SPI_CLKCNT_H_S)| ((3&SPI_CLKCNT_L)<<SPI_CLKCNT_L_S)); //clear bit 31,set SPI clock div }
/****************************************************************************** * FunctionName : spi_master_init * Description : SPI master initial function for common byte units transmission * Parameters : uint8 spi_no - SPI module number, Only "SPI" and "HSPI" are valid *******************************************************************************/ void ICACHE_FLASH_ATTR spi_master_init(uint8 spi_no) { uint32 regvalue; if(spi_no>1) return; //handle invalid input number SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_CS_SETUP|SPI_CS_HOLD|SPI_USR_COMMAND); CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_FLASH_MODE); WRITE_PERI_REG(SPI_CLOCK(spi_no), ((3&SPI_CLKCNT_N)<<SPI_CLKCNT_N_S)| ((1&SPI_CLKCNT_H)<<SPI_CLKCNT_H_S)| ((3&SPI_CLKCNT_L)<<SPI_CLKCNT_L_S)); //clear bit 31,set SPI clock div }
/** * @brief Based on pAttr initialize SPI module. * */ void ICACHE_FLASH_ATTR SPIInit (SpiNum spiNum, SpiAttr* pAttr) { if ((spiNum > SpiNum_HSPI) || (NULL == pAttr)) { return; } // SPI_CPOL & SPI_CPHA switch (pAttr->subMode) { case SpiSubMode_1: CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE); SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE break; case SpiSubMode_2: SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE); SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE break; case SpiSubMode_3: SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE); CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); break; case SpiSubMode_0: default: CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE); CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // To do nothing break; } // SPI bit order if (SpiBitOrder_MSBFirst == pAttr->bitOrder) { CLEAR_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_WR_BIT_ORDER); CLEAR_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_RD_BIT_ORDER); } else if (SpiBitOrder_LSBFirst == pAttr->bitOrder) { SET_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_WR_BIT_ORDER); SET_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_RD_BIT_ORDER); } else { // To do nothing } // Disable flash operation mode // As earlier as better, if not SPI_CTRL2 can not to be set delay cycles. CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_FLASH_MODE); // SPI mode type if (SpiMode_Master == pAttr->mode) { // SPI mode type CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), SPI_SLAVE_MODE); // SPI Send buffer CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO_HIGHPART);// By default slave send buffer C0-C7 // SPI Speed if (1 < (pAttr->speed)) { uint8 i, k; i = (pAttr->speed / 40) ? (pAttr->speed / 40) : 1; k = pAttr->speed / i; CLEAR_PERI_REG_MASK(SPI_CLOCK(spiNum), SPI_CLK_EQU_SYSCLK); WRITE_PERI_REG(SPI_CLOCK(spiNum), (((i - 1) & SPI_CLKDIV_PRE) << SPI_CLKDIV_PRE_S) | (((k - 1) & SPI_CLKCNT_N) << SPI_CLKCNT_N_S) | ((((k + 1) / 2 - 1) & SPI_CLKCNT_H) << SPI_CLKCNT_H_S) | (((k - 1) & SPI_CLKCNT_L) << SPI_CLKCNT_L_S)); //clear bit 31,set SPI clock div } else { WRITE_PERI_REG(SPI_CLOCK(spiNum), SPI_CLK_EQU_SYSCLK); // 80Mhz speed } // By default format:CMD+ADDR+DATA SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CS_SETUP | SPI_CS_HOLD | SPI_USR_MOSI); //delay num SET_PERI_REG_MASK(SPI_CTRL2(spiNum), ((0x1 & SPI_MISO_DELAY_NUM) << SPI_MISO_DELAY_NUM_S)); } else if (SpiMode_Slave == pAttr->mode) { // BIT19 must do SET_PERI_REG_MASK(SPI_PIN(spiNum), BIT19); // SPI mode type SET_PERI_REG_MASK(SPI_SLAVE(spiNum), SPI_SLAVE_MODE); // SPI Send buffer SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO_HIGHPART);// By default slave send buffer C8-C15 SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI); // If do not set delay cycles, slave not working,master cann't get the data. SET_PERI_REG_MASK(SPI_CTRL2(spiNum), ((0x1 & SPI_MOSI_DELAY_NUM) << SPI_MOSI_DELAY_NUM_S)); //delay num // SPI Speed WRITE_PERI_REG(SPI_CLOCK(spiNum), 0); // By default format::CMD(8bits)+ADDR(8bits)+DATA(32bytes). SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN, 7, SPI_USR_COMMAND_BITLEN_S); SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_WR_ADDR_BITLEN, 7, SPI_SLV_WR_ADDR_BITLEN_S); SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_RD_ADDR_BITLEN, 7, SPI_SLV_RD_ADDR_BITLEN_S); SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_BUF_BITLEN, (32 * 8 - 1), SPI_SLV_BUF_BITLEN_S); // For 8266 work on slave mode. SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_STATUS_BITLEN, 7, SPI_SLV_STATUS_BITLEN_S); } else { // To do nothing } //clear Daul or Quad lines transmission mode CLEAR_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_QIO_MODE | SPI_DIO_MODE | SPI_DOUT_MODE | SPI_QOUT_MODE); // Clear the data buffer. uint8 i; uint32 regAddr = REG_SPI_BASE(spiNum) + 0x40; for (i = 0; i < 16; ++i) { WRITE_PERI_REG(regAddr, 0); regAddr += 4; } }