/* Initialize the SPI */ void Chip_SPI_IF_Init(LPC_SPI_T *pSPI, SPI_MODECONFIG_T *pConfig) { uint32_t EnStat; Chip_SPI_Init(pSPI); EnStat = pSPI->CFG & SPI_CFG_SPI_EN; /* Disable before update CFG register */ if (EnStat) { Chip_SPI_Disable(pSPI); } /* SPI Configurate */ pSPI->CFG = ((uint32_t) pConfig->ClockMode) | ((uint32_t) pConfig->DataOrder) | ((uint32_t) pConfig->Mode) | ((uint32_t) pConfig->SSELPol); if ( pConfig->Mode == SPI_CFG_MASTER_EN ) { /* Rate Divider setting */ pSPI->DIV = SPI_DIV_VAL(pConfig->ClkDiv); } /* Clear status flag*/ Chip_SPI_ClearStatus(pSPI, SPI_STAT_RXOV | SPI_STAT_TXUR | SPI_STAT_SSA | SPI_STAT_SSD); /* Return the previous state */ if (EnStat) { Chip_SPI_Enable(pSPI); } }
/* Initialize the SPI */ void Chip_SPI_Init(LPC_SPI_T *pSPI, SPI_CONFIG_T *pConfig) { uint32_t EnStat = pSPI->CFG & SPI_CFG_SPI_EN; Chip_Clock_EnablePeriphClock((pSPI == LPC_SPI1) ? SYSCTL_CLOCK_SPI1 : SYSCTL_CLOCK_SPI0); Chip_SYSCTL_PeriphReset((pSPI == LPC_SPI1) ? RESET_SPI1 : RESET_SPI0); /* Disable before update CFG register */ if (EnStat) { Chip_SPI_Disable(pSPI); } /* SPI Configurate */ pSPI->CFG = ((uint32_t) pConfig->ClockMode) | ((uint32_t) pConfig->DataOrder) | ((uint32_t) pConfig->Mode) | ((uint32_t) pConfig->SSELPol); /* Rate Divider setting */ pSPI->DIV = SPI_DIV_VAL(pConfig->ClkDiv); /* Clear status flag*/ Chip_SPI_ClearStatus(pSPI, SPI_STAT_CLR_RXOV | SPI_STAT_CLR_TXUR | SPI_STAT_CLR_SSA | SPI_STAT_CLR_SSD); /* Return the previous state */ if (EnStat) { Chip_SPI_Enable(pSPI); } }
/* Initialize SPI peripheral block */ void IP_SPI_Init(IP_SPI_002_T *pSPI, IP_SPI_CONFIG_T *pConfig) { uint32_t EnStat = pSPI->CFG & SPI_CFG_SPI_EN; /* Disable before update CFG register */ if (EnStat) { IP_SPI_Disable(pSPI); } /* SPI Configurate */ pSPI->CFG = ((uint32_t) pConfig->ClockMode) | ((uint32_t) pConfig->DataOrder) | ((uint32_t) pConfig->Mode) | ((uint32_t) pConfig->SSELPol); /* Rate Divider setting */ pSPI->DIV = SPI_DIV_VAL(pConfig->ClkDiv); /* Clear status flag*/ IP_SPI_ClearStatus(pSPI, SPI_STAT_CLR_RXOV | SPI_STAT_CLR_TXUR | SPI_STAT_CLR_SSA | SPI_STAT_CLR_SSD); /* Return the previous state */ if (EnStat) { IP_SPI_Enable(pSPI); } }