void cpu_deinit_all() { //** ADC_DeInit(LPC_ADC); CAN_DeInit(LPC_CAN1); CAN_DeInit(LPC_CAN2); EMAC_DeInit(); EXTI_DeInit(); I2C_DeInit(LPC_I2C0); I2C_DeInit(LPC_I2C1); I2C_DeInit(LPC_I2C2); I2S_DeInit(LPC_I2S); NVIC_DeInit(); NVIC_SCBDeInit(); PWM_DeInit(LPC_PWM1); QEI_DeInit(LPC_QEI); //** RIT_DeInit(LPC_RIT); RTC_DeInit(LPC_RTC); SPI_DeInit(LPC_SPI); SSP_DeInit(LPC_SSP0); SSP_DeInit(LPC_SSP1); UART_DeInit(LPC_UART0); UART_DeInit((LPC_UART_TypeDef *) LPC_UART1); //** UART_DeInit(LPC_UART2); //** UART_DeInit(LPC_UART3); TIM_DeInit(LPC_TIM0); TIM_DeInit(LPC_TIM1); //** TIM_DeInit(LPC_TIM2); //** TIM_DeInit(LPC_TIM3); }
void spi_close(void) { PINSEL_CFG_Type PinCfg; SSP_Cmd(pSPI, DISABLE); SSP_DeInit(pSPI); /* PinCfg.Funcnum = PINSEL_FUNC_0; PinCfg.OpenDrain = PINSEL_PINMODE_NORMAL; PinCfg.Pinmode = PINSEL_PINMODE_PULLDOWN; PinCfg.Pinnum = 16; PinCfg.Portnum = 0; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 15; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 17; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 18; PINSEL_ConfigPin(&PinCfg); */ }
void main(void) #endif { RST_CLK_DeInit(); RST_CLK_CPU_PLLconfig (RST_CLK_CPU_PLLsrcHSIdiv2,0); /* Enable peripheral clocks --------------------------------------------------*/ RST_CLK_PCLKcmd((RST_CLK_PCLK_RST_CLK | RST_CLK_PCLK_SSP1 | RST_CLK_PCLK_SSP2 | RST_CLK_PCLK_DMA),ENABLE); RST_CLK_PCLKcmd((RST_CLK_PCLK_PORTF | RST_CLK_PCLK_PORTD), ENABLE); /* Init NVIC */ SCB->AIRCR = 0x05FA0000 | ((uint32_t)0x500); SCB->VTOR = 0x08000000; /* Disable all interrupt */ NVIC->ICPR[0] = 0xFFFFFFFF; NVIC->ICER[0] = 0xFFFFFFFF; /* Disable all DMA request */ MDR_DMA->CHNL_REQ_MASK_CLR = 0xFFFFFFFF; MDR_DMA->CHNL_USEBURST_CLR = 0xFFFFFFFF; /* Reset PORTD settings */ PORT_DeInit(MDR_PORTD); /* Reset PORTF settings */ PORT_DeInit(MDR_PORTF); /* Configure SSP2 pins: FSS, CLK, RXD, TXD */ /* Configure PORTD pins 2, 3, 5, 6 */ PORT_InitStructure.PORT_Pin = (PORT_Pin_2 | PORT_Pin_3 | PORT_Pin_5); PORT_InitStructure.PORT_OE = PORT_OE_IN; PORT_InitStructure.PORT_FUNC = PORT_FUNC_ALTER; PORT_InitStructure.PORT_MODE = PORT_MODE_DIGITAL; PORT_InitStructure.PORT_SPEED = PORT_SPEED_FAST; PORT_Init(MDR_PORTD, &PORT_InitStructure); PORT_InitStructure.PORT_OE = PORT_OE_OUT; PORT_InitStructure.PORT_Pin = (PORT_Pin_6); PORT_Init(MDR_PORTD, &PORT_InitStructure); /* Configure SSP1 pins: FSS, CLK, RXD, TXD */ /* Configure PORTF pins 0, 1, 2, 3 */ PORT_InitStructure.PORT_Pin = (PORT_Pin_3); PORT_InitStructure.PORT_OE = PORT_OE_IN; PORT_Init(MDR_PORTF, &PORT_InitStructure); PORT_InitStructure.PORT_Pin = (PORT_Pin_0 | PORT_Pin_1 | PORT_Pin_2); PORT_InitStructure.PORT_OE = PORT_OE_OUT; PORT_Init(MDR_PORTF, &PORT_InitStructure); /* Init RAM */ Init_RAM (DstBuf1, BufferSize); Init_RAM (SrcBuf1, BufferSize); Init_RAM (DstBuf2, BufferSize); Init_RAM (SrcBuf2, BufferSize); /* Reset all SSP settings */ SSP_DeInit(MDR_SSP1); SSP_DeInit(MDR_SSP2); SSP_BRGInit(MDR_SSP1,SSP_HCLKdiv16); SSP_BRGInit(MDR_SSP2,SSP_HCLKdiv16); /* SSP1 MASTER configuration ------------------------------------------------*/ SSP_StructInit (&sSSP); sSSP.SSP_SCR = 0x10; sSSP.SSP_CPSDVSR = 2; sSSP.SSP_Mode = SSP_ModeMaster; sSSP.SSP_WordLength = SSP_WordLength16b; sSSP.SSP_SPH = SSP_SPH_1Edge; sSSP.SSP_SPO = SSP_SPO_Low; sSSP.SSP_FRF = SSP_FRF_SPI_Motorola; sSSP.SSP_HardwareFlowControl = SSP_HardwareFlowControl_SSE; SSP_Init (MDR_SSP1,&sSSP); /* SSP2 SLAVE configuration ------------------------------------------------*/ sSSP.SSP_SPH = SSP_SPH_1Edge; sSSP.SSP_SPO = SSP_SPO_Low; sSSP.SSP_CPSDVSR = 12; sSSP.SSP_Mode = SSP_ModeSlave; SSP_Init (MDR_SSP2,&sSSP); /* Enable SSP1 DMA Rx and Tx request */ SSP_DMACmd(MDR_SSP1,(SSP_DMA_RXE | SSP_DMA_TXE), ENABLE); /* Enable SSP2 DMA Rx and Tx request */ SSP_DMACmd(MDR_SSP2,(SSP_DMA_RXE | SSP_DMA_TXE), ENABLE); /* Reset all DMA settings */ DMA_DeInit(); DMA_StructInit(&DMA_InitStr); /* DMA_Channel_SSP1_RX configuration ---------------------------------*/ /* Set Primary Control Data */ DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)(&(MDR_SSP1->DR)); DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)DstBuf1; DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncNo; DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncHalfword; DMA_PriCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; DMA_PriCtrlStr.DMA_Mode = DMA_Mode_Basic; DMA_PriCtrlStr.DMA_CycleSize = BufferSize; DMA_PriCtrlStr.DMA_NumContinuous = DMA_Transfers_4; DMA_PriCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged; DMA_PriCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged; /* Set Channel Structure */ DMA_InitStr.DMA_PriCtrlData = &DMA_PriCtrlStr; DMA_InitStr.DMA_Priority = DMA_Priority_High; DMA_InitStr.DMA_UseBurst = DMA_BurstClear; DMA_InitStr.DMA_SelectDataStructure = DMA_CTRL_DATA_PRIMARY; /* Init DMA channel */ DMA_Init(DMA_Channel_SSP1_RX, &DMA_InitStr); /* DMA_Channel_SSP2_RX configuration ---------------------------------*/ /* Set Primary Control Data */ DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)(&(MDR_SSP2->DR)); DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)DstBuf2; /* Init DMA channel */ DMA_Init(DMA_Channel_SSP2_RX, &DMA_InitStr); /* DMA_Channel_SSP1_TX configuration ---------------------------------*/ /* Set Primary Control Data */ DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)SrcBuf1; DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)(&(MDR_SSP1->DR)); DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncHalfword; DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncNo; DMA_InitStr.DMA_Priority = DMA_Priority_Default; /* Init DMA channel */ DMA_Init(DMA_Channel_SSP1_TX, &DMA_InitStr); /* DMA_Channel_SSP2_TX configuration ---------------------------------*/ /* Set Primary Control Data */ DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)SrcBuf2; DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)(&(MDR_SSP2->DR)); /* Init DMA channel */ DMA_Init(DMA_Channel_SSP2_TX, &DMA_InitStr); /* Enable SSP1 */ SSP_Cmd(MDR_SSP1, ENABLE); /* Enable SSP2 */ SSP_Cmd(MDR_SSP2, ENABLE); /* Transfer complete */ while((SSP_GetFlagStatus(MDR_SSP1, SSP_FLAG_BSY))) { } while((SSP_GetFlagStatus(MDR_SSP2, SSP_FLAG_BSY))) { } /* Check the corectness of written dada */ TransferStatus1 = Verif_mem ((BufferSize), SrcBuf1, DstBuf2); TransferStatus2 = Verif_mem ((BufferSize), SrcBuf2, DstBuf1); /* TransferStatus1, TransferStatus2 = PASSED, if the data transmitted and received are correct */ /* TransferStatus1, TransferStatus2 = FAILED, if the data transmitted and received are different */ while(1) { } }
portBASE_TYPE FreeRTOS_SSP_ioctl( Peripheral_Descriptor_t const pxPeripheral, uint32_t ulRequest, void *pvValue ) { Peripheral_Control_t * const pxPeripheralControl = ( Peripheral_Control_t * const ) pxPeripheral; uint32_t ulValue = ( uint32_t ) pvValue, ulInitSSP = pdFALSE; const int8_t cPeripheralNumber = diGET_PERIPHERAL_NUMBER( ( ( Peripheral_Control_t * const ) pxPeripheral ) ); LPC_SSP_TypeDef * pxSSP = ( LPC_SSP_TypeDef * ) diGET_PERIPHERAL_BASE_ADDRESS( ( ( Peripheral_Control_t * const ) pxPeripheral ) ); taskENTER_CRITICAL(); { switch( ulRequest ) { case ioctlUSE_INTERRUPTS : /* Sanity check the array index. */ configASSERT( cPeripheralNumber < ( int8_t ) ( sizeof( xIRQ ) / sizeof( IRQn_Type ) ) ); if( ulValue == pdFALSE ) { NVIC_DisableIRQ( xIRQ[ cPeripheralNumber ] ); } else { /* Enable the Rx interrupts only. New data is sent if an Rx interrupt makes space in the FIFO, so Tx interrupts are not required. */ SSP_IntConfig( LPC_SSP1, SSP_INTCFG_TX, DISABLE ); SSP_IntConfig( pxSSP, sspALL_SSP_RX_INTERRUPTS, ENABLE ); /* Enable the interrupt and set its priority to the minimum interrupt priority. A separate command can be issued to raise the priority if desired. */ NVIC_SetPriority( xIRQ[ cPeripheralNumber ], configSPI_INTERRUPT_PRIORITY ); NVIC_EnableIRQ( xIRQ[ cPeripheralNumber ] ); /* If the Rx is configured to use interrupts, remember the transfer control structure that should be used. A reference to the Tx transfer control structure is taken when a write() operation is actually performed. */ pxRxTransferControlStructs[ cPeripheralNumber ] = pxPeripheralControl->pxRxControl; } break; case ioctlSET_INTERRUPT_PRIORITY : /* The ISR uses ISR safe FreeRTOS API functions, so the priority being set must be lower than (ie numerically larger than) configMAX_LIBRARY_INTERRUPT_PRIORITY. */ configASSERT( ulValue < configMAX_LIBRARY_INTERRUPT_PRIORITY ); NVIC_SetPriority( xIRQ[ cPeripheralNumber ], ulValue ); break; case ioctlSET_SPEED : /* In Hz. */ xSSPConfigurations[ cPeripheralNumber ].ClockRate = ulValue; ulInitSSP = pdTRUE; break; case ioctlSET_SPI_DATA_BITS : /* 4 to 16. */ xSSPConfigurations[ cPeripheralNumber ].Databit = ulValue; ulInitSSP = pdTRUE; break; case ioctlSET_SPI_CLOCK_PHASE : /* SSP_CPHA_FIRST or SSPCPHA_SECOND */ xSSPConfigurations[ cPeripheralNumber ].CPHA = ulValue; ulInitSSP = pdTRUE; break; case ioctlSET_SPI_CLOCK_POLARITY : /* SSP_CPOL_HI or SSP_CPOL_LO. */ xSSPConfigurations[ cPeripheralNumber ].CPOL = ulValue; break; case ioctlSET_SPI_MODE : /* SSP_MASTER_MODE or SSP_SLAVE_MODE. */ xSSPConfigurations[ cPeripheralNumber ].Mode = ulValue; break; case ioctlSET_SSP_FRAME_FORMAT : /* SSP_FRAME_SPI or SSP_FRAME_TI or SSP_FRAME_MICROWIRE. */ xSSPConfigurations[ cPeripheralNumber ].FrameFormat = ulValue; break; } if( ulInitSSP == pdTRUE ) { SSP_Cmd( pxSSP, DISABLE ); SSP_DeInit( pxSSP ); SSP_Init( pxSSP, &( xSSPConfigurations[ cPeripheralNumber ] ) ); SSP_Cmd( pxSSP, ENABLE ); } } taskEXIT_CRITICAL(); return pdPASS; }
/******************************************************************************* * Function Name : main * Description : Main program * Input : None * Output : None * Return : None *******************************************************************************/ int main() { #ifdef DEBUG debug(); #endif SCU_MCLKSourceConfig(SCU_MCLK_OSC); /*Use OSC as the default clock source*/ SCU_PCLKDivisorConfig(SCU_PCLK_Div1); /* ARM Peripheral bus clokdivisor = 1*/ /* SCU configuration */ SCU_Configuration(); /* GPIO pins configuration */ GPIO_Configuration(); /* SSP0 configuration */ SSP_DeInit(SSP0); SSP_InitStructure.SSP_FrameFormat = SSP_FrameFormat_Motorola; SSP_InitStructure.SSP_Mode = SSP_Mode_Master; SSP_InitStructure.SSP_CPOL = SSP_CPOL_High; SSP_InitStructure.SSP_CPHA = SSP_CPHA_2Edge; SSP_InitStructure.SSP_DataSize = SSP_DataSize_8b; SSP_InitStructure.SSP_ClockRate = 5; SSP_InitStructure.SSP_ClockPrescaler = 2; SSP_Init(SSP0, &SSP_InitStructure); /* SSP1 configuration */ SSP_DeInit(SSP1); SSP_InitStructure.SSP_Mode = SSP_Mode_Slave; SSP_InitStructure.SSP_SlaveOutput = SSP_SlaveOutput_Enable; SSP_Init(SSP1, &SSP_InitStructure); /* SSP0 enable */ SSP_Cmd(SSP0, ENABLE); /* SSP1 enable */ SSP_Cmd(SSP1, ENABLE); /* Master to slave transfer procedure */ while(Tx_Idx<32) { SSP_SendData(SSP0, SSP0_Buffer_Tx[Tx_Idx++]); while(SSP_GetFlagStatus(SSP1, SSP_FLAG_RxFifoNotEmpty)==RESET); SSP1_Buffer_Rx[Rx_Idx++] = SSP_ReceiveData(SSP1); } /* Check the received data with the send ones */ TransferStatus1 = Buffercmp(SSP0_Buffer_Tx, SSP1_Buffer_Rx, 32); /* TransferStatus = PASSED, if the data transmitted from SSP0 and received by SSP1 are the same */ /* TransferStatus = FAILED, if the data transmitted from SSP0 and received by SSP1 are different */ /* Clear SSP0 receive Fifo */ for(k=0; k<8; k++) SSP0_Buffer_Rx[k] = SSP_ReceiveData(SSP0); /* Reset counters */ Tx_Idx=Rx_Idx=0; /* Slave to master transfer procedure */ while(Tx_Idx<32) { SSP_SendData(SSP1, SSP1_Buffer_Tx[Tx_Idx]); /* send a dummy bit to generate the clock */ SSP_SendData(SSP0, SSP0_Buffer_Tx[Tx_Idx++]); while(SSP_GetFlagStatus(SSP0, SSP_FLAG_RxFifoNotEmpty)==RESET); SSP0_Buffer_Rx[Rx_Idx++] = SSP_ReceiveData(SSP0); } /* Check the received data with the send ones */ TransferStatus2 = Buffercmp(SSP1_Buffer_Tx, SSP0_Buffer_Rx, 32); /* TransferStatus = PASSED, if the data transmitted from SSP1 and received by SSP0 are the same */ /* TransferStatus = FAILED, if the data transmitted from SSP1 and received by SSP0 are different */ while(1); }