/* Set stencil unit to replace always with the reference value.
*/
static void set_stencil_replace( i830ContextPtr i830,
GLuint s_mask,
GLuint s_clear)
{
/* ctx->Driver.Enable( ctx, GL_STENCIL_TEST, GL_TRUE )
*/
i830->meta.Ctx[I830_CTXREG_ENABLES_1] |= ENABLE_STENCIL_TEST;
i830->meta.Ctx[I830_CTXREG_ENABLES_2] |= ENABLE_STENCIL_WRITE;
/* ctx->Driver.Enable( ctx, GL_DEPTH_TEST, GL_FALSE )
*/
i830->meta.Ctx[I830_CTXREG_ENABLES_1] &= ~ENABLE_DIS_DEPTH_TEST_MASK;
i830->meta.Ctx[I830_CTXREG_ENABLES_2] &= ~ENABLE_DIS_DEPTH_WRITE_MASK;
i830->meta.Ctx[I830_CTXREG_ENABLES_1] |= DISABLE_DEPTH_TEST;
i830->meta.Ctx[I830_CTXREG_ENABLES_2] |= DISABLE_DEPTH_WRITE;
/* ctx->Driver.StencilMask( ctx, s_mask )
*/
i830->meta.Ctx[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_WRITE_MASK;
i830->meta.Ctx[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_WRITE_MASK |
STENCIL_WRITE_MASK((s_mask&0xff)));
/* ctx->Driver.StencilOp( ctx, GL_REPLACE, GL_REPLACE, GL_REPLACE )
*/
i830->meta.Ctx[I830_CTXREG_STENCILTST] &= ~(STENCIL_OPS_MASK);
i830->meta.Ctx[I830_CTXREG_STENCILTST] |=
(ENABLE_STENCIL_PARMS |
STENCIL_FAIL_OP(STENCILOP_REPLACE) |
STENCIL_PASS_DEPTH_FAIL_OP(STENCILOP_REPLACE) |
STENCIL_PASS_DEPTH_PASS_OP(STENCILOP_REPLACE));
/* ctx->Driver.StencilFunc( ctx, GL_ALWAYS, s_clear, ~0 )
*/
i830->meta.Ctx[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_TEST_MASK;
i830->meta.Ctx[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK |
STENCIL_TEST_MASK(0xff));
i830->meta.Ctx[I830_CTXREG_STENCILTST] &= ~(STENCIL_REF_VALUE_MASK |
ENABLE_STENCIL_TEST_FUNC_MASK);
i830->meta.Ctx[I830_CTXREG_STENCILTST] |=
(ENABLE_STENCIL_REF_VALUE |
ENABLE_STENCIL_TEST_FUNC |
STENCIL_REF_VALUE((s_clear&0xff)) |
STENCIL_TEST_FUNC(COMPAREFUNC_ALWAYS));
i830->meta.emitted &= ~I830_UPLOAD_CTX;
}
static void i830ClearWithTris(GLcontext *ctx, GLbitfield mask,
GLboolean all,
GLint cx, GLint cy, GLint cw, GLint ch)
{
i830ContextPtr imesa = I830_CONTEXT( ctx );
__DRIdrawablePrivate *dPriv = imesa->driDrawable;
i830ScreenPrivate *i830Screen = imesa->i830Screen;
I830SAREAPtr sarea = imesa->sarea;
GLuint old_vertex_prim;
GLuint old_dirty;
int x0, y0, x1, y1;
if (I830_DEBUG & DEBUG_IOCTL)
fprintf(stderr, "Clearing with triangles\n");
old_dirty = imesa->dirty & ~I830_UPLOAD_CLIPRECTS;
/* Discard all the dirty flags except the cliprect one, reset later */
imesa->dirty &= I830_UPLOAD_CLIPRECTS;
if(!all) {
x0 = cx;
y0 = cy;
x1 = x0 + cw;
y1 = y0 + ch;
} else {
x0 = 0;
y0 = 0;
x1 = x0 + dPriv->w;
y1 = y0 + dPriv->h;
}
/* Clip to Screen */
if (x0 < 0) x0 = 0;
if (y0 < 0) y0 = 0;
if (x1 > i830Screen->width-1) x1 = i830Screen->width-1;
if (y1 > i830Screen->height-1) y1 = i830Screen->height-1;
LOCK_HARDWARE(imesa);
memcpy(sarea->ContextState,
imesa->Init_Setup,
sizeof(imesa->Setup) );
memcpy(sarea->BufferState,
imesa->BufferSetup,
sizeof(imesa->BufferSetup) );
sarea->StippleState[I830_STPREG_ST1] = 0;
old_vertex_prim = imesa->hw_primitive;
imesa->hw_primitive = PRIM3D_TRIFAN;
if(mask & DD_FRONT_LEFT_BIT) {
GLuint tmp = sarea->ContextState[I830_CTXREG_ENABLES_2];
sarea->dirty |= (I830_UPLOAD_CTX | I830_UPLOAD_BUFFERS |
I830_UPLOAD_TEXBLEND0);
sarea->TexBlendState[0][0] = (STATE3D_MAP_BLEND_OP_CMD(0) |
TEXPIPE_COLOR |
ENABLE_TEXOUTPUT_WRT_SEL |
TEXOP_OUTPUT_CURRENT |
DISABLE_TEX_CNTRL_STAGE |
TEXOP_SCALE_1X |
TEXOP_MODIFY_PARMS |
TEXOP_LAST_STAGE |
TEXBLENDOP_ARG1);
sarea->TexBlendState[0][1] = (STATE3D_MAP_BLEND_OP_CMD(0) |
TEXPIPE_ALPHA |
ENABLE_TEXOUTPUT_WRT_SEL |
TEXOP_OUTPUT_CURRENT |
TEXOP_SCALE_1X |
TEXOP_MODIFY_PARMS |
TEXBLENDOP_ARG1);
sarea->TexBlendState[0][2] = (STATE3D_MAP_BLEND_ARG_CMD(0) |
TEXPIPE_COLOR |
TEXBLEND_ARG1 |
TEXBLENDARG_MODIFY_PARMS |
TEXBLENDARG_CURRENT);
sarea->TexBlendState[0][3] = (STATE3D_MAP_BLEND_ARG_CMD(0) |
TEXPIPE_ALPHA |
TEXBLEND_ARG1 |
TEXBLENDARG_MODIFY_PARMS |
TEXBLENDARG_CURRENT);
sarea->TexBlendStateWordsUsed[0] = 4;
tmp &= ~(ENABLE_STENCIL_WRITE | ENABLE_DEPTH_WRITE);
tmp |= (DISABLE_STENCIL_WRITE |
DISABLE_DEPTH_WRITE |
(imesa->mask_red << WRITEMASK_RED_SHIFT) |
(imesa->mask_green << WRITEMASK_GREEN_SHIFT) |
(imesa->mask_blue << WRITEMASK_BLUE_SHIFT) |
(imesa->mask_alpha << WRITEMASK_ALPHA_SHIFT));
sarea->ContextState[I830_CTXREG_ENABLES_2] = tmp;
if(0)
fprintf(stderr, "fcdq : r_mask(%d) g_mask(%d) b_mask(%d) a_mask(%d)\n",
imesa->mask_red, imesa->mask_green, imesa->mask_blue,
imesa->mask_alpha);
sarea->BufferState[I830_DESTREG_CBUFADDR] = i830Screen->fbOffset;
if(0)
fprintf(stderr, "fcdq : x0(%d) x1(%d) y0(%d) y1(%d)\n"
"r(0x%x) g(0x%x) b(0x%x) a(0x%x)\n",
x0, x1, y0, y1, imesa->clear_red, imesa->clear_green,
imesa->clear_blue, imesa->clear_alpha);
i830ClearDrawQuad(imesa, (float)x0, (float)x1, (float)y0, (float)y1,
imesa->clear_red, imesa->clear_green,
imesa->clear_blue, imesa->clear_alpha);
i830FlushPrimsLocked( imesa );
}
if(mask & DD_BACK_LEFT_BIT) {
GLuint tmp = sarea->ContextState[I830_CTXREG_ENABLES_2];
sarea->dirty |= (I830_UPLOAD_CTX | I830_UPLOAD_BUFFERS |
I830_UPLOAD_TEXBLEND0);
sarea->TexBlendState[0][0] = (STATE3D_MAP_BLEND_OP_CMD(0) |
TEXPIPE_COLOR |
ENABLE_TEXOUTPUT_WRT_SEL |
TEXOP_OUTPUT_CURRENT |
DISABLE_TEX_CNTRL_STAGE |
TEXOP_SCALE_1X |
TEXOP_MODIFY_PARMS |
TEXOP_LAST_STAGE |
TEXBLENDOP_ARG1);
sarea->TexBlendState[0][1] = (STATE3D_MAP_BLEND_OP_CMD(0) |
TEXPIPE_ALPHA |
ENABLE_TEXOUTPUT_WRT_SEL |
TEXOP_OUTPUT_CURRENT |
TEXOP_SCALE_1X |
TEXOP_MODIFY_PARMS |
TEXBLENDOP_ARG1);
sarea->TexBlendState[0][2] = (STATE3D_MAP_BLEND_ARG_CMD(0) |
TEXPIPE_COLOR |
TEXBLEND_ARG1 |
TEXBLENDARG_MODIFY_PARMS |
TEXBLENDARG_CURRENT);
sarea->TexBlendState[0][3] = (STATE3D_MAP_BLEND_ARG_CMD(0) |
TEXPIPE_ALPHA |
TEXBLEND_ARG2 |
TEXBLENDARG_MODIFY_PARMS |
TEXBLENDARG_CURRENT);
sarea->TexBlendStateWordsUsed[0] = 4;
tmp &= ~(ENABLE_STENCIL_WRITE | ENABLE_DEPTH_WRITE);
tmp |= (DISABLE_STENCIL_WRITE |
DISABLE_DEPTH_WRITE |
(imesa->mask_red << WRITEMASK_RED_SHIFT) |
(imesa->mask_green << WRITEMASK_GREEN_SHIFT) |
(imesa->mask_blue << WRITEMASK_BLUE_SHIFT) |
(imesa->mask_alpha << WRITEMASK_ALPHA_SHIFT));
if(0)
fprintf(stderr, "bcdq : r_mask(%d) g_mask(%d) b_mask(%d) a_mask(%d)\n",
imesa->mask_red, imesa->mask_green, imesa->mask_blue,
imesa->mask_alpha);
sarea->ContextState[I830_CTXREG_ENABLES_2] = tmp;
sarea->BufferState[I830_DESTREG_CBUFADDR] = i830Screen->backOffset;
if(0)
fprintf(stderr, "bcdq : x0(%d) x1(%d) y0(%d) y1(%d)\n"
"r(0x%x) g(0x%x) b(0x%x) a(0x%x)\n",
x0, x1, y0, y1, imesa->clear_red, imesa->clear_green,
imesa->clear_blue, imesa->clear_alpha);
i830ClearDrawQuad(imesa, (float)x0, (float)x1, (float)y0, (float)y1,
imesa->clear_red, imesa->clear_green,
imesa->clear_blue, imesa->clear_alpha);
i830FlushPrimsLocked( imesa );
}
if(mask & DD_STENCIL_BIT) {
GLuint s_mask = ctx->Stencil.WriteMask;
sarea->dirty |= (I830_UPLOAD_CTX | I830_UPLOAD_BUFFERS |
I830_UPLOAD_TEXBLEND0);
sarea->TexBlendState[0][0] = (STATE3D_MAP_BLEND_OP_CMD(0) |
TEXPIPE_COLOR |
ENABLE_TEXOUTPUT_WRT_SEL |
TEXOP_OUTPUT_CURRENT |
DISABLE_TEX_CNTRL_STAGE |
TEXOP_SCALE_1X |
TEXOP_MODIFY_PARMS |
TEXOP_LAST_STAGE |
TEXBLENDOP_ARG1);
sarea->TexBlendState[0][1] = (STATE3D_MAP_BLEND_OP_CMD(0) |
TEXPIPE_ALPHA |
ENABLE_TEXOUTPUT_WRT_SEL |
TEXOP_OUTPUT_CURRENT |
TEXOP_SCALE_1X |
TEXOP_MODIFY_PARMS |
TEXBLENDOP_ARG1);
sarea->TexBlendState[0][2] = (STATE3D_MAP_BLEND_ARG_CMD(0) |
TEXPIPE_COLOR |
TEXBLEND_ARG1 |
TEXBLENDARG_MODIFY_PARMS |
TEXBLENDARG_CURRENT);
sarea->TexBlendState[0][3] = (STATE3D_MAP_BLEND_ARG_CMD(0) |
TEXPIPE_ALPHA |
TEXBLEND_ARG2 |
TEXBLENDARG_MODIFY_PARMS |
TEXBLENDARG_CURRENT);
sarea->TexBlendStateWordsUsed[0] = 4;
sarea->ContextState[I830_CTXREG_ENABLES_1] |= (ENABLE_STENCIL_TEST |
ENABLE_DEPTH_TEST);
sarea->ContextState[I830_CTXREG_ENABLES_2] &= ~(ENABLE_STENCIL_WRITE |
ENABLE_DEPTH_WRITE |
ENABLE_COLOR_WRITE);
sarea->ContextState[I830_CTXREG_ENABLES_2] |= (ENABLE_STENCIL_WRITE |
DISABLE_DEPTH_WRITE |
(1 << WRITEMASK_RED_SHIFT) |
(1 << WRITEMASK_GREEN_SHIFT) |
(1 << WRITEMASK_BLUE_SHIFT) |
(1 << WRITEMASK_ALPHA_SHIFT) |
ENABLE_COLOR_WRITE);
sarea->ContextState[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_MASK;
sarea->ContextState[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK |
ENABLE_STENCIL_WRITE_MASK |
STENCIL_TEST_MASK(s_mask) |
STENCIL_WRITE_MASK(s_mask));
sarea->ContextState[I830_CTXREG_STENCILTST] &= ~(STENCIL_OPS_MASK |
STENCIL_REF_VALUE_MASK |
ENABLE_STENCIL_TEST_FUNC_MASK);
sarea->ContextState[I830_CTXREG_STENCILTST] |= (ENABLE_STENCIL_PARMS |
ENABLE_STENCIL_REF_VALUE |
ENABLE_STENCIL_TEST_FUNC |
STENCIL_FAIL_OP(STENCILOP_REPLACE) |
STENCIL_PASS_DEPTH_FAIL_OP(STENCILOP_REPLACE) |
STENCIL_PASS_DEPTH_PASS_OP(STENCILOP_REPLACE) |
STENCIL_REF_VALUE((ctx->Stencil.Clear & 0xff)) |
STENCIL_TEST_FUNC(COMPAREFUNC_ALWAYS));
if(0)
fprintf(stderr, "Enables_1 (0x%x) Enables_2 (0x%x) StenTst (0x%x)\n"
"Modes_4 (0x%x)\n",
sarea->ContextState[I830_CTXREG_ENABLES_1],
sarea->ContextState[I830_CTXREG_ENABLES_2],
sarea->ContextState[I830_CTXREG_STENCILTST],
sarea->ContextState[I830_CTXREG_STATE4]);
sarea->BufferState[I830_DESTREG_CBUFADDR] = i830Screen->fbOffset;
i830ClearDrawQuad(imesa, (float)x0, (float)x1, (float)y0, (float)y1,
255, 255, 255, 255);
i830FlushPrimsLocked( imesa );
}
UNLOCK_HARDWARE(imesa);
imesa->dirty = old_dirty;
imesa->dirty |= (I830_UPLOAD_CTX |
I830_UPLOAD_BUFFERS |
I830_UPLOAD_TEXBLEND0);
imesa->hw_primitive = old_vertex_prim;
}
static void
i830StencilOpSeparate(struct gl_context * ctx, GLenum face, GLenum fail, GLenum zfail,
GLenum zpass)
{
struct i830_context *i830 = i830_context(ctx);
int fop, dfop, dpop;
DBG("%s: fail : %s, zfail: %s, zpass : %s\n", __FUNCTION__,
_mesa_lookup_enum_by_nr(fail),
_mesa_lookup_enum_by_nr(zfail),
_mesa_lookup_enum_by_nr(zpass));
fop = 0;
dfop = 0;
dpop = 0;
switch (fail) {
case GL_KEEP:
fop = STENCILOP_KEEP;
break;
case GL_ZERO:
fop = STENCILOP_ZERO;
break;
case GL_REPLACE:
fop = STENCILOP_REPLACE;
break;
case GL_INCR:
fop = STENCILOP_INCRSAT;
break;
case GL_DECR:
fop = STENCILOP_DECRSAT;
break;
case GL_INCR_WRAP:
fop = STENCILOP_INCR;
break;
case GL_DECR_WRAP:
fop = STENCILOP_DECR;
break;
case GL_INVERT:
fop = STENCILOP_INVERT;
break;
default:
break;
}
switch (zfail) {
case GL_KEEP:
dfop = STENCILOP_KEEP;
break;
case GL_ZERO:
dfop = STENCILOP_ZERO;
break;
case GL_REPLACE:
dfop = STENCILOP_REPLACE;
break;
case GL_INCR:
dfop = STENCILOP_INCRSAT;
break;
case GL_DECR:
dfop = STENCILOP_DECRSAT;
break;
case GL_INCR_WRAP:
dfop = STENCILOP_INCR;
break;
case GL_DECR_WRAP:
dfop = STENCILOP_DECR;
break;
case GL_INVERT:
dfop = STENCILOP_INVERT;
break;
default:
break;
}
switch (zpass) {
case GL_KEEP:
dpop = STENCILOP_KEEP;
break;
case GL_ZERO:
dpop = STENCILOP_ZERO;
break;
case GL_REPLACE:
dpop = STENCILOP_REPLACE;
break;
case GL_INCR:
dpop = STENCILOP_INCRSAT;
break;
case GL_DECR:
dpop = STENCILOP_DECRSAT;
break;
case GL_INCR_WRAP:
dpop = STENCILOP_INCR;
break;
case GL_DECR_WRAP:
dpop = STENCILOP_DECR;
break;
case GL_INVERT:
dpop = STENCILOP_INVERT;
break;
default:
break;
}
I830_STATECHANGE(i830, I830_UPLOAD_CTX);
i830->state.Ctx[I830_CTXREG_STENCILTST] &= ~(STENCIL_OPS_MASK);
i830->state.Ctx[I830_CTXREG_STENCILTST] |= (ENABLE_STENCIL_PARMS |
STENCIL_FAIL_OP(fop) |
STENCIL_PASS_DEPTH_FAIL_OP
(dfop) |
STENCIL_PASS_DEPTH_PASS_OP
(dpop));
}
static void
i830_init_packets(struct i830_context *i830)
{
/* Zero all state */
memset(&i830->state, 0, sizeof(i830->state));
/* Set default blend state */
i830->state.TexBlend[0][0] = (_3DSTATE_MAP_BLEND_OP_CMD(0) |
TEXPIPE_COLOR |
ENABLE_TEXOUTPUT_WRT_SEL |
TEXOP_OUTPUT_CURRENT |
DISABLE_TEX_CNTRL_STAGE |
TEXOP_SCALE_1X |
TEXOP_MODIFY_PARMS |
TEXOP_LAST_STAGE | TEXBLENDOP_ARG1);
i830->state.TexBlend[0][1] = (_3DSTATE_MAP_BLEND_OP_CMD(0) |
TEXPIPE_ALPHA |
ENABLE_TEXOUTPUT_WRT_SEL |
TEXOP_OUTPUT_CURRENT |
TEXOP_SCALE_1X |
TEXOP_MODIFY_PARMS | TEXBLENDOP_ARG1);
i830->state.TexBlend[0][2] = (_3DSTATE_MAP_BLEND_ARG_CMD(0) |
TEXPIPE_COLOR |
TEXBLEND_ARG1 |
TEXBLENDARG_MODIFY_PARMS |
TEXBLENDARG_DIFFUSE);
i830->state.TexBlend[0][3] = (_3DSTATE_MAP_BLEND_ARG_CMD(0) |
TEXPIPE_ALPHA |
TEXBLEND_ARG1 |
TEXBLENDARG_MODIFY_PARMS |
TEXBLENDARG_DIFFUSE);
i830->state.TexBlendWordsUsed[0] = 4;
i830->state.Ctx[I830_CTXREG_VF] = 0;
i830->state.Ctx[I830_CTXREG_VF2] = 0;
i830->state.Ctx[I830_CTXREG_AA] = (_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE |
AA_LINE_REGION_WIDTH_1_0 |
AA_LINE_DISABLE);
i830->state.Ctx[I830_CTXREG_ENABLES_1] = (_3DSTATE_ENABLES_1_CMD |
DISABLE_LOGIC_OP |
DISABLE_STENCIL_TEST |
DISABLE_DEPTH_BIAS |
DISABLE_SPEC_ADD |
DISABLE_FOG |
DISABLE_ALPHA_TEST |
DISABLE_COLOR_BLEND |
DISABLE_DEPTH_TEST);
#if 000 /* XXX all the stencil enable state is set in i830Enable(), right? */
if (i830->intel.hw_stencil) {
i830->state.Ctx[I830_CTXREG_ENABLES_2] = (_3DSTATE_ENABLES_2_CMD |
ENABLE_STENCIL_WRITE |
ENABLE_TEX_CACHE |
ENABLE_DITHER |
ENABLE_COLOR_MASK |
/* set no color comps disabled */
ENABLE_COLOR_WRITE |
ENABLE_DEPTH_WRITE);
}
else
#endif
{
i830->state.Ctx[I830_CTXREG_ENABLES_2] = (_3DSTATE_ENABLES_2_CMD |
DISABLE_STENCIL_WRITE |
ENABLE_TEX_CACHE |
ENABLE_DITHER |
ENABLE_COLOR_MASK |
/* set no color comps disabled */
ENABLE_COLOR_WRITE |
ENABLE_DEPTH_WRITE);
}
i830->state.Ctx[I830_CTXREG_STATE1] = (_3DSTATE_MODES_1_CMD |
ENABLE_COLR_BLND_FUNC |
BLENDFUNC_ADD |
ENABLE_SRC_BLND_FACTOR |
SRC_BLND_FACT(BLENDFACT_ONE) |
ENABLE_DST_BLND_FACTOR |
DST_BLND_FACT(BLENDFACT_ZERO));
i830->state.Ctx[I830_CTXREG_STATE2] = (_3DSTATE_MODES_2_CMD |
ENABLE_GLOBAL_DEPTH_BIAS |
GLOBAL_DEPTH_BIAS(0) |
ENABLE_ALPHA_TEST_FUNC |
ALPHA_TEST_FUNC(COMPAREFUNC_ALWAYS)
| ALPHA_REF_VALUE(0));
i830->state.Ctx[I830_CTXREG_STATE3] = (_3DSTATE_MODES_3_CMD |
ENABLE_DEPTH_TEST_FUNC |
DEPTH_TEST_FUNC(COMPAREFUNC_LESS) |
ENABLE_ALPHA_SHADE_MODE |
ALPHA_SHADE_MODE(SHADE_MODE_LINEAR)
| ENABLE_FOG_SHADE_MODE |
FOG_SHADE_MODE(SHADE_MODE_LINEAR) |
ENABLE_SPEC_SHADE_MODE |
SPEC_SHADE_MODE(SHADE_MODE_LINEAR) |
ENABLE_COLOR_SHADE_MODE |
COLOR_SHADE_MODE(SHADE_MODE_LINEAR)
| ENABLE_CULL_MODE | CULLMODE_NONE);
i830->state.Ctx[I830_CTXREG_STATE4] = (_3DSTATE_MODES_4_CMD |
ENABLE_LOGIC_OP_FUNC |
LOGIC_OP_FUNC(LOGICOP_COPY) |
ENABLE_STENCIL_TEST_MASK |
STENCIL_TEST_MASK(0xff) |
ENABLE_STENCIL_WRITE_MASK |
STENCIL_WRITE_MASK(0xff));
i830->state.Ctx[I830_CTXREG_STENCILTST] = (_3DSTATE_STENCIL_TEST_CMD |
ENABLE_STENCIL_PARMS |
STENCIL_FAIL_OP(STENCILOP_KEEP)
|
STENCIL_PASS_DEPTH_FAIL_OP
(STENCILOP_KEEP) |
STENCIL_PASS_DEPTH_PASS_OP
(STENCILOP_KEEP) |
ENABLE_STENCIL_TEST_FUNC |
STENCIL_TEST_FUNC
(COMPAREFUNC_ALWAYS) |
ENABLE_STENCIL_REF_VALUE |
STENCIL_REF_VALUE(0));
i830->state.Ctx[I830_CTXREG_STATE5] = (_3DSTATE_MODES_5_CMD | FLUSH_TEXTURE_CACHE | ENABLE_SPRITE_POINT_TEX | SPRITE_POINT_TEX_OFF | ENABLE_FIXED_LINE_WIDTH | FIXED_LINE_WIDTH(0x2) | /* 1.0 */
ENABLE_FIXED_POINT_WIDTH |
FIXED_POINT_WIDTH(1));
i830->state.Ctx[I830_CTXREG_IALPHAB] = (_3DSTATE_INDPT_ALPHA_BLEND_CMD |
DISABLE_INDPT_ALPHA_BLEND |
ENABLE_ALPHA_BLENDFUNC |
ABLENDFUNC_ADD);
i830->state.Ctx[I830_CTXREG_FOGCOLOR] = (_3DSTATE_FOG_COLOR_CMD |
FOG_COLOR_RED(0) |
FOG_COLOR_GREEN(0) |
FOG_COLOR_BLUE(0));
i830->state.Ctx[I830_CTXREG_BLENDCOLOR0] = _3DSTATE_CONST_BLEND_COLOR_CMD;
i830->state.Ctx[I830_CTXREG_BLENDCOLOR1] = 0;
i830->state.Ctx[I830_CTXREG_MCSB0] = _3DSTATE_MAP_COORD_SETBIND_CMD;
i830->state.Ctx[I830_CTXREG_MCSB1] = (TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) |
TEXBIND_SET2(TEXCOORDSRC_VTXSET_2) |
TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) |
TEXBIND_SET0(TEXCOORDSRC_VTXSET_0));
i830->state.RasterRules[I830_RASTER_RULES] = (_3DSTATE_RASTER_RULES_CMD |
ENABLE_POINT_RASTER_RULE |
OGL_POINT_RASTER_RULE |
ENABLE_LINE_STRIP_PROVOKE_VRTX |
ENABLE_TRI_FAN_PROVOKE_VRTX |
ENABLE_TRI_STRIP_PROVOKE_VRTX |
LINE_STRIP_PROVOKE_VRTX(1) |
TRI_FAN_PROVOKE_VRTX(2) |
TRI_STRIP_PROVOKE_VRTX(2));
i830->state.Stipple[I830_STPREG_ST0] = _3DSTATE_STIPPLE;
i830->state.Buffer[I830_DESTREG_DV0] = _3DSTATE_DST_BUF_VARS_CMD;
i830->state.Buffer[I830_DESTREG_SENABLE] = (_3DSTATE_SCISSOR_ENABLE_CMD |
DISABLE_SCISSOR_RECT);
i830->state.Buffer[I830_DESTREG_SR0] = _3DSTATE_SCISSOR_RECT_0_CMD;
i830->state.Buffer[I830_DESTREG_SR1] = 0;
i830->state.Buffer[I830_DESTREG_SR2] = 0;
}
static void i830_init_packets( i830ContextPtr i830 )
{
intelScreenPrivate *screen = i830->intel.intelScreen;
/* Zero all state */
memset(&i830->state, 0, sizeof(i830->state));
/* Set default blend state */
i830->state.TexBlend[0][0] = (_3DSTATE_MAP_BLEND_OP_CMD(0) |
TEXPIPE_COLOR |
ENABLE_TEXOUTPUT_WRT_SEL |
TEXOP_OUTPUT_CURRENT |
DISABLE_TEX_CNTRL_STAGE |
TEXOP_SCALE_1X |
TEXOP_MODIFY_PARMS |
TEXOP_LAST_STAGE |
TEXBLENDOP_ARG1);
i830->state.TexBlend[0][1] = (_3DSTATE_MAP_BLEND_OP_CMD(0) |
TEXPIPE_ALPHA |
ENABLE_TEXOUTPUT_WRT_SEL |
TEXOP_OUTPUT_CURRENT |
TEXOP_SCALE_1X |
TEXOP_MODIFY_PARMS |
TEXBLENDOP_ARG1);
i830->state.TexBlend[0][2] = (_3DSTATE_MAP_BLEND_ARG_CMD(0) |
TEXPIPE_COLOR |
TEXBLEND_ARG1 |
TEXBLENDARG_MODIFY_PARMS |
TEXBLENDARG_DIFFUSE);
i830->state.TexBlend[0][3] = (_3DSTATE_MAP_BLEND_ARG_CMD(0) |
TEXPIPE_ALPHA |
TEXBLEND_ARG1 |
TEXBLENDARG_MODIFY_PARMS |
TEXBLENDARG_DIFFUSE);
i830->state.TexBlendWordsUsed[0] = 4;
i830->state.Ctx[I830_CTXREG_VF] = 0;
i830->state.Ctx[I830_CTXREG_VF2] = 0;
i830->state.Ctx[I830_CTXREG_AA] = (_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE |
AA_LINE_REGION_WIDTH_1_0 |
AA_LINE_DISABLE);
i830->state.Ctx[I830_CTXREG_ENABLES_1] = (_3DSTATE_ENABLES_1_CMD |
DISABLE_LOGIC_OP |
DISABLE_STENCIL_TEST |
DISABLE_DEPTH_BIAS |
DISABLE_SPEC_ADD |
DISABLE_FOG |
DISABLE_ALPHA_TEST |
DISABLE_COLOR_BLEND |
DISABLE_DEPTH_TEST);
if (i830->intel.hw_stencil) {
i830->state.Ctx[I830_CTXREG_ENABLES_2] = (_3DSTATE_ENABLES_2_CMD |
ENABLE_STENCIL_WRITE |
ENABLE_TEX_CACHE |
ENABLE_DITHER |
ENABLE_COLOR_MASK |
/* set no color comps disabled */
ENABLE_COLOR_WRITE |
ENABLE_DEPTH_WRITE);
} else {
i830->state.Ctx[I830_CTXREG_ENABLES_2] = (_3DSTATE_ENABLES_2_CMD |
DISABLE_STENCIL_WRITE |
ENABLE_TEX_CACHE |
ENABLE_DITHER |
ENABLE_COLOR_MASK |
/* set no color comps disabled */
ENABLE_COLOR_WRITE |
ENABLE_DEPTH_WRITE);
}
i830->state.Ctx[I830_CTXREG_STATE1] = (_3DSTATE_MODES_1_CMD |
ENABLE_COLR_BLND_FUNC |
BLENDFUNC_ADD |
ENABLE_SRC_BLND_FACTOR |
SRC_BLND_FACT(BLENDFACT_ONE) |
ENABLE_DST_BLND_FACTOR |
DST_BLND_FACT(BLENDFACT_ZERO) );
i830->state.Ctx[I830_CTXREG_STATE2] = (_3DSTATE_MODES_2_CMD |
ENABLE_GLOBAL_DEPTH_BIAS |
GLOBAL_DEPTH_BIAS(0) |
ENABLE_ALPHA_TEST_FUNC |
ALPHA_TEST_FUNC(COMPAREFUNC_ALWAYS) |
ALPHA_REF_VALUE(0) );
i830->state.Ctx[I830_CTXREG_STATE3] = (_3DSTATE_MODES_3_CMD |
ENABLE_DEPTH_TEST_FUNC |
DEPTH_TEST_FUNC(COMPAREFUNC_LESS) |
ENABLE_ALPHA_SHADE_MODE |
ALPHA_SHADE_MODE(SHADE_MODE_LINEAR) |
ENABLE_FOG_SHADE_MODE |
FOG_SHADE_MODE(SHADE_MODE_LINEAR) |
ENABLE_SPEC_SHADE_MODE |
SPEC_SHADE_MODE(SHADE_MODE_LINEAR) |
ENABLE_COLOR_SHADE_MODE |
COLOR_SHADE_MODE(SHADE_MODE_LINEAR) |
ENABLE_CULL_MODE |
CULLMODE_NONE);
i830->state.Ctx[I830_CTXREG_STATE4] = (_3DSTATE_MODES_4_CMD |
ENABLE_LOGIC_OP_FUNC |
LOGIC_OP_FUNC(LOGICOP_COPY) |
ENABLE_STENCIL_TEST_MASK |
STENCIL_TEST_MASK(0xff) |
ENABLE_STENCIL_WRITE_MASK |
STENCIL_WRITE_MASK(0xff));
i830->state.Ctx[I830_CTXREG_STENCILTST] = (_3DSTATE_STENCIL_TEST_CMD |
ENABLE_STENCIL_PARMS |
STENCIL_FAIL_OP(STENCILOP_KEEP) |
STENCIL_PASS_DEPTH_FAIL_OP(STENCILOP_KEEP) |
STENCIL_PASS_DEPTH_PASS_OP(STENCILOP_KEEP) |
ENABLE_STENCIL_TEST_FUNC |
STENCIL_TEST_FUNC(COMPAREFUNC_ALWAYS) |
ENABLE_STENCIL_REF_VALUE |
STENCIL_REF_VALUE(0) );
i830->state.Ctx[I830_CTXREG_STATE5] = (_3DSTATE_MODES_5_CMD |
FLUSH_TEXTURE_CACHE |
ENABLE_SPRITE_POINT_TEX |
SPRITE_POINT_TEX_OFF |
ENABLE_FIXED_LINE_WIDTH |
FIXED_LINE_WIDTH(0x2) | /* 1.0 */
ENABLE_FIXED_POINT_WIDTH |
FIXED_POINT_WIDTH(1) );
i830->state.Ctx[I830_CTXREG_IALPHAB] = (_3DSTATE_INDPT_ALPHA_BLEND_CMD |
DISABLE_INDPT_ALPHA_BLEND |
ENABLE_ALPHA_BLENDFUNC |
ABLENDFUNC_ADD);
i830->state.Ctx[I830_CTXREG_FOGCOLOR] = (_3DSTATE_FOG_COLOR_CMD |
FOG_COLOR_RED(0) |
FOG_COLOR_GREEN(0) |
FOG_COLOR_BLUE(0));
i830->state.Ctx[I830_CTXREG_BLENDCOLOR0] = _3DSTATE_CONST_BLEND_COLOR_CMD;
i830->state.Ctx[I830_CTXREG_BLENDCOLOR1] = 0;
i830->state.Ctx[I830_CTXREG_MCSB0] = _3DSTATE_MAP_COORD_SETBIND_CMD;
i830->state.Ctx[I830_CTXREG_MCSB1] = (TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) |
TEXBIND_SET2(TEXCOORDSRC_VTXSET_2) |
TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) |
TEXBIND_SET0(TEXCOORDSRC_VTXSET_0));
i830->state.Stipple[I830_STPREG_ST0] = _3DSTATE_STIPPLE;
i830->state.Buffer[I830_DESTREG_CBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
i830->state.Buffer[I830_DESTREG_CBUFADDR1] =
(BUF_3D_ID_COLOR_BACK |
BUF_3D_PITCH(screen->front.pitch) | /* pitch in bytes */
BUF_3D_USE_FENCE);
i830->state.Buffer[I830_DESTREG_DBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
i830->state.Buffer[I830_DESTREG_DBUFADDR1] =
(BUF_3D_ID_DEPTH |
BUF_3D_PITCH(screen->depth.pitch) | /* pitch in bytes */
BUF_3D_USE_FENCE);
i830->state.Buffer[I830_DESTREG_DBUFADDR2] = screen->depth.offset;
i830->state.Buffer[I830_DESTREG_DV0] = _3DSTATE_DST_BUF_VARS_CMD;
switch (screen->fbFormat) {
case DV_PF_555:
case DV_PF_565:
i830->state.Buffer[I830_DESTREG_DV1] = (DSTORG_HORT_BIAS(0x8) | /* .5 */
DSTORG_VERT_BIAS(0x8) | /* .5 */
screen->fbFormat |
DEPTH_IS_Z |
DEPTH_FRMT_16_FIXED);
break;
case DV_PF_8888:
i830->state.Buffer[I830_DESTREG_DV1] = (DSTORG_HORT_BIAS(0x8) | /* .5 */
DSTORG_VERT_BIAS(0x8) | /* .5 */
screen->fbFormat |
DEPTH_IS_Z |
DEPTH_FRMT_24_FIXED_8_OTHER);
break;
}
i830->state.Buffer[I830_DESTREG_SENABLE] = (_3DSTATE_SCISSOR_ENABLE_CMD |
DISABLE_SCISSOR_RECT);
i830->state.Buffer[I830_DESTREG_SR0] = _3DSTATE_SCISSOR_RECT_0_CMD;
i830->state.Buffer[I830_DESTREG_SR1] = 0;
i830->state.Buffer[I830_DESTREG_SR2] = 0;
}