extern void stx7108_configure_spi(void)
{
/*
* We set up the PIO pins correctly for SPI
*/
#if defined(CONFIG_SOFT_SPI) /* Use "bit-banging" for SPI */
/* route PIO (alternate #0) */
stx7108_pioalt_select(2, 1, 0); /* SPI_MISO */
stx7108_pioalt_select(2, 0, 0); /* SPI_MOSI */
stx7108_pioalt_select(1, 7, 0); /* SPI_notCS */
stx7108_pioalt_select(1, 6, 0); /* SPI_CLK */
/* set PIO directionality */
SET_PIO_PIN(ST40_PIO_BASE(2), 1, STPIO_IN); /* SPI_MISO */
SET_PIO_PIN(ST40_PIO_BASE(2), 0, STPIO_OUT); /* SPI_MOSI */
SET_PIO_PIN(ST40_PIO_BASE(1), 7, STPIO_OUT); /* SPI_notCS */
SET_PIO_PIN(ST40_PIO_BASE(1), 6, STPIO_OUT); /* SPI_CLK */
/* drive outputs with sensible initial values */
STPIO_SET_PIN(ST40_PIO_BASE(2), 0, 0); /* deassert SPI_MOSI */
STPIO_SET_PIN(ST40_PIO_BASE(1), 7, 1); /* deassert SPI_notCS */
STPIO_SET_PIN(ST40_PIO_BASE(1), 6, 1); /* assert SPI_CLK */
#else
#error Currently only S/W bit-banging for SPI is supported.
#endif /* CONFIG_SOFT_SPI */
}
extern void fli7510_i2c_sda(const int val)
{
#if defined(CONFIG_I2C_BUS_1) /* Use I2C Bus "1" */
STPIO_SET_PIN(PIO_PORT(10), 3, (val) ? 1 : 0);
#elif defined(CONFIG_I2C_BUS_2) /* Use I2C Bus "2" */
STPIO_SET_PIN(PIO_PORT(9), 5, (val) ? 1 : 0);
#elif defined(CONFIG_I2C_BUS_3) /* Use I2C Bus "3" */
STPIO_SET_PIN(PIO_PORT(9), 7, (val) ? 1 : 0);
#endif
}
static void configEthernet(void)
{
/* Setup PIO for the PHY's reset */
SET_PIO_PIN(PIO_PORT(1),6,STPIO_OUT); /* PHY_RES is on PIO1[6] */
/* Finally, just toggle the PHY Reset pin */
STPIO_SET_PIN(PIO_PORT(1), 6, 0); /* Assert PHY_RES */
udelay(100); /* small delay (100us) */
STPIO_SET_PIN(PIO_PORT(1), 6, 1); /* de-assert PHY_RES */
}
extern void stmac_phy_reset(void)
{
/*
* Reset the Ethernet PHY.
* PIO20[0] == GMII0_notRESET
* PIO15[4] == GMII1_notRESET
*/
STPIO_SET_PIN(ST40_PIO_BASE(15), 4, 0);
udelay(10000); /* 10 ms */
STPIO_SET_PIN(ST40_PIO_BASE(15), 4, 1);
}
extern void stmac_phy_reset(void)
{
/*
* Reset the Ethernet PHY.
* Note both PHYs share the *same* reset line.
*
* PIO15[4] = POWER_ON_ETH (a.k.a. ETH_RESET)
*/
STPIO_SET_PIN(ST40_PIO_BASE(15), 4, 0);
udelay(10000); /* 10 ms */
STPIO_SET_PIN(ST40_PIO_BASE(15), 4, 1);
}
extern void spi_cs_deactivate(struct spi_slave * const slave)
{
const int pin = 4; /* PIO17[4] = SPI_CSN */
/* DE-assert SPI CSn */
STPIO_SET_PIN(PIO_PORT(17), pin, 1);
}
extern void stx7108_i2c_sda(const int val)
{
/* SSC's MTSR == I2C's SDA */
const int port = ssc_pios[CONFIG_I2C_BUS].pio[1].port;
const int pin = ssc_pios[CONFIG_I2C_BUS].pio[1].pin;
STPIO_SET_PIN(ST40_PIO_BASE(port), pin, (val) ? 1 : 0);
}
/*
* assert or de-assert the SPI Chip Select line.
*
* input: cs == true, assert CS, else deassert CS
*/
static void spi_chip_select(const int cs)
{
const int pin = 7; /* PIO1[7] = SPI_notCS */
if (cs)
{ /* assert SPI CSn */
STPIO_SET_PIN(ST40_PIO_BASE(1), pin, 0);
}
else
{ /* DE-assert SPI CSn */
STPIO_SET_PIN(ST40_PIO_BASE(1), pin, 1);
}
if (cs)
{ /* wait 250ns for CSn assert to propagate */
udelay(1); /* QQQ: can we make this shorter ? */
}
}
extern void stx7141_usb_init(void)
{
#ifdef QQQ /* QQQ - TO DO */
unsigned long reg, req_reg;
/* Power on the USB */
reg = readl(STX7141_SYSCONF_SYS_CFG32);
reg &= ~(1ul<<4); /* USB_POWER_DOWN_REQ = 0 */
writel(reg, STX7141_SYSCONF_SYS_CFG32);
/* Work around for USB over-current detection chip being
* active low, and the 7141 being active high.
* Note this is an undocumented bit, which apparently enables
* an inverter on the overcurrent signal.
*/
reg = readl(STX7141_SYSCONF_SYS_CFG06);
reg |= 1ul<<29;
writel(reg, STX7141_SYSCONF_SYS_CFG06);
/* USB oc */
SET_PIO_PIN(PIO_PORT(5), 6, STPIO_IN);
/* USB power */
SET_PIO_PIN(PIO_PORT(5), 7, STPIO_ALT_OUT);
STPIO_SET_PIN(PIO_PORT(5), 7, 1);
/* Set strap mode */
#define STRAP_MODE AHB2STBUS_STRAP_16_BIT
reg = readl(AHB2STBUS_STRAP);
#if STRAP_MODE == 0
reg &= ~AHB2STBUS_STRAP_16_BIT;
#else
reg |= STRAP_MODE;
#endif
writel(reg, AHB2STBUS_STRAP);
/* Start PLL */
reg = readl(AHB2STBUS_STRAP);
writel(reg | AHB2STBUS_STRAP_PLL, AHB2STBUS_STRAP);
udelay(100000); /* QQQ: can this delay be shorter ? */
writel(reg & (~AHB2STBUS_STRAP_PLL), AHB2STBUS_STRAP);
udelay(100000); /* QQQ: can this delay be shorter ? */
req_reg =
(1<<21) | /* Turn on read-ahead */
(5<<16) | /* Opcode is store/load 32 */
(0<<15) | /* Turn off write posting */
(1<<14) | /* Enable threshold */
(3<<9) | /* 2**3 Packets in a chunk */
(0<<4) | /* No messages */
(8<<0); /* Threshold is 256 */
do {
writel(req_reg, AHB2STBUS_STBUS_CONFIG);
reg = readl(AHB2STBUS_STBUS_CONFIG);
} while ((reg & 0x7FFFFFFF) != req_reg);
#endif /* QQQ - TO DO */
}
/*
* assert or de-assert the SPI Chip Select line.
*
* input: cs == true, assert CS, else deassert CS
*/
static void spi_chip_select(const int cs)
{
const int pin = 2; /* PIO15[2] = SPI_NOTCS */
if (cs)
{ /* assert SPI CSn */
STPIO_SET_PIN(PIO_PORT(15), pin, 0);
}
else
{ /* DE-assert SPI CSn */
STPIO_SET_PIN(PIO_PORT(15), pin, 1);
}
if (cs)
{ /* wait 250ns for CSn assert to propagate */
udelay(1); /* QQQ: can we make this shorter ? */
}
}
/*
* A pair of functions to assert and de-assert the SPI
* chip select line, for the given SPI "slave" device.
*
* This is used by both the S/W "bit-banging" and the
* H/W SSC drivers (but not the H/W FSM driver).
*
* We only support *one* SPI device, so we just ignore
* the "slave" parameter. This may change later...
*/
extern void spi_cs_activate(struct spi_slave * const slave)
{
const int pin = 4; /* PIO17[4] = SPI_CSN */
/* assert SPI CSn */
STPIO_SET_PIN(PIO_PORT(17), pin, 0);
/* wait 1us for CSn assert to propagate */
udelay(1);
}
static void configSpi(void)
{
#if defined(CONFIG_SOFT_SPI)
/* Configure SPI Serial Flash for PIO "bit-banging" */
/* SPI is on PIO2[2:0], with CS on PIO6[7] */
SET_PIO_PIN(PIO_PORT(2),0,STPIO_OUT); /* SPI_CLK */
SET_PIO_PIN(PIO_PORT(2),1,STPIO_OUT); /* SPI_DOUT */
SET_PIO_PIN(PIO_PORT(2),2,STPIO_IN); /* SPI_DIN */
SET_PIO_PIN(PIO_PORT(6),7,STPIO_OUT); /* SPI_NOTCS */
/* drive outputs with sensible initial values */
STPIO_SET_PIN(PIO_PORT(6), 7, 1); /* deassert SPI_NOCS */
STPIO_SET_PIN(PIO_PORT(2), 0, 1); /* assert SPI_CLK */
STPIO_SET_PIN(PIO_PORT(2), 1, 0); /* deassert SPI_DOUT */
#else
#error Still to impliment SPI via SSC for the STx7111.
#endif /* CONFIG_SOFT_SPI */
}
static void configPIO(void)
{
/* Setup PIO of ASC device */
SET_PIO_ASC(PIO_PORT(4), 3, 2, 4, 5); /* UART2 - AS0 */
SET_PIO_ASC(PIO_PORT(5), 4, 3, 5, 6); /* UART3 - AS1 */
#ifdef CONFIG_DRIVER_NETSTMAC
/* Reset the on-board STe101P PHY */
SET_PIO_PIN(PIO_PORT(4), 7, STPIO_OUT);
STPIO_SET_PIN(PIO_PORT(4), 7, 1);
udelay(1);
STPIO_SET_PIN(PIO_PORT(4), 7, 0);
udelay(1);
STPIO_SET_PIN(PIO_PORT(4), 7, 1);
#endif /* CONFIG_DRIVER_NETSTMAC */
#if defined(CONFIG_CMD_NAND)
/* Setup PIO for NAND FLASH devices: Ready/Not_Busy */
SET_PIO_PIN(PIO_PORT(2), 7, STPIO_IN);
#endif /* CONFIG_CMD_NAND */
}
static void configPIO(void)
{
/* Setup PIOs for ASC device */
#if CONFIG_SYS_STM_ASC_BASE == ST40_ASC1_REGS_BASE
/* Route UART1 via PIO5 for TX, RX, CTS & RTS (Alternative #1) */
PIOALT(5, 1, 1, stm_pad_direction_output); /* UART1-TX */
PIOALT(5, 2, 1, stm_pad_direction_input); /* UART1-RX */
PIOALT(5, 4, 1, stm_pad_direction_output); /* UART1-RTS */
PIOALT(5, 3, 1, stm_pad_direction_input); /* UART1-CTS */
#elif CONFIG_SYS_STM_ASC_BASE == ST40_ASC3_REGS_BASE
/* Route UART3 via PIO24/25 for TX, RX (Alternative #1) */
PIOALT(24, 4, 1, stm_pad_direction_output); /* UART3-TX */
PIOALT(24, 5, 1, stm_pad_direction_input); /* UART3-RX */
// PIOALT(24, 7, 1, stm_pad_direction_output); /* UART3-RTS */
// PIOALT(25, 0, 1, stm_pad_direction_input); /* UART3-CTS */
#else
#error Unknown ASC port selected!
#endif /* CONFIG_SYS_STM_ASC_BASE == ST40_ASCx_REGS_BASE */
#ifdef CONFIG_DRIVER_NET_STM_GMAC
/*
* Configure the Ethernet PHY Reset signal
* PIO15[4] == POWER_ON_ETH (a.k.a. ETH_RESET)
*/
SET_PIO_PIN(ST40_PIO_BASE(15), 4, STPIO_OUT);
#endif /* CONFIG_DRIVER_NET_STM_GMAC */
/*
* Some of the peripherals are powered by regulators
* controlled by the following PIO line...
* PIO5[0] == POWER_ON
*/
SET_PIO_PIN(ST40_PIO_BASE(5), 0, STPIO_OUT);
STPIO_SET_PIN(ST40_PIO_BASE(5), 0, 1);
}
extern void fli7510_spi_sda(const int val)
{
const int pin = 3; /* PIO17[3] = SPI_MOSI */
STPIO_SET_PIN(PIO_PORT(17), pin, val ? 1 : 0);
}
extern void stx7105_spi_sda(const int val)
{
const int pin = 1; /* PIO15[1] = SPI_DOUT */
STPIO_SET_PIN(PIO_PORT(15), pin, val ? 1 : 0);
}
/* configure the SATA host controller */
stm_sata_probe();
initialised_phy = 1;
}
}
#endif /* CONFIG_SH_STM_SATA */
#if defined(CONFIG_SPI)
#if defined(CONFIG_SOFT_SPI) /* Use "bit-banging" for SPI */
extern void stx7105_spi_scl(const int val)
{
const int pin = 0; /* PIO15[0] = SPI_CLK */
STPIO_SET_PIN(PIO_PORT(15), pin, val ? 1 : 0);
}
/* drive outputs with sensible initial values */
STPIO_SET_PIN(ST40_PIO_BASE(2), 0, 0); /* deassert SPI_MOSI */
STPIO_SET_PIN(ST40_PIO_BASE(1), 7, 1); /* deassert SPI_notCS */
STPIO_SET_PIN(ST40_PIO_BASE(1), 6, 1); /* assert SPI_CLK */
#else
#error Currently only S/W bit-banging for SPI is supported.
#endif /* CONFIG_SOFT_SPI */
}
#if defined(CONFIG_SOFT_SPI) /* Use "bit-banging" for SPI */
extern void stx7108_spi_scl(const int val)
{
const int pin = 6; /* PIO1[6] = SPI_CLK */
STPIO_SET_PIN(ST40_PIO_BASE(1), pin, val ? 1 : 0);
}
void stx7105_led_write(int led)
{
const int pin = 4; /* PIO0[1] = */
STPIO_SET_PIN(PIO_PORT(0), pin,led); //gongjia mark
}
extern void stx7108_spi_sda(const int val)
{
const int pin = 0; /* PIO2[0] = SPI_MOSI */
STPIO_SET_PIN(ST40_PIO_BASE(2), pin, val ? 1 : 0);
}
/**********************************************************************/
#if defined(CONFIG_SPI)
#if defined(CONFIG_SOFT_SPI) /* Use "bit-banging" for SPI */
extern void fli7510_spi_scl(const int val)
{
const int pin = 2; /* PIO17[2] = SPI_CLK */
STPIO_SET_PIN(PIO_PORT(17), pin, val ? 1 : 0);
}
extern void stx7200_usb_init(void)
{
const bd_t * const bd = gd->bd;
unsigned long reg;
const unsigned char power_pins[3] = {1, 3, 4};
const unsigned char oc_pins[3] = {0, 2, 5};
#if CONFIG_SYS_USB_BASE == CONFIG_SYS_USB0_BASE
const size_t port = 0;
#elif CONFIG_SYS_USB_BASE == CONFIG_SYS_USB1_BASE
const size_t port = 1;
#elif CONFIG_SYS_USB_BASE == CONFIG_SYS_USB2_BASE
const size_t port = 2;
#else
#error Unknown USB Host Controller Base Address
#endif
/* ClockgenB powers up with all the frequency synths bypassed.
* Enable them all here. Without this, USB 1.1 doesn't work,
* as it needs a 48MHz clock which is separate from the USB 2
* clock which is derived from the SATA clock. */
writel(0, STX7200_CLOCKGENB_OUT_MUX_CFG);
/* route USB and parts of MAFE instead of DVO.*/
/* DVO output selection (probably ignored). */
reg = readl(STX7200_SYSCONF_SYS_CFG07);
reg &= ~(1ul<<26); /* conf_pad_pio[2] = 0 */
reg &= ~(1ul<<27); /* conf_pad_pio[3] = 0 */
writel(reg, STX7200_SYSCONF_SYS_CFG07);
/* Enable soft JTAG mode for USB and SATA */
reg = readl(STX7200_SYSCONF_SYS_CFG33);
reg |= (1ul<<6); /* soft_jtag_en = 1 */
reg &= ~(0xful<<0); /* tck = tdi = trstn_usb = tms_usb = 0 */
writel(reg, STX7200_SYSCONF_SYS_CFG33);
#ifdef CONFIG_USB_STI7200_CUT1_SOFT_JTAG_RESET_WORKAROUND
/* reset USB HC via the JTAG scan path */
usb_soft_jtag_reset();
#endif
/* USB power */
SET_PIO_PIN(PIO_PORT(7), power_pins[port], STPIO_ALT_OUT);
STPIO_SET_PIN(PIO_PORT(7), power_pins[port], 1);
/* USB Over-Current */
if (STX7200_DEVICEID_CUT(bd->bi_devid) < 2)
SET_PIO_PIN(PIO_PORT(7), oc_pins[port], STPIO_ALT_BIDIR);
else
SET_PIO_PIN(PIO_PORT(7), oc_pins[port], STPIO_IN);
/* tusb_powerdown_req[port] = 0 */
reg = readl(STX7200_SYSCONF_SYS_CFG22);
reg &= ~(1ul<<(port+3));
writel(reg, STX7200_SYSCONF_SYS_CFG22);
/* Set strap mode */
#define STRAP_MODE AHB2STBUS_STRAP_16_BIT
reg = readl(AHB2STBUS_STRAP);
#if STRAP_MODE == 0
reg &= ~AHB2STBUS_STRAP_16_BIT;
#else
reg |= STRAP_MODE;
#endif
writel(reg, AHB2STBUS_STRAP);
/* Start PLL */
reg = readl(AHB2STBUS_STRAP);
writel(reg | AHB2STBUS_STRAP_PLL, AHB2STBUS_STRAP);
udelay(100000); /* QQQ: can this delay be shorter ? */
writel(reg & (~AHB2STBUS_STRAP_PLL), AHB2STBUS_STRAP);
udelay(100000); /* QQQ: can this delay be shorter ? */
/* Set the STBus Opcode Config for 32-bit access */
writel(AHB2STBUS_STBUS_OPC_32BIT, AHB2STBUS_STBUS_OPC);
/* Set the Message Size Config to 4 packets per message */
writel(AHB2STBUS_MSGSIZE_4, AHB2STBUS_MSGSIZE);
/* Set the Chunk Size Config to 4 packets per chunk */
writel(AHB2STBUS_CHUNKSIZE_4, AHB2STBUS_CHUNKSIZE);
}
