void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable Internal RC clock */
SYSCLK->PWRCON |= SYSCLK_PWRCON_IRC22M_EN_Msk;
/* Waiting for IRC22M clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_IRC22M_STB_Msk);
/* Switch HCLK clock source to Internal RC */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_IRC22M;
/* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/
SYSCLK->PLLCON |= SYSCLK_PLLCON_PD_Msk;
/* Enable external 12MHz XTAL, internal 22.1184MHz */
SYSCLK->PWRCON |= SYSCLK_PWRCON_XTL12M_EN_Msk | SYSCLK_PWRCON_IRC22M_EN_Msk;
/* Enable PLL and Set PLL frequency */
SYSCLK->PLLCON = PLLCON_SETTING;
/* Waiting for clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_PLL_STB_Msk | SYSCLK_CLKSTATUS_XTL12M_STB_Msk | SYSCLK_CLKSTATUS_IRC22M_STB_Msk);
/* Switch HCLK clock source to PLL, STCLK to HCLK/2 */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_STCLK_HCLK_DIV2 | SYSCLK_CLKSEL0_HCLK_PLL;
/* Enable IP clock */
SYSCLK->APBCLK = SYSCLK_APBCLK_PWM01_EN_Msk | SYSCLK_APBCLK_PWM23_EN_Msk | SYSCLK_APBCLK_TMR0_EN_Msk;
/* IP clock source */
SYSCLK->CLKSEL1 = SYSCLK_CLKSEL1_PWM01_XTAL | SYSCLK_CLKSEL1_PWM23_XTAL |SYSCLK_CLKSEL1_TMR0_XTAL;
/* Reset PWMB channel0~channel3 and Reset TIMER0*/
SYS->IPRSTC2 = SYS_IPRSTC2_PWM03_RST_Msk | SYS_IPRSTC2_TMR0_RST_Msk;
SYS->IPRSTC2 = 0;
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P2 multi-function pins for PWMA Channel0~3 */
//SYS->P2_MFP = SYS_MFP_P20_PWM0|SYS_MFP_P21_PWM1|SYS_MFP_P22_PWM2;
SYS->P2_MFP = SYS_MFP_P22_PWM2;
/* Lock protected registers */
SYS_LockReg();
}
/*---------------------------------------------------------------------------------------------------------*/
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable External XTAL (4~24 MHz) */
SYSCLK->PWRCON |= SYSCLK_PWRCON_XTL12M_EN_Msk;
/* Waiting for 12MHz clock ready */
SYS_WaitingForClockReady( SYSCLK_CLKSTATUS_XTL12M_STB_Msk);
/* Switch HCLK clock source to XTAL */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_XTAL;
/* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/
SYSCLK->PLLCON |= SYSCLK_PLLCON_PD_Msk;
/* Set PLL frequency */
SYSCLK->PLLCON = PLLCON_SETTING;
/* Waiting for clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_PLL_STB_Msk);
/* Switch HCLK clock source to PLL */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_PLL;
/* Enable IP clock */
SYSCLK->APBCLK = SYSCLK_APBCLK_UART0_EN_Msk | SYSCLK_APBCLK_ADC_EN_Msk ;
/* IP clock source */
SYSCLK->CLKSEL1 = SYSCLK_CLKSEL1_UART_XTAL | SYSCLK_CLKSEL1_ADC_XTAL ;
/* Set ADC divisor */
_ADC_SET_CLK_DIV(7);
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set GPB multi-function pins for UART0 RXD and TXD */
SYS->GPB_MFP = SYS_GPB_MFP_PB1_TXD0 | SYS_GPB_MFP_PB0_RXD0;
/* Disable the GPA0 - GPA3 digital input path to avoid the leakage current. */
PA->OFFD = (GPIO_OFFD_ENABLE(0)|GPIO_OFFD_ENABLE(1)|GPIO_OFFD_ENABLE(2)|GPIO_OFFD_ENABLE(3));
/* Configure the GPA0 - GPA3 ADC analog input pins */
SYS->GPA_MFP = SYS_GPA_MFP_PA0_ADC0 | SYS_GPA_MFP_PA1_ADC1 | SYS_GPA_MFP_PA2_ADC2 | SYS_GPA_MFP_PA3_ADC3 ;
SYS->ALT_MFP1 = 0;
/* Lock protected registers */
SYS_LockReg();
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable Internal RC clock */
SYSCLK->PWRCON |= SYSCLK_PWRCON_IRC22M_EN_Msk;
/* Waiting for IRC22M clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_IRC22M_STB_Msk);
/* Switch HCLK clock source to internal RC */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_IRC22M;
/* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/
SYSCLK->PLLCON |= SYSCLK_PLLCON_PD_Msk;
/* Enable external 12MHz XTAL, 10kHz */
SYSCLK->PWRCON |= SYSCLK_PWRCON_XTL12M_EN_Msk | SYSCLK_PWRCON_IRC10K_EN_Msk;
/* Enable PLL and Set PLL frequency */
SYSCLK->PLLCON = PLLCON_SETTING;
/* Waiting for clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_PLL_STB_Msk | SYSCLK_CLKSTATUS_XTL12M_STB_Msk | SYSCLK_CLKSTATUS_IRC10K_STB_Msk);
/* Switch HCLK clock source to PLL, STCLK to HCLK/2 */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_STCLK_HCLK_DIV2 | SYSCLK_CLKSEL0_HCLK_PLL;
/* Enable IP clock */
SYSCLK->AHBCLK = SYSCLK_AHBCLK_ISP_EN_Msk;
SYSCLK->APBCLK = SYSCLK_APBCLK_UART0_EN_Msk | SYSCLK_APBCLK_SPI0_EN_Msk;
/* IP clock source */
SYSCLK->CLKSEL1 = SYSCLK_CLKSEL1_UART_PLL;
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P3 multi-function pins for UART0 RXD and TXD */
SYS->P3_MFP = SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0;
/* Set P1.4, P1.5, P1.6, P1.7 for SPI0 */
SYS->P1_MFP = SYS_MFP_P14_SPISS0 | SYS_MFP_P15_MOSI_0 | SYS_MFP_P16_MISO_0 | SYS_MFP_P17_SPICLK0;
/* Lock protected registers */
SYS_LockReg();
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable External XTAL (4~24 MHz) */
SYSCLK->PWRCON |= SYSCLK_PWRCON_XTL12M_EN_Msk;
/* Enable external 32 kHz XTAL */
SYSCLK->PWRCON |= SYSCLK_PWRCON_XTL32K_EN_Msk;
/* Waiting for clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_XTL12M_STB_Msk | SYSCLK_CLKSTATUS_XTL32K_STB_Msk);
/* Switch HCLK clock source to XTAL */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_XTAL;
/* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/
SYSCLK->PLLCON |= SYSCLK_PLLCON_PD_Msk;
/* Set PLL frequency */
SYSCLK->PLLCON = PLLCON_SETTING;
/* Waiting for clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_PLL_STB_Msk);
/* Switch HCLK clock source to PLL */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_PLL;
/* Enable IP clock */
SYSCLK->APBCLK = SYSCLK_APBCLK_UART0_EN_Msk | SYSCLK_APBCLK_RTC_EN_Msk | SYSCLK_APBCLK_TMR0_EN_Msk;
/* IP clock source */
SYSCLK->CLKSEL1 = SYSCLK_CLKSEL1_UART_PLL | SYSCLK_CLKSEL1_TMR0_XTAL;
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PB multi-function pins for UART0 RXD, UART0 TXD */
SYS->GPB_MFP = SYS_GPB_MFP_PB0_RXD0 | SYS_GPB_MFP_PB1_TXD0;
/* Lock protected registers */
SYS_LockReg();
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable External XTAL (4~24 MHz) */
SYSCLK->PWRCON |= SYSCLK_PWRCON_XTL12M_EN_Msk;
/* Waiting for 12MHz clock ready */
SYS_WaitingForClockReady( SYSCLK_CLKSTATUS_XTL12M_STB_Msk);
/* Switch HCLK clock source to XTAL */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_XTAL;
/* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/
SYSCLK->PLLCON |= SYSCLK_PLLCON_PD_Msk;
/* Set PLL frequency */
SYSCLK->PLLCON = PLLCON_SETTING;
/* Waiting for clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_PLL_STB_Msk);
/* Switch HCLK clock source to PLL */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_PLL;
/* Enable IP clock */
SYSCLK->APBCLK = SYSCLK_APBCLK_UART0_EN_Msk | SYSCLK_APBCLK_SPI0_EN_Msk | SYSCLK_APBCLK_SPI1_EN_Msk;
/* Select IP clock source */
SYSCLK->CLKSEL1 = SYSCLK_CLKSEL1_UART_XTAL;
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PB multi-function pins for UART0 RXD and TXD */
SYS->GPB_MFP = SYS_GPB_MFP_PB1_TXD0 | SYS_GPB_MFP_PB0_RXD0;
/* Set PC0, PC1, PC2 and PC3 for SPI0; set PC8, PC9, PC10 and PC11 for SPI1 */
SYS->GPC_MFP = SYS_GPC_MFP_PC0_SPISS00 | SYS_GPC_MFP_PC1_SPICLK0 | SYS_GPC_MFP_PC2_MISO00 | SYS_GPC_MFP_PC3_MOSI00 |
SYS_GPC_MFP_PC8_SPISS10 | SYS_GPC_MFP_PC9_SPICLK1 | SYS_GPC_MFP_PC10_MISO10 | SYS_GPC_MFP_PC11_MOSI10;
SYS->ALT_MFP = 0;
/* Lock protected registers */
SYS_LockReg();
}
void SYS_PLL_Test(void)
{
int32_t i;
/*---------------------------------------------------------------------------------------------------------*/
/* PLL clock confiruation test */
/*---------------------------------------------------------------------------------------------------------*/
printf("\n-------------------------[ Test PLL ]-----------------------------\n");
for (i = 0; i < sizeof(g_au32PllSetting)/sizeof(g_au32PllSetting[0]) ; i++)
{
/* Switch HCLK clock source to XTAL */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_XTAL;
/* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/
SYSCLK->PLLCON|= SYSCLK_PLLCON_PD_Msk;
/* Set PLL frequency */
SYSCLK->PLLCON = g_au32PllSetting[i];
/* Waiting for clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_PLL_STB_Msk);
/* Switch HCLK clock source to PLL */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_PLL;
/* Update System Core Clock */
SystemCoreClockUpdate();
printf(" Change system clock to %d Hz ......................... ", SystemCoreClock);
/* Ouput selected clock to CKO, CKO Clock = HCLK / 2^(1 + 1) */
SYS_EnableCKO(SYSCLK_CLKSEL2_FRQDIV_HCLK, 1);
/* The delay loop is used to check if the CPU speed is increasing */
Delay(0x400000);
if (pi())
{
printf("[FAIL]\n");
}
else
{
printf("[OK]\n");
}
/* Disable CKO clock */
SYS_DisableCKO();
}
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable external 12MHz XTAL */
SYSCLK->PWRCON |= SYSCLK_PWRCON_XTL12M_EN_Msk;
SYSCLK->PLLCON = PLLCON_SETTING;
/* Waiting for clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_PLL_STB_Msk | SYSCLK_CLKSTATUS_XTL12M_STB_Msk);
/* Switch HCLK clock source to PLL */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_PLL;
/* Enable IP clock */
SYSCLK->AHBCLK = SYSCLK_AHBCLK_PDMA_EN_Msk;
SYSCLK->APBCLK = SYSCLK_APBCLK_UART0_EN_Msk | SYSCLK_APBCLK_UART1_EN_Msk;
/* IP clock source */
SYSCLK->CLKSEL1 = SYSCLK_CLKSEL1_UART_PLL;
/* Reset PDMA and UART0/1*/
SYS->IPRSTC1 = SYS_IPRSTC1_PDMA_RST_Msk;
SYS->IPRSTC1 = 0;
SYS->IPRSTC2 = SYS_IPRSTC2_UART0_RST_Msk | SYS_IPRSTC2_UART1_RST_Msk;
SYS->IPRSTC2 = 0;
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PB0/PB1 multi-function pins for UART0 RXD and TXD */
SYS->GPB_MFP = SYS_GPB_MFP_PB0_RXD0 | SYS_GPB_MFP_PB1_TXD0 |
SYS_GPB_MFP_PB4_RXD1 | SYS_GPB_MFP_PB5_TXD1;
/* Lock protected registers */
SYS_LockReg();
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable external 12MHz XTAL */
SYSCLK->PWRCON |= SYSCLK_PWRCON_XTL12M_EN_Msk;
/* Enable internal 22.1184 MHz Oscillator */
SYSCLK->PWRCON |= SYSCLK_PWRCON_IRC22M_EN_Msk;
/* Waiting for clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_XTL12M_STB_Msk | SYSCLK_CLKSTATUS_IRC22M_STB_Msk);
/* Force system to use other clock source before PLL setting */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_IRC22M;
/* Disable PLL before changing PLL setting */
SYSCLK->PLLCON |= SYSCLK_PLLCON_PD_Msk;
/* Enable PLL and update new PLL setting */
SYSCLK->PLLCON = PLLCON_SETTING;
/* Waiting for PLL ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_PLL_STB_Msk);
/* Switch HCLK clock source to PLL */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_PLL;
/* Enable IP clock */
SYSCLK->APBCLK = SYSCLK_APBCLK_UART0_EN_Msk | SYSCLK_APBCLK_TMR0_EN_Msk |
SYSCLK_APBCLK_CAN0_EN_Msk | SYSCLK_APBCLK_CAN1_EN_Msk;
/* IP clock source */
SYSCLK->CLKSEL1 = SYSCLK_CLKSEL1_UART_PLL | SYSCLK_CLKSEL1_TMR0_XTAL;
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PA multi-function pins for CANTX1, CANRX1 */
SYS->GPA_MFP = SYS_GPA_MFP_PA10_CANTX1 | SYS_GPA_MFP_PA11_CANRX1;
/* Set PB multi-function pins for UART0 RXD, UART0 TXD */
SYS->GPB_MFP = SYS_GPB_MFP_PB0_RXD0 | SYS_GPB_MFP_PB1_TXD0;
/* Set PD multi-function pins for CANTX0, CANRX0 */
SYS->GPD_MFP = SYS_GPD_MFP_PD6_CAN0RX | SYS_GPD_MFP_PD7_CAN0TX;
/* Alt setting for CANTX1, CANRX1 */
SYS->ALT_MFP = SYS_ALT_MFP_PA10_CANTX1 | SYS_ALT_MFP_PA11_CANRX1;
/* Lock protected registers */
//SYS_LockReg();
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Set clock divder */
SYSCLK->CLKDIV = SYSCLK_CLKDIV_HCLK(HCLK_DIV) | SYSCLK_CLKDIV_USB(1);
/* Enable External XTAL (4~24 MHz) */
SYSCLK->PWRCON |= SYSCLK_PWRCON_XTL12M_EN_Msk;
/* Waiting for 12MHz clock ready */
SYS_WaitingForClockReady( SYSCLK_CLKSTATUS_XTL12M_STB_Msk);
/* Switch HCLK clock source to XTAL */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_XTAL;
/* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/
SYSCLK->PLLCON |= SYSCLK_PLLCON_PD_Msk;
/* Set PLL frequency */
SYSCLK->PLLCON = PLLCON_SETTING;
/* Waiting for clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_PLL_STB_Msk);
/* Switch HCLK clock source to PLL */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_PLL;
/* Enable IP clock */
SYSCLK->APBCLK = SYSCLK_APBCLK_UART0_EN_Msk | SYSCLK_APBCLK_I2S_EN_Msk | SYSCLK_APBCLK_I2C0_EN_Msk;
/* IP clock source */
SYSCLK->CLKSEL1 = SYSCLK_CLKSEL1_UART_XTAL | SYSCLK_CLKSEL1_WDT_IRC10K |
SYSCLK_CLKSEL1_TMR0_XTAL | SYSCLK_CLKSEL1_TMR1_HCLK | SYSCLK_CLKSEL1_TMR2_IRC22M | SYSCLK_CLKSEL1_TMR3_XTAL;
#ifdef DEMO_OPT_SLAVE
/* Use external 12MHz as I2S clock source */
SYSCLK->CLKSEL2 = SYSCLK_CLKSEL2_I2S_XTAL;
#else
/* Use external HCLK as I2S clock source */
SYSCLK->CLKSEL2 = SYSCLK_CLKSEL2_I2S_HCLK;
#endif
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / HCLK_DIV; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PA multi-function pins for I2C0 SDA, SCL, I2S MCLK */
SYS->GPA_MFP = SYS_GPA_MFP_PA8_SDA0 | SYS_GPA_MFP_PA9_SCL0 | SYS_GPA_MFP_PA15_I2SMCLK;
/* Set PB multi-function pins for UART0 RXD, TXD */
SYS->GPB_MFP = SYS_GPB_MFP_PB0_RXD0 | SYS_GPB_MFP_PB1_TXD0;
/* Set PC multi-function pins for I2S LRCLK, BCLK, SDI, SDO */
SYS->GPC_MFP = SYS_GPC_MFP_PC0_I2SLRCLK | SYS_GPC_MFP_PC1_I2SBCLK | SYS_GPC_MFP_PC2_I2SDI |
SYS_GPC_MFP_PC3_I2SDO;
SYS->ALT_MFP = SYS_ALT_MFP_PC0_I2SLRCLK | SYS_ALT_MFP_PC1_I2SBCLK | SYS_ALT_MFP_PC2_I2SDI |
SYS_ALT_MFP_PC3_I2SDO | SYS_ALT_MFP_PA15_I2SMCLK;
SYS->ALT_MFP1 = SYS_ALT_MFP1_PA15_I2SMCLK;
/* Lock protected registers */
//SYS_LockReg();
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable Internal RC clock */
SYSCLK->PWRCON |= SYSCLK_PWRCON_IRC22M_EN_Msk;
/* Waiting for IRC22M clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_IRC22M_STB_Msk);
/* Switch HCLK clock source to Internal RC */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_IRC22M;
/* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/
SYSCLK->PLLCON |= SYSCLK_PLLCON_PD_Msk;
/* Enable external 12MHz XTAL, internal 22.1184MHz */
SYSCLK->PWRCON |= SYSCLK_PWRCON_XTL12M_EN_Msk | SYSCLK_PWRCON_IRC22M_EN_Msk;
/* Enable PLL and Set PLL frequency */
SYSCLK->PLLCON = PLLCON_SETTING;
/* Waiting for clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_PLL_STB_Msk | SYSCLK_CLKSTATUS_XTL12M_STB_Msk | SYSCLK_CLKSTATUS_IRC22M_STB_Msk);
/* Switch HCLK clock source to PLL, STCLK to HCLK/2 */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_STCLK_HCLK_DIV2 | SYSCLK_CLKSEL0_HCLK_PLL;
/* Enable IP clock */
// SYSCLK->APBCLK = SYSCLK_APBCLK_PWM01_EN_Msk | SYSCLK_APBCLK_PWM23_EN_Msk | SYSCLK_APBCLK_TMR2_EN_Msk;
/* IP clock source */
// SYSCLK->CLKSEL1 = SYSCLK_CLKSEL1_PWM01_HCLK | SYSCLK_CLKSEL1_PWM23_HCLK | SYSCLK_CLKSEL1_TMR2_HCLK;
/* IP clock source */
// SYSCLK->CLKSEL2 = SYSCLK_CLKSEL2_PWM01_XTAL|SYSCLK_CLKSEL2_PWM23_XTAL;
/* Reset PWMA channel0~channel3 */
// SYS->IPRSTC2 = SYS_IPRSTC2_PWM03_RST_Msk;
// SYS->IPRSTC2 = 0;
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
// Init LCD GPIO
_GPIO_SET_PIN_MODE(P3, 0, GPIO_PMD_OUTPUT);
_GPIO_SET_PIN_MODE(P3, 1, GPIO_PMD_OUTPUT);
_GPIO_SET_PIN_MODE(P3, 2, GPIO_PMD_OUTPUT);
_GPIO_SET_PIN_MODE(P3, 3, GPIO_PMD_OUTPUT);
_GPIO_SET_PIN_MODE(P3, 4, GPIO_PMD_OUTPUT);
_GPIO_SET_PIN_MODE(P3, 5, GPIO_PMD_OUTPUT);
// Init Encoder GPIO
// _GPIO_SET_PIN_MODE(P0, 2, GPIO_PMD_INPUT);
// _GPIO_SET_PIN_MODE(P0, 3, GPIO_PMD_INPUT);
/*
_GPIO_ENABLE_DEBOUNCE(P0, 2);
_GPIO_ENABLE_DEBOUNCE(P0, 3);
_GPIO_SET_DEBOUNCE_TIME(GPIO_DBNCECON_DBCLKSRC_HCLK, GPIO_DBNCECON_DBCLKSEL_16);
*/
// GPIO_EnableInt(P0, 2, GPIO_INT_RISING);
// GPIO_EnableInt(P0, 3, GPIO_INT_RISING);
// NVIC_EnableIRQ(GPIO_P0P1_IRQn);
// NVIC_EnableIRQ(TMR2_IRQn);
// NVIC_EnableIRQ(PWMA_IRQn);
// Test Output
// _GPIO_SET_PIN_MODE(P0, 4, GPIO_PMD_OUTPUT);
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P3 multi-function pins for UART0 RXD and TXD */
// SYS->P3_MFP = SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0;
/* Set P2 multi-function pins for PWMB Channel0~3 */
// SYS->P2_MFP = SYS_MFP_P20_PWM0;
// SYS->P4_MFP = SYS_MFP_P40_T2EX;
/* Lock protected registers */
SYS_LockReg();
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable Internal RC clock */
SYSCLK->PWRCON |= SYSCLK_PWRCON_IRC22M_EN_Msk;
/* Waiting for IRC22M clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_IRC22M_STB_Msk);
/* Switch HCLK clock source to Internal RC */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_IRC22M;
/* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/
SYSCLK->PLLCON |= SYSCLK_PLLCON_PD_Msk;
/* Enable external 12MHz XTAL */
SYSCLK->PWRCON |= SYSCLK_PWRCON_XTL12M_EN_Msk;
/* Enable PLL and Set PLL frequency */
SYSCLK->PLLCON = PLLCON_SETTING;
/* Waiting for clock ready */
SYS_WaitingForClockReady(SYSCLK_CLKSTATUS_PLL_STB_Msk | SYSCLK_CLKSTATUS_XTL12M_STB_Msk);
/* Switch HCLK clock source to PLL, STCLK to HCLK/2 */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_STCLK_HCLK_DIV2 | SYSCLK_CLKSEL0_HCLK_PLL;
/* Enable EBI clock */
SYSCLK->AHBCLK |= SYSCLK_AHBCLK_EBI_EN_Msk;
/* Enable IP clock */
SYSCLK->APBCLK = SYSCLK_APBCLK_UART0_EN_Msk;
/* IP clock source */
SYSCLK->CLKSEL1 = SYSCLK_CLKSEL1_UART_PLL;
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P3 multi-function pins for UART0 RXD, TXD and EBI MCLK, nWR and nRD */
SYS->P3_MFP = SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0 | SYS_MFP_P33_MCLK | SYS_MFP_P36_nWR | SYS_MFP_P37_nRD;
/* Set P0 multi-function pins for EBI AD0 ~ AD7 */
SYS->P0_MFP = SYS_MFP_P00_AD0 | SYS_MFP_P01_AD1 | SYS_MFP_P02_AD2 | SYS_MFP_P03_AD3 |
SYS_MFP_P04_AD4 | SYS_MFP_P05_AD5 | SYS_MFP_P06_AD6 | SYS_MFP_P07_AD7;
/* Set P2 multi-function pins for EBI AD8 ~ AD15 */
SYS->P2_MFP = SYS_MFP_P20_AD8 | SYS_MFP_P21_AD9 | SYS_MFP_P22_AD10 | SYS_MFP_P23_AD11 |
SYS_MFP_P24_AD12 | SYS_MFP_P25_AD13 | SYS_MFP_P26_AD14 | SYS_MFP_P27_AD15;
/* Set P1 multi-function pins for EBI nWRL and nWRH */
SYS->P1_MFP = SYS_MFP_P10_nWRL | SYS_MFP_P11_nWRH;
/* Set P4 multi-function pins for EBI nCS, ALE and ICE CLK and DAT */
SYS->P4_MFP = SYS_MFP_P44_nCS | SYS_MFP_P45_ALE | SYS_MFP_P46_ICE_CLK | SYS_MFP_P47_ICE_DAT;
/* Lock protected registers */
SYS_LockReg();
}
