static void evergreen_set_streamout_enable(struct r600_common_context *rctx, unsigned buffer_enable_bit) { struct radeon_winsys_cs *cs = rctx->rings.gfx.cs; if (buffer_enable_bit) { r600_write_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2); radeon_emit(cs, S_028B94_STREAMOUT_0_EN(1)); /* R_028B94_VGT_STRMOUT_CONFIG */ radeon_emit(cs, S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit)); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */ } else { r600_write_context_reg(cs, R_028B94_VGT_STRMOUT_CONFIG, S_028B94_STREAMOUT_0_EN(0)); } }
void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit) { struct radeon_winsys_cs *cs = ctx->cs; if (buffer_enable_bit) { cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - EVERGREEN_CONTEXT_REG_OFFSET) >> 2; cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(1); cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); cs->buf[cs->cdw++] = (R_028B98_VGT_STRMOUT_BUFFER_CONFIG - EVERGREEN_CONTEXT_REG_OFFSET) >> 2; cs->buf[cs->cdw++] = S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit); } else {
cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0); cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0); cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */ cs->buf[cs->cdw++] = R_0084FC_CP_STRMOUT_CNTL >> 2; /* register */ cs->buf[cs->cdw++] = 0; cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* reference value */ cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* mask */ cs->buf[cs->cdw++] = 4; /* poll interval */ } void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit) { struct radeon_winsys_cs *cs = ctx->cs; if (buffer_enable_bit) { cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - EVERGREEN_CONTEXT_REG_OFFSET) >> 2; cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(1); cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); cs->buf[cs->cdw++] = (R_028B98_VGT_STRMOUT_BUFFER_CONFIG - EVERGREEN_CONTEXT_REG_OFFSET) >> 2; cs->buf[cs->cdw++] = S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit); } else { cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - EVERGREEN_CONTEXT_REG_OFFSET) >> 2; cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(0); } }