/********************************************************************************* *** ERROR_INT ISR ***/ void BLE_ERROR_Handler(void) { #if DEVELOPMENT_DEBUG // Break into the debugger if one is attached otherwise a hardfault int will be triggerd __asm("BKPT #0\n"); #endif // Handle exception accordingly // Acknowledge interrupt SetBits32(BLE_INTACK_REG, ERRORINTACK, 1); SetBits32(BLE_CNTL2_REG, EMACCERRACK, 1); }
/* * Init TX and RX buffers, they are in EM but not in the retainable part * so the pointers have to be programmed again * */ if(func_check_mem_flag) { if (func_check_mem_flag==2) { //init TX/RX buffers after DEEPSLEEP co_buf_init_deep_sleep(); // Set the first RX descriptor pointer into the HW ble_currentrxdescptr_set(REG_BLE_EM_RX_ADDR_GET(co_buf_rx_current_get())); } //INIT NONE RET. HEAP after DEEPSLEEP ke_mem_init(KE_MEM_NON_RETENTION, (uint8_t*)(jump_table_struct[rwip_heap_non_ret_pos]), jump_table_struct[rwip_heap_non_ret_size]); func_check_mem_flag = 0;//false; } #endif //RW_BLE_SUPPORT #endif //DEEP_SLEEP } #endif //0 // /********************************************************************************* // *** SLP_INT ISR // ***/ void BLE_SLP_Handler(void) //void BLE_SLP_Handler_func(void) { ble_regs_pop(); //smpc_regs_pop(); //#if !DEEP_SLEEP_ENABLED //# if DEVELOPMENT__NO_OTP // SetBits16(SYS_CTRL_REG, DEBUGGER_ENABLE, 1); //# else // SetBits16(SYS_CTRL_REG, DEBUGGER_ENABLE, 0); //# endif // DEVELOPMENT__NO_OTP //#endif // !DEEP_SLEEP_ENABLED SetBits16(GP_CONTROL_REG, BLE_WAKEUP_REQ, 0); //just to be sure if(jump_table_struct[0] == TASK_GTL) { // UART and pads have already been activated by periph_init() which is called // at initialization by main_func() and during wakeup by BLE_WAKEUP_LP_Handler(). gtl_eif_init(); } SetBits32(BLE_INTACK_REG, SLPINTACK, 1); #if DEEP_SLEEP //Needed only for compilation. Remove when ROM code is ready. #if RW_BLE_SUPPORT rwip_wakeup(); #endif //RW_BLE_SUPPORT #endif //DEEP_SLEEP if (lp_clk_sel == LP_CLK_RCX20) calibrate_rcx20(20); }
/* * Wait for at least one Low Power clock edge after the power up of the Radio Power Domain *e.g. with ble_wait_lp_clk_posedge() ) * or even better check the BLE_CNTL2_REG[WAKEUPLPSTAT] ! * Thus you assure that BLE_WAKEUP_LP_IRQ is deasserted and BLE_SLP_IRQ is asserted. * After this check exit this ISE in order to proceed with BLE_SLP_Handler(). */ while ( GetBits32(BLE_CNTL2_REG, WAKEUPLPSTAT) || !GetBits32(BLE_INTSTAT_REG, SLPINTSTAT)) if (t) break; // Now BLE_WAKEUP_LP_IRQ is deasserted and BLE_SLP_IRQ is asserted, so exit in order to proceed with BLE_SLP_Handler(). // NOTE: If returning from BLE_WAKEUP_LP_Handler() will not cause BLE_SLP_Handler() to start, // but the code after __WFI() is executed, then THERE WAS A SW SETUP PROBLEM !!! // so it is recommended to place a check after __WFI(). } #if 0 // /********************************************************************************* // *** CSCNT ISR // ***/ void BLE_CSCNT_Handler(void) { SetBits32(BLE_INTACK_REG, CSCNTINTACK, 1); #if DEEP_SLEEP //Needed only for compilation. Remove when ROM code is ready. #if RW_BLE_SUPPORT // Handle end of wake-up rwip_wakeup_end(); /* * Init TX and RX buffers, they are in EM but not in the retainable part * so the pointers have to be programmed again * */ if(func_check_mem_flag) { if (func_check_mem_flag==2) { //init TX/RX buffers after DEEPSLEEP co_buf_init_deep_sleep(); // Set the first RX descriptor pointer into the HW ble_currentrxdescptr_set(REG_BLE_EM_RX_ADDR_GET(co_buf_rx_current_get())); } //INIT NONE RET. HEAP after DEEPSLEEP ke_mem_init(KE_MEM_NON_RETENTION, (uint8_t*)(jump_table_struct[rwip_heap_non_ret_pos]), jump_table_struct[rwip_heap_non_ret_size]); func_check_mem_flag = 0;//false; } #endif //RW_BLE_SUPPORT #endif //DEEP_SLEEP }
void set_state_start_continue_tx(void) { if(test_state==STATE_IDLE) { struct llm_le_tx_test_cmd tx_con_test; tx_con_test.tx_freq = test_freq; tx_con_test.test_data_len = 37; //select a valid value. tx_con_test.pk_payload_type = test_data_pattern; llm_test_mode_start_tx( (struct llm_le_tx_test_cmd const *)&tx_con_test); SetBits32(BLE_RFTESTCNTL_REG,INFINITETX,1); SetBits32(BLE_RFTESTCNTL_REG,TXLENGTHSRC,0); SetBits32(BLE_RFTESTCNTL_REG,TXPLDSRC,0); SetBits32(BLE_RFTESTCNTL_REG,TXLENGTH,0); test_state = STATE_START_CONTINUE_TX; } }
/** **************************************************************************************** * @brief Callback function, called when external wakeup function is triggered. * * @return void. **************************************************************************************** */ void ext_wakeup_cb(void) { if (GetBits16(SYS_STAT_REG, PER_IS_DOWN)) { // Return GPIO functionality from external wakeup GPIO #if DEVELOPMENT_DEBUG GPIO_reservations(); #endif set_pad_functions(); } SetBits32(GP_CONTROL_REG, BLE_WAKEUP_REQ, 1); }
void BLE_SLP_Handler(void) //void BLE_SLP_Handler_func(void) { ble_regs_pop(); // smpc_regs_pop(); // SetBits16(SYS_CTRL_REG, DEBUGGER_ENABLE, 0); SetBits16(GP_CONTROL_REG, BLE_WAKEUP_REQ, 0); //just to be sure if((jump_table_struct[0] == TASK_GTL) || (BLE_INTEGRATED_HOST_GTL == 1 )) { // UART and pads have already been activated by periph_init() which is called // at initialization by main_func() and during wakeup by BLE_WAKEUP_LP_Handler(). gtl_eif_init(); } SetBits32(BLE_INTACK_REG, SLPINTACK, 1); #if DEEP_SLEEP //Needed only for compilation. Remove when ROM code is ready. #if RW_BLE_SUPPORT rwip_wakeup(); #endif //RW_BLE_SUPPORT #endif //DEEP_SLEEP /* * Radio Subsystem initialization. Execute here after making sure that BLE core is awake. */ rf_workaround_init(); rf_reinit(); if (lp_clk_sel == LP_CLK_RCX20) calibrate_rcx20(20); rwble_last_event = BLE_EVT_SLP; }
void app_init(void) { app_disable_sleep(); test_state = STATE_IDLE; test_data_pattern = 2; test_freq = 0; test_data_len = 37; text_tx_nr_of_packets = 50; test_tx_packet_nr = 0; test_rx_packet_nr = 0; test_rx_packet_nr_syncerr = 0; test_rx_packet_nr_crcerr = 0; test_rx_irq_cnt = 0; rx_test_rssi_1 = 0; rx_test_rssi_2 = 0; SetBits32(BLE_CNTL2_REG, BLE_RSSI_SEL, 1); //SELECT CURRENT AVERAGE RSSI. rf_calibration_request_cbt = 0; init_TXEN_RXEN_irqs(); #if 0 //test starts automatically see mail Yannis, George { // allocate the complete event message struct llm_le_tx_test_cmd *event = ke_msg_alloc(LLM_LE_TEST_TX_CMD, TASK_LLM, TASK_GTL, 3); ///TX frequency for Tx test event->tx_freq = 0; ///TX test data length event->test_data_len = 4; ///TX test payload type - see enum event->pk_payload_type = 0; // send the message ke_msg_send(event); } #endif }
void rf_reinit_func(void) { uint32 tmp32 = 0; SetBits32(&tmp32, RTRIP_DELAY, 7); SetBits32(&tmp32, TXPWRDN, 0x5); SetBits32(&tmp32, RXPWRUP, RXPWRUP_VAL); SetBits32(&tmp32, TXPWRUP, TXPWRUP_VAL); SetWord32(BLE_RADIOPWRUPDN_REG, tmp32); SetBits32(BLE_RADIOCNTL1_REG, XRFSEL, 3); SetBits32(BLE_RWBTLECNTL_REG, SYNCERR, 0); //this must be always '0' SetBits16(CLK_RADIO_REG, RFCU_DIV, 1); //RFCU clock must always be 8MHz! SetBits16(CLK_RADIO_REG, RFCU_ENABLE, 1); SetBits16(PMU_CTRL_REG, RETENTION_MODE, 0xF); if (lp_clk_sel == LP_CLK_XTAL32) { //If LP clock is XTAL32 in Boost mode set XTAL32K_CUR to 1. if (GetBits16(ANA_STATUS_REG, BOOST_SELECTED) == 0x1) SetBits16(CLK_32K_REG, XTAL32K_CUR, 1); } rf_regs(); #if LUT_PATCH_ENABLED const volatile struct LUT_CFG_struct *pLUT_CFG; // = (const volatile struct LUT_CFG_struct *)(jump_table_struct[lut_cfg_pos]); pLUT_CFG= (const volatile struct LUT_CFG_struct *)(jump_table_struct[lut_cfg_pos]); if (pLUT_CFG->HW_LUT_MODE) { SetWord16(RF_VCOCAL_CTRL_REG, vcocal_ctrl_reg_val); } #endif //LUT_PATCH_ENABLED enable_rf_diag_irq(RF_DIAG_IRQ_MODE_RXTX); // This just enables the TX_EN int. RX_EN int enable status remains as it was }
void rwip_init(uint32_t error) { #if (NVDS_SUPPORT && DEEP_SLEEP) uint8_t length = 1; uint8_t sleep_enable; uint8_t ext_wakeup_enable; #endif //NVDS_SUPPORT && DEEP_SLEEP // Reset RW environment memset(&rwip_env, 0, sizeof(rwip_env)); ke_mem_heaps_used = KE_MEM_BLOCK_MAX; #if (KE_SUPPORT) // Initialize kernel ke_init(); // Initialize memory heap used by kernel. #if (KE_MEM_RW) // Memory allocated for environment variables //ke_mem_init(KE_MEM_ENV, (uint8_t*)rwip_heap_env, RWIP_HEAP_ENV_SIZE); ke_mem_init(KE_MEM_ENV,(uint8_t*)(jump_table_struct[rwip_heap_env_pos]), jump_table_struct[rwip_heap_env_size]); #if 1//(BLE_HOST_PRESENT) // Memory allocated for Attribute database //ke_mem_init(KE_MEM_ATT_DB, (uint8_t*)rwip_heap_db, RWIP_HEAP_DB_SIZE); ke_mem_init(KE_MEM_ATT_DB,(uint8_t*)(jump_table_struct[rwip_heap_db_pos]), jump_table_struct[rwip_heap_db_size]); #endif // (BLE_HOST_PRESENT) // Memory allocated for kernel messages //ke_mem_init(KE_MEM_KE_MSG, (uint8_t*)rwip_heap_msg, RWIP_HEAP_MSG_SIZE); ke_mem_init(KE_MEM_KE_MSG,(uint8_t*)(jump_table_struct[rwip_heap_msg_pos]), jump_table_struct[rwip_heap_msg_size]); // Non Retention memory block //ke_mem_init(KE_MEM_NON_RETENTION, (uint8_t*)rwip_heap_non_ret, RWIP_HEAP_NON_RET_SIZE); ke_mem_init(KE_MEM_NON_RETENTION, (uint8_t*)(jump_table_struct[rwip_heap_non_ret_pos]), jump_table_struct[rwip_heap_non_ret_size]); #endif // (KE_MEM_RW) #endif //KE_SUPPORT #if (GTL_ITF) // Initialize the Generic Transport Layer gtl_init(rwip_eif_get(RWIP_EIF_AHI)); #endif //GTL_ITF // Initialize RF #if (BT_EMB_PRESENT || BLE_EMB_PRESENT) rf_init(&rwip_rf); SetBits32(BLE_RADIOCNTL1_REG, XRFSEL, 3); #endif //BT_EMB_PRESENT || BLE_EMB_PRESENT #if (BT_EMB_PRESENT) // Initialize BT rwbt_init(); #endif //BT_EMB_PRESENT #if (BLE_EMB_PRESENT) // Initialize BLE rwble_init(); #endif //BLE_EMB_PRESENT #if (BLE_HOST_PRESENT) // Initialize BLE Host stack rwble_hl_init(); #endif //BLE_HOST_PRESENT #if (DISPLAY_SUPPORT) // Initialize display module display_init(); // Add some configuration information to display display_add_config(); #endif //DISPLAY_SUPPORT #if (NVDS_SUPPORT && DEEP_SLEEP) // Activate deep sleep feature if enabled in NVDS if(nvds_get(NVDS_TAG_SLEEP_ENABLE, &length, &sleep_enable) == NVDS_OK) { if(sleep_enable != 0) { rwip_env.sleep_enable = true; // Set max sleep duration depending on wake-up mode if(nvds_get(NVDS_TAG_EXT_WAKEUP_ENABLE, &length, &ext_wakeup_enable) == NVDS_OK) { if(ext_wakeup_enable != 0) { //vm rwip_env.ext_wakeup_enable = true; rwip_env.ext_wakeup_enable = ext_wakeup_enable; } } } } #endif //NVDS_SUPPORT && DEEP_SLEEP // If FW initializes due to FW reset, send the message to Host if(error != RESET_NO_ERROR) { #if (BT_EMB_PRESENT && HCIC_ITF) rwbt_send_message(error); #elif (BLE_EMB_PRESENT && HCIC_ITF) rwble_send_message(error); #elif (BLE_HOST_PRESENT && GTL_ITF) rwble_hl_send_message(error); #endif //BT_EMB_PRESENT / BLE_EMB_PRESENT } /* ************************************************************************************ * Application initialization ************************************************************************************ */ // vm moved to main // if(jump_table_struct[0]==TASK_APP) // Initialize APP // app_init(); func_check_mem_flag = 0;//false; }
sleep_mode_t rwip_sleep(void) { sleep_mode_t proc_sleep = mode_active; uint32_t twirq_set_value; uint32_t twirq_reset_value; uint32_t twext_value; #if (DEEP_SLEEP) uint32_t sleep_duration = jump_table_struct[max_sleep_duration_external_wakeup_pos];//MAX_SLEEP_DURATION_EXTERNAL_WAKEUP; #endif //DEEP_SLEEP #ifndef DEVELOPMENT_DEBUG uint32_t sleep_lp_cycles; #endif DBG_SWDIAG(SLEEP, ALGO, 0); #if (BLE_APP_PRESENT) if ( app_ble_ext_wakeup_get() || (rwip_env.ext_wakeup_enable == 2) ) // sleep forever! sleep_duration = 0; #else # if (!EXTERNAL_WAKEUP) // sleep_duration will remain as it was set above.... if (rwip_env.ext_wakeup_enable == 2) sleep_duration = 0; # endif #endif do { /************************************************************************ ************** CHECK STARTUP FLAG ************** ************************************************************************/ POWER_PROFILE_INIT; // Do not allow sleep if system is in startup period if (check_sys_startup_period()) break; /************************************************************************ ************** CHECK KERNEL EVENTS ************** ************************************************************************/ // Check if some kernel processing is ongoing if (!ke_sleep_check()) break; // Processor sleep can be enabled proc_sleep = mode_idle; DBG_SWDIAG(SLEEP, ALGO, 1); #if (DEEP_SLEEP) /************************************************************************ ************** CHECK ENABLE FLAG ************** ************************************************************************/ // Check sleep enable flag if(!rwip_env.sleep_enable) break; /************************************************************************ ************** CHECK RADIO POWER DOWN ************** ************************************************************************/ // Check if BLE + Radio are still sleeping if(GetBits16(SYS_STAT_REG, RAD_IS_DOWN)) { // If BLE + Radio are in sleep return the appropriate mode for ARM proc_sleep = mode_sleeping; break; } /************************************************************************ ************** CHECK RW FLAGS ************** ************************************************************************/ // First check if no pending procedure prevents us from going to sleep if (rwip_prevent_sleep_get() != 0) break; DBG_SWDIAG(SLEEP, ALGO, 2); /************************************************************************ ************** CHECK EXT WAKEUP FLAG ************** ************************************************************************/ /* If external wakeup is enabled, sleep duration can be set to maximum, otherwise * the system must be woken-up periodically to poll incoming packets from HCI */ if((BLE_APP_PRESENT == 0) || (BLE_INTEGRATED_HOST_GTL == 1 )) // No need for periodic wakeup if we have full-hosted system { if(!rwip_env.ext_wakeup_enable) sleep_duration = jump_table_struct[max_sleep_duration_periodic_wakeup_pos]; // MAX_SLEEP_DURATION_PERIODIC_WAKEUP; } /************************************************************************ * * * CHECK DURATION UNTIL NEXT EVENT * * * ************************************************************************/ // If there's any timer pending, compute the time to wake-up to serve it if (ke_env.queue_timer.first != NULL) sleep_duration = jump_table_struct[max_sleep_duration_external_wakeup_pos]; #ifdef USE_POWER_OPTIMIZATIONS // Store sleep_duration calculated so far. Check below if sleep would be allowed. // If not, there's no reason to verify / ensure the available time for SLP... uint32_t tmp_dur = sleep_duration; #endif /************************************************************************ ************** CHECK KERNEL TIMERS ************** ************************************************************************/ // Compute the duration up to the next software timer expires if (!ke_timer_sleep_check(&sleep_duration, rwip_env.wakeup_delay)) break; DBG_SWDIAG(SLEEP, ALGO, 3); #if (BLE_EMB_PRESENT) /************************************************************************ ************** CHECK BLE ************** ************************************************************************/ // Compute the duration up to the next BLE event if (!lld_sleep_check(&sleep_duration, rwip_env.wakeup_delay)) break; #endif // BLE_EMB_PRESENT DBG_SWDIAG(SLEEP, ALGO, 4); #if (BT_EMB_PRESENT) /************************************************************************ ************** CHECK BT ************** ************************************************************************/ // Compute the duration up to the next BT active slot if (!ld_sleep_check(&sleep_duration, rwip_env.wakeup_delay)) break; #endif // BT_EMB_PRESENT DBG_SWDIAG(SLEEP, ALGO, 5); #if (HCIC_ITF) /************************************************************************ ************** CHECK HCI ************** ************************************************************************/ if((BLE_APP_PRESENT == 0) || (BLE_INTEGRATED_HOST_GTL == 1 )) { // Try to switch off HCI if (!hci_enter_sleep()) break; } #endif // HCIC_ITF #if (GTL_ITF) /************************************************************************ ************** CHECK TL ************** ************************************************************************/ if((BLE_APP_PRESENT == 0) || (BLE_INTEGRATED_HOST_GTL == 1 )) { // Try to switch off Transport Layer if (!gtl_enter_sleep()) break; } #endif // GTL_ITF DBG_SWDIAG(SLEEP, ALGO, 6); #ifdef USE_POWER_OPTIMIZATIONS /************************************************************************ ****** BLOCK UNTIL THERE'S TIME FOR sleep() AND SLP ISR ****** ************************************************************************/ uint32_t xtal16m_settling_cycles; bool rcx_duration_corr = false; // Restore sleep_duration sleep_duration = tmp_dur; /* * Wait until there's enough time for SLP to restore clocks when the chip wakes up. * Then check again if sleep is possible. */ if ( ((lp_clk_sel == LP_CLK_RCX20) && (CFG_LP_CLK == LP_CLK_FROM_OTP)) || (CFG_LP_CLK == LP_CLK_RCX20) ) { xtal16m_settling_cycles = lld_sleep_us_2_lpcycles_sel_func(XTAL16M_SETTLING_IN_USEC); while ( (ble_finetimecnt_get() < 550) && (ble_finetimecnt_get() > 200) ); // If we are close to the end of this slot then the actual sleep entry will // occur during the next one. But the sleep_duration will have been calculated // based on the current slot... if (ble_finetimecnt_get() <= 200) rcx_duration_corr = true; } else if ( ((lp_clk_sel == LP_CLK_XTAL32) && (CFG_LP_CLK == LP_CLK_FROM_OTP)) || (CFG_LP_CLK == LP_CLK_XTAL32) ) { while (ble_finetimecnt_get() < 300); } /************************************************************************ * * * CHECK DURATION UNTIL NEXT EVENT * * (this is the 2nd check) * * * ************************************************************************/ bool sleep_check = false; do { /************************************************************************ ************** CHECK KERNEL TIMERS (2) ************** ************************************************************************/ // Compute the duration up to the next software timer expires if (!ke_timer_sleep_check(&sleep_duration, rwip_env.wakeup_delay)) break; DBG_SWDIAG(SLEEP, ALGO, 3); #if (BLE_EMB_PRESENT) /************************************************************************ ************** CHECK BLE (2) ************** ************************************************************************/ // Compute the duration up to the next BLE event if (!lld_sleep_check(&sleep_duration, rwip_env.wakeup_delay)) break; #endif // BLE_EMB_PRESENT sleep_check = true; } while(0); if (!sleep_check) { if((BLE_APP_PRESENT == 0) || (BLE_INTEGRATED_HOST_GTL == 1 )) { #if BLE_HOST_PRESENT gtl_eif_init(); #else hci_eif_init(); #endif } // sleep is aborted and serial i/f communication is restored break; } if (sleep_duration && rcx_duration_corr) sleep_duration--; DBG_SWDIAG(SLEEP, ALGO, 4); #endif POWER_PROFILE_CHECKS_COMPLETED; /************************************************************************ ************** PROGRAM CORE DEEP SLEEP ************** ************************************************************************/ if ( ((lp_clk_sel == LP_CLK_RCX20) && (CFG_LP_CLK == LP_CLK_FROM_OTP)) || (CFG_LP_CLK == LP_CLK_RCX20) ) { #if !defined(USE_POWER_OPTIMIZATIONS) twirq_set_value = lld_sleep_us_2_lpcycles_sel_func(XTAL_TRIMMING_TIME_USEC); twirq_reset_value = TWIRQ_RESET_VALUE; // TWEXT setting twext_value = TWEXT_VALUE_RCX; #else // Calculate the time we need to wake-up before "time 0" to do XTAL16 settling, // call periph_init() and power-up the BLE core. uint32_t lpcycles = lld_sleep_us_2_lpcycles_sel_func(LP_ISR_TIME_USEC); // Set TWIRQ_SET taking into account that some LP cycles are needed for the power up FSM. twirq_set_value = RCX_POWER_UP_TIME + lpcycles; if (sleep_env.slp_state == ARCH_DEEP_SLEEP_ON) twirq_set_value += RCX_OTP_COPY_OVERHEAD; // BOOST mode + RCX is not supported if (GetBits16(ANA_STATUS_REG, BOOST_SELECTED) == 1) ASSERT_WARNING(0); // Program LP deassertion to occur when the XTAL16M has settled twirq_reset_value = lpcycles - xtal16m_settling_cycles; // TWEXT setting twext_value = lpcycles; #endif } else if ( ((lp_clk_sel == LP_CLK_XTAL32) && (CFG_LP_CLK == LP_CLK_FROM_OTP)) || (CFG_LP_CLK == LP_CLK_XTAL32) ) { #if !defined(USE_POWER_OPTIMIZATIONS) twirq_set_value = XTAL_TRIMMING_TIME; twirq_reset_value = TWIRQ_RESET_VALUE; twext_value = TWEXT_VALUE_XTAL32; #else // The time we need to wake-up before "time 0" to do XTAL16 settling, // call periph_init() and power-up the BLE core is LP_ISR_TIME_XTAL32_CYCLES in this case. // Set TWIRQ_SET taking into account that some LP cycles are needed for the power up FSM. twirq_set_value = XTAL32_POWER_UP_TIME + LP_ISR_TIME_XTAL32_CYCLES; if (sleep_env.slp_state == ARCH_DEEP_SLEEP_ON) twirq_set_value += XTAL32_OTP_COPY_OVERHEAD; // Adjust TWIRQ_SET in case of BOOST mode, if needed if (set_boost_low_vbat1v_overhead == APPLY_OVERHEAD) twirq_set_value += BOOST_POWER_UP_OVERHEAD; set_boost_low_vbat1v_overhead = NOT_MEASURED; // Program LP deassertion to occur when the XTAL16M has settled twirq_reset_value = LP_ISR_TIME_XTAL32_CYCLES - XTAL16M_SETTLING_IN_XTAL32_CYCLES; // TWEXT setting twext_value = LP_ISR_TIME_XTAL32_CYCLES; #endif } //Prepare BLE_ENBPRESET_REG for next sleep cycle SetBits32(BLE_ENBPRESET_REG, TWIRQ_RESET, twirq_reset_value); // TWIRQ_RESET SetBits32(BLE_ENBPRESET_REG, TWIRQ_SET, twirq_set_value); // TWIRQ_SET SetBits32(BLE_ENBPRESET_REG, TWEXT, twext_value); // TWEXT //Everything ready for sleep! proc_sleep = mode_sleeping; #ifdef USE_POWER_OPTIMIZATIONS // Eliminate any additional delays. if (sleep_duration) sleep_duration += SLEEP_DURATION_CORR; POWER_PROFILE_SLEEP_TIMES; #endif #if (BT_EMB_PRESENT) // Put BT core into deep sleep ld_sleep_enter(rwip_slot_2_lpcycles(sleep_duration), rwip_env.ext_wakeup_enable); #elif (BLE_EMB_PRESENT) // Put BT core into deep sleep if ( ((lp_clk_sel == LP_CLK_XTAL32) && (CFG_LP_CLK == LP_CLK_FROM_OTP)) || (CFG_LP_CLK == LP_CLK_XTAL32) ) sleep_lp_cycles = rwip_slot_2_lpcycles(sleep_duration); else if ( ((lp_clk_sel == LP_CLK_RCX20) && (CFG_LP_CLK == LP_CLK_FROM_OTP)) || (CFG_LP_CLK == LP_CLK_RCX20) ) sleep_lp_cycles = rwip_slot_2_lpcycles_rcx(sleep_duration); lld_sleep_enter(sleep_lp_cycles, rwip_env.ext_wakeup_enable); #endif //BT_EMB_PRESENT / BT_EMB_PRESENT DBG_SWDIAG(SLEEP, SLEEP, 1); /************************************************************************ ************** SWITCH OFF RF ************** ************************************************************************/ POWER_PROFILE_REMAINING_TIME; rwip_rf.sleep(); #ifdef USE_POWER_OPTIMIZATIONS // We may lower the clock now while we are waiting the BLE to go to sleep... bool slow_system_clk = false; #if (BLE_APP_PRESENT) if ( app_use_lower_clocks_check() ) #endif { // It will save some power if you lower the clock while waiting for STAT... SetBits16(CLK_AMBA_REG, PCLK_DIV, 3); // lowest is 2MHz (div 8, source is @16MHz) SetBits16(CLK_AMBA_REG, HCLK_DIV, 3); slow_system_clk = true; } #endif while(!ble_deep_sleep_stat_getf()); //check and wait till you may disable the radio. 32.768KHz XTAL must be running! //(debug note: use BLE_CNTL2_REG:MON_LP_CLK bit to check (write 0, should be set to 1 by the BLE)) while ( !(GetWord32(BLE_CNTL2_REG) & RADIO_PWRDN_ALLOW) ) {}; #ifdef USE_POWER_OPTIMIZATIONS if (slow_system_clk) { // and restore clock rates (refer to a couple of lines above) use_highest_amba_clocks(); } #endif ble_regs_push(); // push the ble ret.vars to retention memory // smpc_regs_push(); // push smpc ble ret.vars to retention memory //BLE CLK must be turned off when DEEP_SLEEP_STAT is set SetBits16(CLK_RADIO_REG, BLE_ENABLE, 0); #endif // DEEP_SLEEP } while(0); return proc_sleep; }
int main_func(void) { volatile unsigned i; sleep_mode_t sleep_mode; // keep at system RAM. On each while loop it will get a new value. sys_startup_flag = true; /* ************************************************************************************ * Platform initialization ************************************************************************************ */ #if (USE_WDOG) SetWord16(WATCHDOG_REG, 0xC8); // 200 * 10.24ms = ~2sec active time! SetWord16(WATCHDOG_CTRL_REG, 0); // Generate an NMI when counter reaches 0 and a WDOG (SYS) Reset when it reaches -16! // WDOG can be frozen by SW! SetWord16(RESET_FREEZE_REG, FRZ_WDOG); // Start WDOG #else SetWord16(SET_FREEZE_REG, FRZ_WDOG); #endif set_system_clocks(); GPIO_init(); periph_init(); /* Don't remove next line otherwhise dummy[0] could be optimized away * The dummy array is intended to reserve the needed Exch.Memory space in retention memory */ dummy[0] = dummy[0]; descript[0] = descript[0]; #if (BLE_CONNECTION_MAX_USER > 4) cs_table[0] = cs_table[0]; #endif /* Don't remove next line otherwhise data__1 is optimized away. * The address 0x9010 is used by the ROM code (rand.o) and cannot be used by the * application code! */ //GZ data__1 = 0; // Initialize unloaded RAM area //unloaded_area_init(); // Initialize random process srand(1); // Initialize the exchange memory interface, emi in RAM for the time being, so no init necessary #if 0 emi_init(); #endif // Initialize NVDS module nvds_init((uint8_t *)NVDS_FLASH_ADDRESS, NVDS_FLASH_SIZE); //check and read BDADDR from OTP nvds_read_bdaddr_from_otp(); #ifdef RADIO_580 iq_trim_from_otp(); #endif /* ************************************************************************************ * BLE initialization ************************************************************************************ */ init_pwr_and_clk_ble(); //diagnostic(); // rf_init(&rwip_rf); // SetBits32(BLE_RADIOCNTL1_REG, XRFSEL, 3); #if UNCALIBRATED_AT_FAB SetBits16(BANDGAP_REG, BGR_TRIM, 0x0); // trim RET Bandgap SetBits16(BANDGAP_REG, LDO_RET_TRIM, 0xA); // trim RET LDO SetWord16(RF_LNA_CTRL1_REG, 0x24E); SetWord16(RF_LNA_CTRL2_REG, 0x26); SetWord16(RF_LNA_CTRL3_REG, 0x7); SetWord16(RF_RSSI_COMP_CTRL_REG, 0x7777); SetWord16(RF_VCO_CTRL_REG, 0x1); SetBits16(CLK_16M_REG, RC16M_TRIM, 0xA); #endif // Initialize BLE stack NVIC_ClearPendingIRQ(BLE_SLP_IRQn); NVIC_ClearPendingIRQ(BLE_EVENT_IRQn); NVIC_ClearPendingIRQ(BLE_RF_DIAG_IRQn); NVIC_ClearPendingIRQ(BLE_RX_IRQn); NVIC_ClearPendingIRQ(BLE_CRYPT_IRQn); NVIC_ClearPendingIRQ(BLE_FINETGTIM_IRQn); NVIC_ClearPendingIRQ(BLE_GROSSTGTIM_IRQn); NVIC_ClearPendingIRQ(BLE_WAKEUP_LP_IRQn); rwip_init(error); /* Set spi to HW (Ble) * Necessary: So from this point the BLE HW can generate spi burst iso SW * SPI BURSTS are necessary for the radio TX and RX burst, done by hardware * beause of the accurate desired timing */ //FPGA #ifdef FPGA_USED SetBits32(BLE_CNTL2_REG,SW_RPL_SPI ,1); #endif //Enable BLE core SetBits32(BLE_RWBTLECNTL_REG,RWBLE_EN ,1); #if RW_BLE_SUPPORT && HCIC_ITF // If FW initializes due to FW reset, send the message to Host if(error != RESET_NO_ERROR) { rwble_send_message(error); } #endif /* ************************************************************************************ * Sleep mode initializations (especially for full embedded) ************************************************************************************ */ #if (EXT_SLEEP_ENABLED) app_set_extended_sleep(); #elif (DEEP_SLEEP_ENABLED) app_set_deep_sleep(); #else app_disable_sleep(); #endif if (lp_clk_sel == LP_CLK_RCX20) { calibrate_rcx20(20); read_rcx_freq(20); } /* ************************************************************************************ * Application initializations ************************************************************************************ */ #if (BLE_APP_PRESENT) { app_init(); // Initialize APP } #endif /* #if (BLE_APP_PRESENT) */ /* ************************************************************************************ * Main loop ************************************************************************************ */ lld_sleep_init_func(); SetWord16(TRIM_CTRL_REG, 0xA2); SetBits16(CLK_16M_REG, XTAL16_CUR_SET, 0x5); // // Gives 1dB higher sensitivity - UNTESTED // if (GetBits16(ANA_STATUS_REG, BOOST_SELECTED) == 0x1) // { // // Boost-mode // SetBits16(DCDC_CTRL2_REG, DCDC_CUR_LIM, 0x8); // 80mA // } // else // { // // Buck-mode // SetBits16(DCDC_CTRL2_REG, DCDC_CUR_LIM, 0x4); // 40mA // } // Now enable the TX_EN/RX_EN interrupts, depending on the RF mode of operation (PLL-LUT and MGC_KMODALPHA combinations) #if LUT_PATCH_ENABLED const volatile struct LUT_CFG_struct *pLUT_CFG; pLUT_CFG = (const volatile struct LUT_CFG_struct *)(jump_table_struct[lut_cfg_pos]); if (!pLUT_CFG->HW_LUT_MODE) { enable_rf_diag_irq(RF_DIAG_IRQ_MODE_RXTX); } else { #if MGCKMODA_PATCH_ENABLED enable_rf_diag_irq(RF_DIAG_IRQ_MODE_TXONLY); // This just enables the TX_EN int. RX_EN int enable status remains as it was #endif //MGCKMODA_PATCH_ENABLED } #else //LUT_PATCH_ENABLED #if MGCKMODA_PATCH_ENABLED enable_rf_diag_irq(RF_DIAG_IRQ_MODE_TXONLY); // This just enables the TX_EN int. RX_EN int enable status remains as it was #endif //MGCKMODA_PATCH_ENABLED #endif //LUT_PATCH_ENABLED #if BLE_APP_SPOTAR //app_spotar_exec_patch(); #endif if ( (app_get_sleep_mode() == 2) || (app_get_sleep_mode() == 1) ) { SetWord16(SET_FREEZE_REG, FRZ_WDOG); // Stop WDOG until debugger is removed if ((GetWord16(SYS_STAT_REG) & DBG_IS_UP) == DBG_IS_UP) SetBits16(SYS_CTRL_REG, DEBUGGER_ENABLE, 1); // close debugger } /* ************************************************************************************ * Watchdog ************************************************************************************ */ #if (USE_WDOG) SetWord16(WATCHDOG_REG, 0xC8); // 200 * 10.24ms active time for initialization! SetWord16(RESET_FREEZE_REG, FRZ_WDOG); // Start WDOG #endif /* ************************************************************************************ * Main loop ************************************************************************************ */ while(1) { // schedule all pending events if(GetBits16(CLK_RADIO_REG, BLE_ENABLE) == 1) { // BLE clock is enabled if(GetBits32(BLE_DEEPSLCNTL_REG, DEEP_SLEEP_STAT) == 0 && !(rwip_prevent_sleep_get() & RW_WAKE_UP_ONGOING)) { // BLE is running #ifndef FPGA_USED uint8_t ble_evt_end_set = ke_event_get(KE_EVENT_BLE_EVT_END); // BLE event end is set. conditional RF calibration can run. #endif rwip_schedule(); #ifndef FPGA_USED if (ble_evt_end_set) { uint32_t sleep_duration = 0; if (lp_clk_sel == LP_CLK_RCX20) read_rcx_freq(20); if (lld_sleep_check(&sleep_duration, 4)) //6 slots -> 3.750 ms conditionally_run_radio_cals(); // check time and temperature to run radio calibrations. } #endif #if (BLE_APP_PRESENT) if ( app_asynch_trm() ) continue; // so that rwip_schedule() is called again #endif } } #if (BLE_APP_PRESENT) // asynchronous events processing if (app_asynch_proc()) continue; // so that rwip_schedule() is called again #endif GLOBAL_INT_STOP(); #if (BLE_APP_PRESENT) app_asynch_sleep_proc(); #endif // if app has turned sleep off, rwip_sleep() will act accordingly // time from rwip_sleep() to WFI() must be kept as short as possible! sleep_mode = rwip_sleep(); // BLE is sleeping ==> app defines the mode if (sleep_mode == mode_sleeping) { if (sleep_env.slp_state == ARCH_EXT_SLEEP_ON) { sleep_mode = mode_ext_sleep; } else { sleep_mode = mode_deep_sleep; } } if (sleep_mode == mode_ext_sleep || sleep_mode == mode_deep_sleep) { SetBits16(PMU_CTRL_REG, RADIO_SLEEP, 1); // turn off radio if (jump_table_struct[nb_links_user] > 1) { if( (sleep_mode == mode_deep_sleep) && func_check_mem() && test_rxdone() && ke_mem_is_empty(KE_MEM_NON_RETENTION) ) { func_check_mem_flag = 2;//true; } else sleep_mode = mode_ext_sleep; } else { if( (sleep_mode == mode_deep_sleep) && ke_mem_is_empty(KE_MEM_NON_RETENTION) ) { func_check_mem_flag = 1;//true; } else sleep_mode = mode_ext_sleep; } #if (BLE_APP_PRESENT) // hook for app specific tasks when preparing sleeping app_sleep_prepare_proc(&sleep_mode); #endif if (sleep_mode == mode_ext_sleep || sleep_mode == mode_deep_sleep) { SCB->SCR |= 1<<2; // enable sleepdeep mode bit in System Control Register (SCR[2]=SLEEPDEEP) SetBits16(SYS_CTRL_REG, PAD_LATCH_EN, 0); // activate PAD latches SetBits16(PMU_CTRL_REG, PERIPH_SLEEP, 1); // turn off peripheral power domain if (sleep_mode == mode_ext_sleep) { SetBits16(SYS_CTRL_REG, RET_SYSRAM, 1); // retain System RAM SetBits16(SYS_CTRL_REG, OTP_COPY, 0); // disable OTP copy } else { // mode_deep_sleep #if DEVELOPMENT__NO_OTP SetBits16(SYS_CTRL_REG, RET_SYSRAM, 1); // retain System RAM #else SetBits16(SYS_CTRL_REG, RET_SYSRAM, 0); // turn System RAM off => all data will be lost! #endif otp_prepare(0x1FC0); // this is 0x1FC0 32 bits words, so 0x7F00 bytes } } SetBits16(CLK_16M_REG, XTAL16_BIAS_SH_DISABLE, 0); #if (BLE_APP_PRESENT) // hook for app specific tasks just before sleeping app_sleep_entry_proc(&sleep_mode); #endif WFI(); #if (BLE_APP_PRESENT) // hook for app specific tasks just after waking up app_sleep_exit_proc(sleep_mode); #endif // reset SCR[2]=SLEEPDEEP bit else the mode=idle WFI will cause a deep sleep // instead of a processor halt SCB->SCR &= ~(1<<2); } else if (sleep_mode == mode_idle) { #if (!BLE_APP_PRESENT) if (check_gtl_state()) { #endif WFI(); #if (!BLE_APP_PRESENT) } #endif } // restore interrupts GLOBAL_INT_START(); #if (USE_WDOG) SetWord16(WATCHDOG_REG, 0xC8); // Reset WDOG! 200 * 10.24ms active time for normal mode! #endif } }
int main_func(void) { volatile unsigned i; sleep_mode_t sleep_mode; // keep at system RAM. On each while loop it will get a new value. sys_startup_flag = true; /* ************************************************************************************ * Platform initialization ************************************************************************************ */ #if (USE_WDOG) SetWord16(WATCHDOG_REG, 0xC8); // 200 * 10.24ms = ~2sec active time! SetWord16(WATCHDOG_CTRL_REG, 0); // Generate an NMI when counter reaches 0 and a WDOG (SYS) Reset when it reaches -16! // WDOG can be frozen by SW! SetWord16(RESET_FREEZE_REG, FRZ_WDOG); // Start WDOG #else SetWord16(SET_FREEZE_REG, FRZ_WDOG); #endif #if defined(CFG_USE_DEFAULT_XTAL16M_TRIM_VALUE_IF_NOT_CALIBRATED) #define DEFAULT_XTAL16M_TRIM_VALUE (1302) // Apply the default XTAL16 trim value if a trim value has not been programmed in OTP if ( 0 == GetWord16(CLK_FREQ_TRIM_REG) ) { SetBits16(CLK_16M_REG, RC16M_ENABLE, 1); // enable RC 16MHz for (volatile int i = 0; i < 20; i++); SetBits16(CLK_CTRL_REG, SYS_CLK_SEL, 1); // switch to RC16 while( (GetWord16(CLK_CTRL_REG) & RUNNING_AT_RC16M) == 0 ); // wait for actual switch SetBits16(CLK_CTRL_REG, XTAL16M_DISABLE, 1); // disable XTAL16 SetWord16(CLK_FREQ_TRIM_REG, DEFAULT_XTAL16M_TRIM_VALUE); // set default trim value SetBits16(CLK_CTRL_REG, XTAL16M_DISABLE, 0); // enable XTAL16 while( (GetWord16(SYS_STAT_REG) & XTAL16_SETTLED) == 0 ); // wait for XTAL16 settle SetBits16(CLK_CTRL_REG , SYS_CLK_SEL ,0); // switch to XTAL16 while( (GetWord16(CLK_CTRL_REG) & RUNNING_AT_XTAL16M) == 0 ); // wait for actual switch } #endif set_system_clocks(); GPIO_init(); periph_init(); /* Don't remove next line otherwhise dummy[0] could be optimized away * The dummy array is intended to reserve the needed Exch.Memory space in retention memory */ dummy[0] = dummy[0]; descript[0] = descript[0]; #ifndef __DA14581__ #if (BLE_CONNECTION_MAX_USER > 4) cs_table[0] = cs_table[0]; #endif #else #if (BLE_CONNECTION_MAX_USER > 1) cs_table[0] = cs_table[0]; #endif #endif /* Don't remove next line otherwhise data__1 is optimized away. * The address 0x9010 is used by the ROM code (rand.o) and cannot be used by the * application code! */ //GZ data__1 = 0; // Initialize unloaded RAM area //unloaded_area_init(); // Initialize random process srand(1); // Initialize the exchange memory interface, emi in RAM for the time being, so no init necessary #if 0 emi_init(); #endif // Initialize NVDS module // 初始化非易失性存储器 nvds_init((uint8_t *)NVDS_FLASH_ADDRESS, NVDS_FLASH_SIZE); //check and read BDADDR from OTP nvds_read_bdaddr_from_otp(); #ifdef RADIO_580 iq_trim_from_otp(); #endif /* ************************************************************************************ * BLE initialization ************************************************************************************ */ init_pwr_and_clk_ble(); //diagnostic(); // rf_init(&rwip_rf); // SetBits32(BLE_RADIOCNTL1_REG, XRFSEL, 3); #if UNCALIBRATED_AT_FAB SetBits16(BANDGAP_REG, BGR_TRIM, 0x0); // trim RET Bandgap SetBits16(BANDGAP_REG, LDO_RET_TRIM, 0xA); // trim RET LDO SetWord16(RF_LNA_CTRL1_REG, 0x24E); SetWord16(RF_LNA_CTRL2_REG, 0x26); SetWord16(RF_LNA_CTRL3_REG, 0x7); SetWord16(RF_VCO_CTRL_REG, 0x1); SetBits16(CLK_16M_REG, RC16M_TRIM, 0xA); #endif // Initialize BLE stack NVIC_ClearPendingIRQ(BLE_SLP_IRQn); NVIC_ClearPendingIRQ(BLE_EVENT_IRQn); NVIC_ClearPendingIRQ(BLE_RF_DIAG_IRQn); NVIC_ClearPendingIRQ(BLE_RX_IRQn); NVIC_ClearPendingIRQ(BLE_CRYPT_IRQn); NVIC_ClearPendingIRQ(BLE_FINETGTIM_IRQn); NVIC_ClearPendingIRQ(BLE_GROSSTGTIM_IRQn); NVIC_ClearPendingIRQ(BLE_WAKEUP_LP_IRQn); rwip_init(error); #if ((BLE_APP_PRESENT == 0 || BLE_INTEGRATED_HOST_GTL == 1) && BLE_HOST_PRESENT ) patch_gtl_task(); #endif // #if (BLE_APP_PRESENT == 0 || BLE_INTEGRATED_HOST_GTL == 1) /* Set spi to HW (Ble) * Necessary: So from this point the BLE HW can generate spi burst iso SW * SPI BURSTS are necessary for the radio TX and RX burst, done by hardware * beause of the accurate desired timing */ //FPGA #ifdef FPGA_USED SetBits32(BLE_CNTL2_REG,SW_RPL_SPI ,1); #endif //Enable BLE core SetBits32(BLE_RWBTLECNTL_REG,RWBLE_EN ,1); #if RW_BLE_SUPPORT && HCIC_ITF // If FW initializes due to FW reset, send the message to Host if(error != RESET_NO_ERROR) { rwble_send_message(error); } #endif /* ************************************************************************************ * Sleep mode initializations (especially for full embedded) ************************************************************************************ */ #if (EXT_SLEEP_ENABLED) app_set_extended_sleep(); #elif (DEEP_SLEEP_ENABLED) app_set_deep_sleep(); #else app_disable_sleep(); #endif if (lp_clk_sel == LP_CLK_RCX20) { calibrate_rcx20(20); read_rcx_freq(20); } /* ************************************************************************************ * Application initializations ************************************************************************************ */ #if (BLE_APP_PRESENT) { app_init(); // Initialize APP // 初始化应用程序 } #endif /* #if (BLE_APP_PRESENT) */ /* ************************************************************************************ * Main loop ************************************************************************************ */ lld_sleep_init_func(); SetWord16(TRIM_CTRL_REG, 0xA2); SetBits16(CLK_16M_REG, XTAL16_CUR_SET, 0x5); // // Gives 1dB higher sensitivity - UNTESTED // if (GetBits16(ANA_STATUS_REG, BOOST_SELECTED) == 0x1) // { // // Boost-mode // SetBits16(DCDC_CTRL2_REG, DCDC_CUR_LIM, 0x8); // 80mA // } // else // { // // Buck-mode // SetBits16(DCDC_CTRL2_REG, DCDC_CUR_LIM, 0x4); // 40mA // } // Now enable the TX_EN/RX_EN interrupts, depending on the RF mode of operation (PLL-LUT and MGC_KMODALPHA combinations) enable_rf_diag_irq(RF_DIAG_IRQ_MODE_RXTX); #if BLE_APP_SPOTAR // 打补丁 //app_spotar_exec_patch(); #endif if ( (app_get_sleep_mode() == 2) || (app_get_sleep_mode() == 1) ) { SetWord16(SET_FREEZE_REG, FRZ_WDOG); // Stop WDOG until debugger is removed while ((GetWord16(SYS_STAT_REG) & DBG_IS_UP) == DBG_IS_UP) {}; SetBits16(SYS_CTRL_REG, DEBUGGER_ENABLE, 0); // close debugger } /* ************************************************************************************ * Watchdog ************************************************************************************ */ #if (USE_WDOG) SetWord16(WATCHDOG_REG, 0xC8); // 200 * 10.24ms active time for initialization! SetWord16(RESET_FREEZE_REG, FRZ_WDOG); // Start WDOG #endif #if (STREAMDATA_QUEUE) stream_fifo_init (); #endif /* ************************************************************************************ * Main loop ************************************************************************************ */ // 设置LED电亮 SetWord16(P10_MODE_REG,0x310); SetWord16(P11_MODE_REG,0x300); //SetWord16(P1_DATA_REG,~(GetWord16(P1_DATA_REG)) | 0xfd); //SetWord16(P10_MODE_REG,0x300); // // 定时器时钟使能 // SetWord16(CLK_PER_REG, 0x0008); // // // SetWord16(TIMER0_CTRL_REG, 0x0e); // SetWord16(TIMER0_ON_REG, 65535); // SetWord16(TIMER0_RELOAD_M_REG, 10000); // SetWord16(TIMER0_RELOAD_N_REG, 5000); // SetWord16(TIMER0_CTRL_REG, TIMER0_CTRL_REG | 0x01); // NVIC_SetPriority(SWTIM_IRQn,254); // NVIC_EnableIRQ(SWTIM_IRQn); while(1) { // schedule all pending events if(GetBits16(CLK_RADIO_REG, BLE_ENABLE) == 1) { // BLE clock is enabled if(GetBits32(BLE_DEEPSLCNTL_REG, DEEP_SLEEP_STAT) == 0 && !(rwip_prevent_sleep_get() & RW_WAKE_UP_ONGOING)) { // BLE is running #ifndef FPGA_USED uint8_t ble_evt_end_set = ke_event_get(KE_EVENT_BLE_EVT_END); // BLE event end is set. conditional RF calibration can run. #endif rwip_schedule(); // 调度 aiwesky 20101003 #ifndef FPGA_USED if (ble_evt_end_set) { uint32_t sleep_duration = 0; if (lp_clk_sel == LP_CLK_RCX20) read_rcx_freq(20); if (lld_sleep_check(&sleep_duration, 4)) //6 slots -> 3.750 ms conditionally_run_radio_cals(); // check time and temperature to run radio calibrations. } #endif #if (BLE_APP_PRESENT) if ( app_asynch_trm() ) continue; // so that rwip_schedule() is called again #endif #ifdef CFG_PRINTF { arch_printf_process(); } #endif } } #if (BLE_APP_PRESENT) // asynchronous events processing if (app_asynch_proc()) continue; // so that rwip_schedule() is called again #endif #if (STREAMDATA_QUEUE) if (stream_queue_more_data( )) continue; #endif #if (!BLE_APP_PRESENT) if (check_gtl_state()) #endif { GLOBAL_INT_STOP(); #if (BLE_APP_PRESENT) app_asynch_sleep_proc(); #endif // // set wake-up delay only for RCX (to cover small frequency shifts due to temerature variation) // if (lp_clk_sel == LP_CLK_RCX20) // set_sleep_delay(); // if app has turned sleep off, rwip_sleep() will act accordingly // time from rwip_sleep() to WFI() must be kept as short as possible! sleep_mode = rwip_sleep(); // 读取休眠模式 // BLE is sleeping ==> app defines the mode if (sleep_mode == mode_sleeping) { if (sleep_env.slp_state == ARCH_EXT_SLEEP_ON) { sleep_mode = mode_ext_sleep; } else { sleep_mode = mode_deep_sleep; } } if (sleep_mode == mode_ext_sleep || sleep_mode == mode_deep_sleep) { SetBits16(PMU_CTRL_REG, RADIO_SLEEP, 1); // turn off radio if (jump_table_struct[nb_links_user] > 1) { if( (sleep_mode == mode_deep_sleep) && func_check_mem() && test_rxdone() && ke_mem_is_empty(KE_MEM_NON_RETENTION) ) { func_check_mem_flag = 2;//true; } else sleep_mode = mode_ext_sleep; } else { if( (sleep_mode == mode_deep_sleep) && ke_mem_is_empty(KE_MEM_NON_RETENTION) ) { func_check_mem_flag = 1;//true; } else sleep_mode = mode_ext_sleep; } #if (BLE_APP_PRESENT) // hook for app specific tasks when preparing sleeping app_sleep_prepare_proc(&sleep_mode); #endif if (sleep_mode == mode_ext_sleep || sleep_mode == mode_deep_sleep) { SCB->SCR |= 1<<2; // enable sleepdeep mode bit in System Control Register (SCR[2]=SLEEPDEEP) SetBits16(SYS_CTRL_REG, PAD_LATCH_EN, 0); // activate PAD latches SetBits16(PMU_CTRL_REG, PERIPH_SLEEP, 1); // turn off peripheral power domain if (sleep_mode == mode_ext_sleep) { SetBits16(SYS_CTRL_REG, RET_SYSRAM, 1); // retain System RAM SetBits16(SYS_CTRL_REG, OTP_COPY, 0); // disable OTP copy } else { // mode_deep_sleep #if DEVELOPMENT_DEBUG SetBits16(SYS_CTRL_REG, RET_SYSRAM, 1); // retain System RAM #else SetBits16(SYS_CTRL_REG, RET_SYSRAM, 0); // turn System RAM off => all data will be lost! #endif otp_prepare(0x1FC0); // this is 0x1FC0 32 bits words, so 0x7F00 bytes } } SetBits16(CLK_16M_REG, XTAL16_BIAS_SH_DISABLE, 0); #if (BLE_APP_PRESENT) // hook for app specific tasks just before sleeping app_sleep_entry_proc(&sleep_mode); #endif #if ((EXTERNAL_WAKEUP) && (!BLE_APP_PRESENT)) // external wake up, only in external processor designs ext_wakeup_enable(EXTERNAL_WAKEUP_GPIO_PORT, EXTERNAL_WAKEUP_GPIO_PIN, EXTERNAL_WAKEUP_GPIO_POLARITY); #endif WFI(); // 暂停执行直到事件发生 aiwesky 20151003 #if (BLE_APP_PRESENT) // hook for app specific tasks just after waking up app_sleep_exit_proc(sleep_mode); #endif #if ((EXTERNAL_WAKEUP) && (!BLE_APP_PRESENT)) // external wake up, only in external processor designs // Disable external wakeup interrupt ext_wakeup_disable(); #endif // reset SCR[2]=SLEEPDEEP bit else the mode=idle WFI will cause a deep sleep // instead of a processor halt SCB->SCR &= ~(1<<2); } else if (sleep_mode == mode_idle) { #if (!BLE_APP_PRESENT) if (check_gtl_state()) #endif { WFI(); } } // restore interrupts GLOBAL_INT_START(); } #if (USE_WDOG) SetWord16(WATCHDOG_REG, 0xC8); // Reset WDOG! 200 * 10.24ms active time for normal mode! #endif } }
/** **************************************************************************************** * @brief Initialisation of ble core, pwr and clk * * The Hclk and Pclk are set **************************************************************************************** */ void init_pwr_and_clk_ble(void) { SetBits16(CLK_RADIO_REG, BLE_DIV, 0); SetBits16(CLK_RADIO_REG, BLE_ENABLE, 1); SetBits16(CLK_RADIO_REG, RFCU_DIV, 1); SetBits16(CLK_RADIO_REG, RFCU_ENABLE, 1); /* * Power up BLE core & reset BLE Timers */ SetBits16(CLK_32K_REG, RC32K_ENABLE, 1); SetBits16(SYS_CTRL_REG, CLK32_SOURCE, 0); SetBits16(CLK_RADIO_REG, BLE_LP_RESET, 1); SetBits16(PMU_CTRL_REG, RADIO_SLEEP, 0); while (!(GetWord16(SYS_STAT_REG) & RAD_IS_UP)); // Just wait for radio to truely wake up select_lp_clk(); if ( ((lp_clk_sel == LP_CLK_XTAL32) && (CFG_LP_CLK == LP_CLK_FROM_OTP)) || (CFG_LP_CLK == LP_CLK_XTAL32) ) { SetBits16(CLK_32K_REG, XTAL32K_ENABLE, 1); // Enable XTAL32KHz // Disable XTAL32 amplitude regulation in BOOST mode if (GetBits16(ANA_STATUS_REG, BOOST_SELECTED) == 0x1) SetBits16(CLK_32K_REG, XTAL32K_DISABLE_AMPREG, 1); else SetBits16(CLK_32K_REG, XTAL32K_DISABLE_AMPREG, 0); SetBits16(CLK_32K_REG, XTAL32K_CUR, 5); SetBits16(CLK_32K_REG, XTAL32K_RBIAS, 3); SetBits16(SYS_CTRL_REG, CLK32_SOURCE, 1); // Select XTAL32K as LP clock } else if ( ((lp_clk_sel == LP_CLK_RCX20) && (CFG_LP_CLK == LP_CLK_FROM_OTP)) || (CFG_LP_CLK == LP_CLK_RCX20) ) { SetBits16(CLK_RCX20K_REG, RCX20K_NTC, 0xB); SetBits16(CLK_RCX20K_REG, RCX20K_BIAS, 1); SetBits16(CLK_RCX20K_REG, RCX20K_TRIM, 0); SetBits16(CLK_RCX20K_REG, RCX20K_LOWF, 1); SetBits16(CLK_RCX20K_REG, RCX20K_ENABLE, 1); SetBits16(CLK_RCX20K_REG, RCX20K_SELECT, 1); SetBits16(SYS_CTRL_REG, CLK32_SOURCE, 0); SetBits16(CLK_32K_REG, XTAL32K_ENABLE, 0); // Disable Xtal32KHz } else ASSERT_WARNING(0); SetBits16(CLK_32K_REG, RC32K_ENABLE, 0); // Disable RC32KHz SetBits16(CLK_RADIO_REG, BLE_LP_RESET, 0); if (GetBits16(ANA_STATUS_REG, BOOST_SELECTED) == 0x1) SetWord16(DCDC_CTRL3_REG, 0x5); /* * Just make sure that BLE core is stopped (if already running) */ SetBits32(BLE_RWBTLECNTL_REG, RWBLE_EN, 0); /* * Since BLE is stopped (and powered), set CLK_SEL */ SetBits32(BLE_CNTL2_REG, BLE_CLK_SEL, 16); SetBits32(BLE_CNTL2_REG, BLE_RSSI_SEL, 1); }
void rf_init_func(struct rwip_rf_api *api) { uint32 tmp32 = 0; uint8 idx = 0; uint8 temp_freq_tbl[EM_BLE_FREQ_TABLE_LEN]; // Initialize the RF driver API structure api->reg_rd = rf_reg_rd; api->reg_wr = rf_reg_wr; api->txpwr_dbm_get = rf_txpwr_dbm_get; //api->txpwr_max = RPL_POWER_MAX; api->sleep = rf_sleep; api->reset = rf_reset; #ifdef CFG_BLE api->isr = RADIOCNTL_Handler; api->force_agc_enable = rf_force_agc_enable; #endif //CFG_BLE api->rssi_convert = rf_rssi_convert; #ifdef CFG_BT api->txpwr_inc = rf_txpwr_inc; api->txpwr_dec = rf_txpwr_dec; api->txpwr_epc_req = rf_txpwr_epc_req; api->txpwr_cs_get = rf_txpwr_cs_get; api->rssi_high_thr = (uint8_t)RPL_RSSI_20dB_THRHLD; api->rssi_low_thr = (uint8_t)RPL_RSSI_60dB_THRHLD; api->rssi_interf_thr = (uint8_t)RPL_RSSI_70dB_THRHLD; #ifdef CFG_BTCORE_30 api->wakeup_delay = RPL_WK_UP_DELAY; #endif //CFG_BTCORE_30 api->skew = RPL_RADIO_SKEW; #endif //CFG_BT // CLK_FREQ_TRIM_REG initialization was moved to main_func() in arch_main.c // The initialization of this register is done by the Boot ROM code if a valid // value has been written to the corresponding position in the OTP header by // the customer. // main_func() will write this register with a default value and the customer // must remove this code when he has written the OTP header. SetBits32(&tmp32, RTRIP_DELAY, 7); SetBits32(&tmp32, TXPWRDN, 0x5); SetBits32(&tmp32, RXPWRUP, RXPWRUP_VAL); SetBits32(&tmp32, TXPWRUP, TXPWRUP_VAL); SetWord32(BLE_RADIOPWRUPDN_REG,tmp32); SetBits32(BLE_RADIOCNTL0_REG, DPCORR_EN, 0); //THIS MAY NOT BE '1', THEN WE MISS 12 BITS IN THE SYNCWORD DURING A RX BURST SetBits32(BLE_RADIOCNTL1_REG, XRFSEL, 3); SetBits32(BLE_CNTL2_REG, SW_RPL_SPI ,0); SetBits32(BLE_CNTL2_REG, BB_ONLY,0); while(idx < EM_BLE_FREQ_TABLE_LEN) { temp_freq_tbl[idx] = idx ; idx++; } em_ble_burst_wr(&temp_freq_tbl[0], EM_BLE_FT_OFFSET, EM_BLE_FREQ_TABLE_LEN); rf_regs(); last_temp_count = get_rc16m_count(); #if LUT_PATCH_ENABLED pll_vcocal_LUT_InitUpdate(LUT_INIT); #endif rf_calibration(); }
/** **************************************************************************************** * @brief Initialisation of ble core, pwr and clk * * The Hclk and Pclk are set **************************************************************************************** */ void init_pwr_and_clk_ble(void) { SetBits16(CLK_RADIO_REG, BLE_DIV, 0); SetBits16(CLK_RADIO_REG, BLE_ENABLE, 1); SetBits16(CLK_RADIO_REG, RFCU_DIV, 1); SetBits16(CLK_RADIO_REG, RFCU_ENABLE, 1); /* * Power up BLE core & reset BLE Timers */ SetBits16(CLK_32K_REG, RC32K_ENABLE, 1); SetBits16(SYS_CTRL_REG, CLK32_SOURCE, 0); SetBits16(CLK_RADIO_REG, BLE_LP_RESET, 1); SetBits16(PMU_CTRL_REG, RADIO_SLEEP, 0); while (!(GetWord16(SYS_STAT_REG) & RAD_IS_UP)); // Just wait for radio to truely wake up select_lp_clk(); if (lp_clk_sel == LP_CLK_XTAL32) { SetBits16(CLK_32K_REG, XTAL32K_ENABLE, 1); // Enable XTAL32KHz // Disable XTAL32 amplitude regulation in BOOST mode if (GetBits16(ANA_STATUS_REG, BOOST_SELECTED) == 0x1) SetBits16(CLK_32K_REG, XTAL32K_DISABLE_AMPREG, 1); else SetBits16(CLK_32K_REG, XTAL32K_DISABLE_AMPREG, 0); SetBits16(CLK_32K_REG, XTAL32K_CUR, 5); SetBits16(CLK_32K_REG, XTAL32K_RBIAS, 3); SetBits16(SYS_CTRL_REG, CLK32_SOURCE, 1); // Select XTAL32K as LP clock } else if (lp_clk_sel == LP_CLK_RCX20) { SetBits16(CLK_RCX20K_REG, RCX20K_NTC, 0xB); SetBits16(CLK_RCX20K_REG, RCX20K_BIAS, 1); SetBits16(CLK_RCX20K_REG, RCX20K_TRIM, 0); SetBits16(CLK_RCX20K_REG, RCX20K_LOWF, 1); SetBits16(CLK_RCX20K_REG, RCX20K_ENABLE, 1); SetBits16(CLK_RCX20K_REG, RCX20K_SELECT, 1); SetBits16(SYS_CTRL_REG, CLK32_SOURCE, 0); } SetBits16(CLK_32K_REG, RC32K_ENABLE, 0); // Disable RC32KHz SetBits16(CLK_RADIO_REG, BLE_LP_RESET, 0); if (GetBits16(ANA_STATUS_REG, BOOST_SELECTED) == 0x1) SetWord16(DCDC_CTRL3_REG, 0x5); /* * Just make sure that BLE core is stopped (if already running) */ SetBits32(BLE_RWBTLECNTL_REG, RWBLE_EN, 0); /* * Since BLE is stopped (and powered), set CLK_SEL */ SetBits32(BLE_CNTL2_REG, BLE_CLK_SEL, 16); SetBits32(BLE_CNTL2_REG, BLE_RSSI_SEL, 1); /* * Set spi interface to software */ #ifdef FPGA_USED // the following 2 lines are for FPGA implementation SetBits32(BLE_CNTL2_REG, SW_RPL_SPI, 0); SetBits32(BLE_CNTL2_REG, BB_ONLY, 1); #endif }