static int Audio_mrgrx_Volume_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { mmrgrx_Volume = ucontrol->value.integer.value[0]; printk("%s mmrgrx_Volume = 0x%x \n", __func__, mmrgrx_Volume); if (GetMemoryPathEnable(Soc_Aud_Digital_Block_MRG_I2S_OUT) == true) { SetHwDigitalGain(mmrgrx_Volume, Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN1); } return 0; }
static int mtk_pcm_mrgrx_prepare(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; printk("%s rate = %d\n", __func__, runtime->rate); if (mPrepareDone == false) { #ifndef DENALI_FPGA_EARLYPORTING mtk_wcn_cmb_stub_audio_ctrl((CMB_STUB_AIF_X)CMB_STUB_AIF_3); #endif // interconnection setting SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I15, Soc_Aud_InterConnectionOutput_O13); SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I16, Soc_Aud_InterConnectionOutput_O14); SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I10, Soc_Aud_InterConnectionOutput_O03); SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I11, Soc_Aud_InterConnectionOutput_O04); // Set HW_GAIN SetHwDigitalGainMode(Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN1, runtime->rate, 0x40); SetHwDigitalGainEnable(Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN1, true); SetHwDigitalGain(mmrgrx_Volume, Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN1); // start I2S DAC out if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC) == false) { SetI2SDacOut(runtime->rate,false, Soc_Aud_I2S_WLEN_WLEN_16BITS); SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true); SetI2SDacEnable(true); } else { SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true); } if (GetMemoryPathEnable(Soc_Aud_Digital_Block_MRG_I2S_OUT) == false) { //set merge interface SetMemoryPathEnable(Soc_Aud_Digital_Block_MRG_I2S_OUT, true); SetMrgI2SEnable(true, runtime->rate); } else { SetMemoryPathEnable(Soc_Aud_Digital_Block_MRG_I2S_OUT, true); } EnableAfe(true); mPrepareDone = true; } return 0; }
static int Audio_i2s0_SideGen_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { uint32 u32AudioI2S = 0, MclkDiv0, MclkDiv3, REG448 = 0, REG44C = 0; uint32 samplerate = 0; AudDrv_Clk_On(); printk("%s() mi2s0_hdoutput_control = %d\n", __func__, mi2s0_hdoutput_control); if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(i2s0_SIDEGEN)) { printk("return -EINVAL\n"); return -EINVAL; } mi2s0_sidegen_control = ucontrol->value.integer.value[0]; if (mi2s0_sidegen_control == 1) { samplerate = 48000; } else if (mi2s0_sidegen_control == 2) { samplerate = 44100; } else if (mi2s0_sidegen_control == 3) { samplerate = 32000; } else if (mi2s0_sidegen_control == 4) { samplerate = 16000; // here start digital part SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I14, Soc_Aud_InterConnectionOutput_O00); SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I14, Soc_Aud_InterConnectionOutput_O01); } else if (mi2s0_sidegen_control == 5) { samplerate = 8000; // here start digital part SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I14, Soc_Aud_InterConnectionOutput_O00); SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I14, Soc_Aud_InterConnectionOutput_O01); } else if (mi2s0_sidegen_control == 6) { samplerate = 16000; // here start digital part SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I14, Soc_Aud_InterConnectionOutput_O00); SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I14, Soc_Aud_InterConnectionOutput_O01); printk("%s() Soc_Aud_InterCon_Connection I01 O14\n", __func__); //phone call echo reference connection: I0/I1->O13/O14(HW Gain1)->I11 ->O24 SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I01, Soc_Aud_InterConnectionOutput_O14);//0x448, 0x10000 REG448 = Afe_Get_Reg(AFE_GAIN1_CONN2); printk("%s() AFE_GAIN1_CONN2 (0X448) =0x%x\n", __func__, REG448); printk("%s() Soc_Aud_InterCon_Connection I11 O24\n", __func__); SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I11, Soc_Aud_InterConnectionOutput_O24);//0x44c, 0x8 REG44C = Afe_Get_Reg(AFE_GAIN1_CONN3); printk("%s() AFE_GAIN1_CONN3 (0X44C) =0x%x\n", __func__, REG44C); // Set HW_GAIN1 SetHwDigitalGainMode(Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN1, samplerate, 0x80); SetHwDigitalGainEnable(Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN1, true); SetHwDigitalGain(0x80000, Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN1); Afe_Set_Reg(AFE_DAC_CON1, 0x400, 0xF00); } if (mi2s0_sidegen_control != 0) { printk("%s() mi2s0_sidegen_control=%d, mi2s0_hdoutput_control=%d\n", __func__, mi2s0_sidegen_control, mi2s0_hdoutput_control); AudDrv_Clk_On(); Afe_Set_Reg(AUDIO_TOP_CON1, 0x2, 0x2); // I2S_SOFT_Reset Afe_Set_Reg(AUDIO_TOP_CON1, 0x1 << 4, 0x1 << 4); // I2S_SOFT_Reset uint32 Audio_I2S_Dac = 0; SetSampleRate(Soc_Aud_Digital_Block_MEM_I2S, samplerate); Audio_I2S_Dac |= (Soc_Aud_LR_SWAP_NO_SWAP << 31); // Audio_I2S_Dac |= (Soc_Aud_INV_BCK_INVESE << 29);//BCK Inv Audio_I2S_Dac |= (Soc_Aud_I2S_IN_PAD_SEL_I2S_IN_FROM_IO_MUX << 28);//I2S in from io_mux Audio_I2S_Dac |= (Soc_Aud_INV_LRCK_NO_INVERSE << 5); Audio_I2S_Dac |= (Soc_Aud_I2S_FORMAT_I2S << 3); Audio_I2S_Dac |= (Soc_Aud_I2S_WLEN_WLEN_32BITS << 1); u32AudioI2S = SampleRateTransform(samplerate) << 8; u32AudioI2S |= Soc_Aud_I2S_FORMAT_I2S << 3; // us3 I2s format u32AudioI2S |= Soc_Aud_I2S_WLEN_WLEN_32BITS << 1; // 32 BITS if (mi2s0_hdoutput_control == true) { printk("%s() mi2s0_sidegen_control = %d set low jitter\n", __func__, mi2s0_sidegen_control); MclkDiv0 = SetCLkMclk(Soc_Aud_I2S0, samplerate); //select I2S SetCLkBclk(MclkDiv0, samplerate, 2, Soc_Aud_I2S_WLEN_WLEN_32BITS); MclkDiv3 = SetCLkMclk(Soc_Aud_I2S3, samplerate); //select I2S SetCLkBclk(MclkDiv3, samplerate, 2, Soc_Aud_I2S_WLEN_WLEN_32BITS); u32AudioI2S |= Soc_Aud_LOW_JITTER_CLOCK << 12 ; //Low jitter mode Audio_I2S_Dac |= Soc_Aud_LOW_JITTER_CLOCK << 12 ; //Low jitter mode } else { printk("%s() mi2s0_sidegen_control = %d NOT set low jitter\n", __func__, mi2s0_sidegen_control); u32AudioI2S &= ~(Soc_Aud_LOW_JITTER_CLOCK << 12) ; Audio_I2S_Dac &= ~(Soc_Aud_LOW_JITTER_CLOCK << 12) ; } // start I2S DAC out if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2) == false) { printk("%s(), mi2s0_sidegen_control=%d, write AFE_I2S_CON (0x%x), AFE_I2S_CON3(0x%x)\n", __func__, mi2s0_sidegen_control, Audio_I2S_Dac, u32AudioI2S); Afe_Set_Reg(AFE_I2S_CON, 0x0, 0x1); SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2, true); Afe_Set_Reg(AFE_I2S_CON, Audio_I2S_Dac | 0x1, MASK_ALL); Afe_Set_Reg(AFE_I2S_CON3, u32AudioI2S | 1, AFE_MASK_ALL); Afe_Set_Reg(AUDIO_TOP_CON1, 0x0 << 4, 0x1 << 4); Afe_Set_Reg(AUDIO_TOP_CON1, 0x0, 0x2); // I2S_SOFT_Reset EnableAfe(true); } else { printk("%s(), mi2s0_sidegen_control=%d, write AFE_I2S_CON (0x%x), AFE_I2S_CON3(0x%x)\n", __func__, mi2s0_sidegen_control, Audio_I2S_Dac, u32AudioI2S); Afe_Set_Reg(AFE_I2S_CON, 0x0, 0x1); SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2, true); Afe_Set_Reg(AFE_I2S_CON, Audio_I2S_Dac | 0x1, MASK_ALL); Afe_Set_Reg(AFE_I2S_CON3, u32AudioI2S | 1, AFE_MASK_ALL); Afe_Set_Reg(AUDIO_TOP_CON1, 0x0 << 4, 0x1 << 4); Afe_Set_Reg(AUDIO_TOP_CON1, 0x0, 0x2); // I2S_SOFT_Reset EnableAfe(true); } } else { SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2, false); if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2) == false) { if (mi2s0_hdoutput_control == true) { Afe_Set_Reg(AFE_I2S_CON3, 0, 1 << 12); //Clear Low jitter mode setting } Afe_Set_Reg(AFE_I2S_CON3, 0x0, 0x1); Afe_Set_Reg(AFE_I2S_CON, 0x0, 0x1); SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I14, Soc_Aud_InterConnectionOutput_O00); SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I14, Soc_Aud_InterConnectionOutput_O01); EnableAfe(false); } AudDrv_Clk_Off(); } AudDrv_Clk_Off(); return 0; }
static int mtk_pcm_fm_i2s_prepare(struct snd_pcm_substream *substream) { AudioDigtalI2S m2ndI2SInAttribute; struct snd_pcm_runtime *runtime = substream->runtime; printk("%s rate = %d\n", __func__, runtime->rate); if (mPrepareDone == false) { //mtk_wcn_cmb_stub_audio_ctrl((CMB_STUB_AIF_X)CMB_STUB_AIF_3);//temp mark for early porting // interconnection setting SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I00, Soc_Aud_InterConnectionOutput_O13); SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I01, Soc_Aud_InterConnectionOutput_O14); SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I10, Soc_Aud_InterConnectionOutput_O03); SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I11, Soc_Aud_InterConnectionOutput_O04); ///<<<lenovo-sw, fangzf1 @2015-06-11 for fm SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I10, Soc_Aud_InterConnectionOutput_O00); SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I11, Soc_Aud_InterConnectionOutput_O01); ///lenovo-sw, fangzf1 @2015-06-11 for fm>>> // Set HW_GAIN SetHwDigitalGainMode(Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN1, runtime->rate, 0x40); SetHwDigitalGainEnable(Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN1, true); SetHwDigitalGain(mfm_i2s_Volume, Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN1); // start I2S DAC out if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC) == false) { SetI2SDacOut(runtime->rate,false,Soc_Aud_I2S_WLEN_WLEN_16BITS); SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true); SetI2SDacEnable(true); } else { SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true); } if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_2) == false) { //set merge interface SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_2, true); // Config 2nd I2S IN memset((void *)&m2ndI2SInAttribute, 0, sizeof(m2ndI2SInAttribute)); m2ndI2SInAttribute.mLR_SWAP = Soc_Aud_LR_SWAP_NO_SWAP; m2ndI2SInAttribute.mI2S_IN_PAD_SEL = false; // I2S_IN_FROM_CONNSYS m2ndI2SInAttribute.mI2S_SLAVE = Soc_Aud_I2S_SRC_SLAVE_MODE; m2ndI2SInAttribute.mI2S_SAMPLERATE = 32000; m2ndI2SInAttribute.mINV_LRCK = Soc_Aud_INV_LRCK_NO_INVERSE; m2ndI2SInAttribute.mI2S_FMT = Soc_Aud_I2S_FORMAT_I2S; m2ndI2SInAttribute.mI2S_WLEN = Soc_Aud_I2S_WLEN_WLEN_16BITS; Set2ndI2SIn(&m2ndI2SInAttribute); if (runtime->rate == 48000) SetI2SASRCConfig(true, 48000); /* Covert from 32000 Hz to 48000 Hz */ else SetI2SASRCConfig(true, 44100); /* Covert from 32000 Hz to 44100 Hz */ SetI2SASRCEnable(true); Set2ndI2SInEnable(true); } else { SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_2, true); } EnableAfe(true); mPrepareDone = true; } return 0; }