int main (int argc, char **argv) { debug = argc > 1; TEST4(1); TEST4(-1); printf ("%d test(s) failed\n", nfailed); return nfailed != 0; }
/** * constdef -> * ident = const */ ConstDefSP ConstDefB(void) { ConstDefSP t; NEWNODE(ConstDefS, t); if (TEST(ID)) { t->idp = IdentB(READCURR); } else t->idp = NULL; if (TEST(EQU)) { match(EQU); } else { --runlevel; syntaxError(MISSEQU, lineno, FALSE, prevTokenString); } if (TEST4(PLUS, MINUS, UNS, CH)) { switch (token) { case PLUS: match(PLUS); t->idp->type = Int_Const_Ident_t; if (TEST(UNS)) { t->idp->val = atoi(tokenString); match(UNS); } else { --runlevel; syntaxError(MISSUNS, lineno, FALSE, prevTokenString); } break; case MINUS: match(MINUS); t->idp->type = Int_Const_Ident_t; if (TEST(UNS)) { t->idp->val = - atoi(tokenString); match(UNS); } else { --runlevel; syntaxError(MISSUNS, lineno, FALSE, prevTokenString); } break; case UNS: t->idp->type = Int_Const_Ident_t; t->idp->val = atoi(tokenString); match(UNS); break; case CH: t->idp->type = Char_Const_Ident_t; t->idp->val = (int) tokenString[0]; match(CH); break; default: --runlevel; syntaxError(UNEXPECT, lineno, TRUE, tokenString); } } else t->idp = NULL; return t; }
int main() { TEST1(); TEST2(); TEST2(); TEST3(); TEST4(); TEST5(); TEST6(); TEST7(); TEST8(); TEST9(); TEST10(); TEST11(); TEST12(); TEST12(); TEST13(); TEST14(); TEST15(); TEST16(); TEST17(); TEST18(); TEST19(); TEST20(); TEST21(); TEST22(); TEST22(); TEST23(); TEST24(); TEST25(); TEST26(); TEST27(); TEST28(); TEST29(); TEST30(); TEST31(); TEST32(); TEST32(); TEST33(); TEST34(); TEST35(); TEST36(); TEST37(); TEST38(); TEST39(); return 0; }
int main() { int i; init_reg_val2(); #if (__mips_isa_rev < 6) printf("B \n"); for (i = 0; i < N; i++) TEST1(reg_val1[i], t0); printf("BAL \n"); for (i = 0; i < N; i++) TEST2(reg_val1[i], t0); printf("--- BEQ --- if RSval == RTval then " \ "out = RDval + 1 else out = RDval + 6\n"); TEST3("beq", 0, 0, 1, 2, 3, 4); TEST3("beq", 1, 1, 1, 3, 4, 5); TEST3("beq", 2, 0xffffffff, 0xffffffff, 4, 5, 6); TEST3("beq", 3, 0xffffffff, 0xfffffffe, 5, 6, 7); TEST3("beq", 4, 0xfffffffe, 0xffffffff, 6, 7, 8); TEST3("beq", 5, 0xffffffff, 0xffffffff, 7, 8, 9); TEST3("beq", 6, 0x5, 0x5, 8, 9, 10); TEST3("beq", 7, -3, -4, 9, 10, 11); TEST3("beq", 8, 125, 125, 10, 11, 12); TEST3("beq", 9, 0x80000000, 0x80000000, 11, 12, 15); TEST3("beq", 10, 0xffffffff, 0x80000000, 12, 13, 14); TEST3("beq", 11, 0x256, 0x256, 13, 14, 15); TEST3("beq", 12, 0x55, 0x55, 14, 15, 16); TEST3("beq", 13, 0xfff, 0xdd, 15, 16, 17); TEST3("beq", 14, -1, 0x5, 16, 17, 18); TEST3("beq", 15, -1, -1, 17, 18, 19); printf("--- BGEZ --- if RSval >= 0 then " \ "out = RDval + 1 else out = RDval + 9\n"); TEST4("bgez", 0, 0, 2, 3); TEST4("bgez", 1, 1, 3, 4); TEST4("bgez", 2, 0xffffffff, 4, 5); TEST4("bgez", 3, 0xffffffff, 5, 6); TEST4("bgez", 4, 0xfffffffe, 6, 7); TEST4("bgez", 5, 0xffffffff, 7, 8); TEST4("bgez", 6, 0x5, 8, 9); TEST4("bgez", 7, -3, 9, 10); TEST4("bgez", 8, 125, 10, 11); TEST4("bgez", 9, 0x80000000, 11, 12); TEST4("bgez", 10, 0xffffffff, 12, 13); TEST4("bgez", 11, 0x256, 13, 14); TEST4("bgez", 12, 0x55, 14, 15); TEST4("bgez", 13, 0xfff, 15, 16); TEST4("bgez", 14, -1, 16, 17); TEST4("bgez", 15, -1, 17, 18); printf("--- BGEZAL --- if RSval >= 0 then " \ "out = RDval + 1 else out = RDval + 6\n"); TEST5("bgezal", 0, 0, 2, 3); TEST5("bgezal", 1, 1, 3, 4); TEST5("bgezal", 2, 0xffffffff, 4, 5); TEST5("bgezal", 3, 0xffffffff, 5, 6); TEST5("bgezal", 4, 0xfffffffe, 6, 7); TEST5("bgezal", 5, 0xffffffff, 7, 8); TEST5("bgezal", 6, 0x5, 8, 9); TEST5("bgezal", 7, -3, 9, 10); TEST5("bgezal", 8, 125, 10, 11); TEST5("bgezal", 9, 0x80000000, 11, 12); TEST5("bgezal", 10, 0xffffffff, 12, 13); TEST5("bgezal", 11, 0x256, 13, 14); TEST5("bgezal", 12, 0x55, 14, 15); TEST5("bgezal", 13, 0xfff, 15, 16); TEST5("bgezal", 14, -1, 16, 17); TEST5("bgezal", 15, -1, 17, 18); printf("--- BGTZ --- if RSval > 0 then " \ "out = RDval + 1 else out = RDval + 9\n"); TEST4("bgtz", 0, 0, 2, 3); TEST4("bgtz", 1, 1, 3, 4); TEST4("bgtz", 2, 0xffffffff, 4, 5); TEST4("bgtz", 3, 0xffffffff, 5, 6); TEST4("bgtz", 4, 0xfffffffe, 6, 7); TEST4("bgtz", 5, 0xffffffff, 7, 8); TEST4("bgtz", 6, 0x5, 8, 9); TEST4("bgtz", 7, -3, 9, 10); TEST4("bgtz", 8, 125, 10, 11); TEST4("bgtz", 9, 0x80000000, 11, 12); TEST4("bgtz", 10, 0xffffffff, 12, 13); TEST4("bgtz", 11, 0x256, 13, 14); TEST4("bgtz", 12, 0x55, 14, 15); TEST4("bgtz", 13, 0xfff, 15, 16); TEST4("bgtz", 14, -1, 16, 17); TEST4("bgtz", 15, -1, 17, 18); printf("--- BLEZ --- if RSval <= 0 then " \ "out = RDval + 1 else out = RDval + 9\n"); TEST4("blez", 0, 0, 2, 3); TEST4("blez", 1, 1, 3, 4); TEST4("blez", 2, 0xffffffff, 4, 5); TEST4("blez", 3, 0xffffffff, 5, 6); TEST4("blez", 4, 0xfffffffe, 6, 7); TEST4("blez", 5, 0xffffffff, 7, 8); TEST4("blez", 6, 0x5, 8, 9); TEST4("blez", 7, -3, 9, 10); TEST4("blez", 8, 125, 10, 11); TEST4("blez", 9, 0x80000000, 11, 12); TEST4("blez", 10, 0xffffffff, 12, 13); TEST4("blez", 11, 0x256, 13, 14); TEST4("blez", 12, 0x55, 14, 15); TEST4("blez", 13, 0xfff, 15, 16); TEST4("blez", 14, -1, 16, 17); TEST4("blez", 15, -1, 17, 18); printf("--- BLTZ --- if RSval < 0 then " \ "out = RDval + 1 else out = RDval + 9\n"); TEST4("bltz", 0, 0, 2, 3); TEST4("bltz", 1, 1, 3, 4); TEST4("bltz", 2, 0xffffffff, 4, 5); TEST4("bltz", 3, 0xffffffff, 5, 6); TEST4("bltz", 4, 0xfffffffe, 6, 7); TEST4("bltz", 5, 0xffffffff, 7, 8); TEST4("bltz", 6, 0x5, 8, 9); TEST4("bltz", 7, -3, 9, 10); TEST4("bltz", 8, 125, 10, 11); TEST4("bltz", 9, 0x80000000, 11, 12); TEST4("bltz", 10, 0xffffffff, 12, 13); TEST4("bltz", 11, 0x256, 13, 14); TEST4("bltz", 12, 0x55, 14, 15); TEST4("bltz", 13, 0xfff, 15, 16); TEST4("bltz", 14, -1, 16, 17); TEST4("bltz", 15, -1, 17, 18); printf("--- BLTZAL --- if RSval < 0 then " \ "out = RDval + 1 else out = RDval + 6\n"); TEST5("bltzal", 0, 0, 2, 3); TEST5("bltzal", 1, 1, 3, 4); TEST5("bltzal", 2, 0xffffffff, 4, 5); TEST5("bltzal", 3, 0xffffffff, 5, 6); TEST5("bltzal", 4, 0xfffffffe, 6, 7); TEST5("bltzal", 5, 0xffffffff, 7, 8); TEST5("bltzal", 6, 0x5, 8, 9); TEST5("bltzal", 7, -3, 9, 10); TEST5("bltzal", 8, 125, 10, 11); TEST5("bltzal", 9, 0x80000000, 11, 12); TEST5("bltzal", 10, 0xffffffff, 12, 13); TEST5("bltzal", 11, 0x256, 13, 14); TEST5("bltzal", 12, 0x55, 14, 15); TEST5("bltzal", 13, 0xfff, 15, 16); TEST5("bltzal", 14, -1, 16, 17); TEST5("bltzal", 15, -1, 17, 18); printf("--- BNE --- if RSval != RTval then " \ "out = RDval + 1 else out = RDval + 6\n"); TEST3("bne", 0, 0, 1, 2, 3, 4); TEST3("bne", 1, 1, 1, 3, 4, 5); TEST3("bne", 2, 0xffffffff, 0xffffffff, 4, 5, 6); TEST3("bne", 3, 0xffffffff, 0xfffffffe, 5, 6, 7); TEST3("bne", 4, 0xfffffffe, 0xffffffff, 6, 7, 8); TEST3("bne", 5, 0xffffffff, 0xffffffff, 7, 8, 9); TEST3("bne", 6, 0x5, 0x5, 8, 9, 10); TEST3("bne", 7, -3, -4, 9, 10, 11); TEST3("bne", 8, 125, 125, 10, 11, 12); TEST3("bne", 9, 0x80000000, 0x80000000, 11, 12, 15); TEST3("bne", 10, 0xffffffff, 0x80000000, 12, 13, 14); TEST3("bne", 11, 0x256, 0x256, 13, 14, 15); TEST3("bne", 12, 0x55, 0x55, 14, 15, 16); TEST3("bne", 13, 0xfff, 0xdd, 15, 16, 17); TEST3("bne", 14, -1, 0x5, 16, 17, 18); TEST3("bne", 15, -1, -1, 17, 18, 19); printf("JAL, JR \n"); for (i = 0; i < N; i++) TEST2a(reg_val1[i], t0); printf("J, JALR \n"); for (i = 0; i < N; i++) TEST2b(reg_val1[i], t1); #endif return 0; }
int main() { int i; init_reg_val2(); for (i = 0; i < N; i++) { TEST1(reg_val1[i]); TEST2(reg_val1[i]); TEST1(reg_val2[i]); TEST2(reg_val2[i]); } printf("--- MOVF.S ---\n"); TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 1, 0); TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 1, 8); TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 1, 16); TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 1, 24); TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 1, 32) TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 1, 40) TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 1, 48) TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 1, 56) TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 0, 0); TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 0, 8); TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 0, 16); TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 0, 24); TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 0, 32); TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 0, 40); TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 0, 48); TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 0, 56); printf("--- MOVF.D ---\n"); TEST3d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 0); TEST3d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 8); TEST3d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 16); TEST3d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 24); TEST3d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 32); TEST3d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 40) TEST3d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 48) TEST3d("movf.d $f4, $f6, $fcc0", f4, f6, 1, 56) TEST3d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 0); TEST3d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 8); TEST3d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 16); TEST3d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 24); TEST3d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 32); TEST3d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 40); TEST3d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 48); TEST3d("movf.d $f4, $f6, $fcc0", f4, f6, 0, 56); printf("--- MOVN.S ---\n"); TEST4("movn.s $f0, $f2, $11", 0, 0, f0, f2, 11); TEST4("movn.s $f0, $f2, $11", 0, 1, f0, f2, 11); TEST4("movn.s $f0, $f2, $11", 8, 0xffff, f0, f2, 11); TEST4("movn.s $f0, $f2, $11", 16, -1, f0, f2, 11); TEST4("movn.s $f0, $f2, $11", 16, 5, f0, f2, 11); TEST4("movn.s $f0, $f2, $11", 24, 0, f0, f2, 11); TEST4("movn.s $f0, $f2, $11", 24, 0, f0, f2, 11); TEST4("movn.s $f0, $f2, $11", 32, 5, f0, f2, 11); TEST4("movn.s $f0, $f2, $11", 32, 125487, f0, f2, 11); TEST4("movn.s $f0, $f2, $11", 40, 68, f0, f2, 11); TEST4("movn.s $f0, $f2, $11", 40, -122544, f0, f2, 11); TEST4("movn.s $f0, $f2, $11", 48, 0, f0, f2, 11); TEST4("movn.s $f0, $f2, $11", 48, 0, f0, f2, 11); TEST4("movn.s $f0, $f2, $11", 56, 0xffffffff, f0, f2, 11); TEST4("movn.s $f0, $f2, $11", 56, 0x80000000, f0, f2, 11); TEST4("movn.s $f0, $f2, $11", 64, 0x7fffffff, f0, f2, 11); printf("--- MOVN.D ---\n"); TEST4d("movn.d $f0, $f2, $11", 0, 0, f0, f2, 11); TEST4d("movn.d $f0, $f2, $11", 0, 1, f0, f2, 11); TEST4d("movn.d $f0, $f2, $11", 8, 0xffff, f0, f2, 11); TEST4d("movn.d $f0, $f2, $11", 8, -1, f0, f2, 11); TEST4d("movn.d $f0, $f2, $11", 16, 5, f0, f2, 11); TEST4d("movn.d $f0, $f2, $11", 24, 0, f0, f2, 11); TEST4d("movn.d $f0, $f2, $11", 24, 0, f0, f2, 11); TEST4d("movn.d $f0, $f2, $11", 32, 5, f0, f2, 11); TEST4d("movn.d $f0, $f2, $11", 32, 125487, f0, f2, 11); TEST4d("movn.d $f0, $f2, $11", 40, 68, f0, f2, 11); TEST4d("movn.d $f0, $f2, $11", 40, -122544, f0, f2, 11); TEST4d("movn.d $f0, $f2, $11", 48, 0, f0, f2, 11); TEST4d("movn.d $f0, $f2, $11", 48, 0, f0, f2, 11); TEST4d("movn.d $f0, $f2, $11", 56, 0xffffffff, f0, f2, 11); TEST4d("movn.d $f0, $f2, $11", 56, 0x80000000, f0, f2, 11); TEST4d("movn.d $f0, $f2, $11", 64, 0x7fffffff, f0, f2, 11); printf("--- MOVT.S ---\n"); TEST3("movt.s $f4, $f6, $fcc0", f4, f6, 1, 0); TEST3("movt.s $f4, $f6, $fcc0", f4, f6, 1, 0); TEST3("movt.s $f4, $f6, $fcc0", f4, f6, 1, 8); TEST3("movt.s $f4, $f6, $fcc0", f4, f6, 1, 16); TEST3("movt.s $f4, $f6, $fcc0", f4, f6, 1, 24); TEST3("movt.s $f4, $f6, $fcc0", f4, f6, 1, 32); TEST3("movt.s $f4, $f6, $fcc0", f4, f6, 1, 40) TEST3("movt.s $f4, $f6, $fcc0", f4, f6, 1, 48) TEST3("movt.s $f4, $f6, $fcc0", f4, f6, 1, 56) TEST3("movt.s $f4, $f6, $fcc0", f4, f6, 0, 0); TEST3("movt.s $f4, $f6, $fcc0", f4, f6, 0, 8); TEST3("movt.s $f4, $f6, $fcc0", f4, f6, 0, 16); TEST3("movt.s $f4, $f6, $fcc0", f4, f6, 0, 24); TEST3("movt.s $f4, $f6, $fcc0", f4, f6, 0, 32); TEST3("movt.s $f4, $f6, $fcc0", f4, f6, 0, 40); TEST3("movt.s $f4, $f6, $fcc0", f4, f6, 0, 48); TEST3("movt.s $f4, $f6, $fcc0", f4, f6, 0, 56); printf("--- MOVT.D ---\n"); TEST3d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 0); TEST3d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 0); TEST3d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 8); TEST3d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 16); TEST3d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 24); TEST3d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 32); TEST3d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 40) TEST3d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 48) TEST3d("movt.d $f4, $f6, $fcc0", f4, f6, 1, 56) TEST3d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 0); TEST3d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 8); TEST3d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 16); TEST3d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 24); TEST3d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 32); TEST3d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 40); TEST3d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 48); TEST3d("movt.d $f4, $f6, $fcc0", f4, f6, 0, 56); printf("--- MOVZ.S ---\n"); TEST4("movz.s $f0, $f2, $11", 0, 0, f0, f2, 11); TEST4("movz.s $f0, $f2, $11", 8, 1, f0, f2, 11); TEST4("movz.s $f0, $f2, $11", 8, 0xffff, f0, f2, 11); TEST4("movz.s $f0, $f2, $11", 16, -1, f0, f2, 11); TEST4("movz.s $f0, $f2, $11", 16, 5, f0, f2, 11); TEST4("movz.s $f0, $f2, $11", 24, 0, f0, f2, 11); TEST4("movz.s $f0, $f2, $11", 24, 0, f0, f2, 11); TEST4("movz.s $f0, $f2, $11", 32, 5, f0, f2, 11); TEST4("movz.s $f0, $f2, $11", 32, 125487, f0, f2, 11); TEST4("movz.s $f0, $f2, $11", 40, 68, f0, f2, 11); TEST4("movz.s $f0, $f2, $11", 40, -122544, f0, f2, 11); TEST4("movz.s $f0, $f2, $11", 48, 0, f0, f2, 11); TEST4("movz.s $f0, $f2, $11", 48, 0, f0, f2, 11); TEST4("movz.s $f0, $f2, $11", 56, 0xffffffff, f0, f2, 11); TEST4("movz.s $f0, $f2, $11", 56, 0x80000000, f0, f2, 11); TEST4("movz.s $f0, $f2, $11", 64, 0x7fffffff, f0, f2, 11); printf("--- MOVZ.D ---\n"); TEST4d("movz.d $f0, $f2, $11", 0, 0, f0, f2, 11); TEST4d("movz.d $f0, $f2, $11", 0, 1, f0, f2, 11); TEST4d("movz.d $f0, $f2, $11", 8, 0xffff, f0, f2, 11); TEST4d("movz.d $f0, $f2, $11", 16, -1, f0, f2, 11); TEST4d("movz.d $f0, $f2, $11", 16, 5, f0, f2, 11); TEST4d("movz.d $f0, $f2, $11", 24, 0, f0, f2, 11); TEST4d("movz.d $f0, $f2, $11", 24, 0, f0, f2, 11); TEST4d("movz.d $f0, $f2, $11", 32, 5, f0, f2, 11); TEST4d("movz.d $f0, $f2, $11", 32, 125487, f0, f2, 11); TEST4d("movz.d $f0, $f2, $11", 40, 68, f0, f2, 11); TEST4d("movz.d $f0, $f2, $11", 40, -122544, f0, f2, 11); TEST4d("movz.d $f0, $f2, $11", 48, 0, f0, f2, 11); TEST4d("movz.d $f0, $f2, $11", 48, 0, f0, f2, 11); TEST4d("movz.d $f0, $f2, $11", 56, 0xffffffff, f0, f2, 11); TEST4d("movz.d $f0, $f2, $11", 56, 0x80000000, f0, f2, 11); TEST4d("movz.d $f0, $f2, $11", 64, 0x7fffffff, f0, f2, 11); printf("--- MOVF --- if FPConditionalCode(cc) == 0 then " "out = RSval else out = RDval\n"); for (i = 0; i < 24; i++) { TEST5("movf", 0xaaaaaaaa, 0x80000000, t0, t1); TEST5("movf", 0xccccffff, 0xffffffff, t1, t2); TEST5("movf", 0xffffaaaa, 0xaaaaffff, t3, t1); TEST5("movf", 0x0, 0xffffffff, t3, t0); } printf("--- MOVT --- if FPConditionalCode(cc) == 1 then " "out = RSval else out = RDval\n"); for (i = 0; i < 24; i++) { TEST5("movt", 0x0, 0xffffffff, t0, t1); TEST5("movt", 0x11111111, 0xeeeeffff, t1, t2); TEST5("movt", 0x5555ffff, 0xffffffff, t3, t1); TEST5("movt", 0xeeeeeeee, 0xffffeeee, t3, t0); } return 0; }
int main() { arithmetic_op op; int i; init_reg_val2(); for (op = ADD; op <= SUBU; op++) { for (i = 0; i < N; i++) { switch(op) { case ADD: /* If either GPR rt or GPR rs does not contain sign-extended 32-bit values (bits 63..31 equal), then the result of the operation is UNPREDICTABLE. */ TEST1("add $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], t0, t1, t2); break; case ADDI: /* If GPR rs does not contain a sign-extended 32-bit value (bits 63..31 equal), then the result of the operation is UNPREDICTABLE. */ TEST2("addi $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1); TEST2("addi $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3); TEST2("addi $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1); TEST2("addi $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1); break; case ADDIU: /* If GPR rs does not contain a sign-extended 32-bit value (bits 63..31 equal), then the result of the operation is UNPREDICTABLE. */ TEST2("addiu $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1); TEST2("addiu $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3); TEST2("addiu $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1); TEST2("addiu $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1); break; case ADDU: /* If either GPR rt or GPR rs does not contain sign-extended 32-bit values (bits 63..31 equal), then the result of the operation is UNPREDICTABLE. */ TEST1("addu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], t0, t1, t2); break; case CLO: /* If GPR rs does not contain a sign-extended 32-bit value (bits 63..31 equal), then the results of the operation are UNPREDICTABLE. */ TEST3("clo $t0, $t1", reg_val1[i], t0, t1); break; case CLZ: /* If GPR rs does not contain a sign-extended 32-bit value (bits 63..31 equal), then the results of the operation are UNPREDICTABLE. */ TEST3("clz $t0, $t1", reg_val1[i], t0, t1); break; case DADD: /* If the addition results in 64-bit 2âs complement arithmetic overflow, then the destination register is not modified and an IntegerOverflow exception occurs. */ TEST1("dadd $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], t0, t1, t2); break; case DADDI: /* If the addition results in 64-bit 2âs complement arithmetic overflow, then the destination register is not modified and an Integer Overflow exception occurs. */ TEST2("daddi $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1); TEST2("daddi $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3); TEST2("daddi $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1); TEST2("daddi $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1); TEST2("daddi $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1); TEST2("daddi $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3); TEST2("daddi $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1); TEST2("daddi $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1); break; case DADDIU: /* No Integer Overflow exception occurs under any circumstances. */ TEST2("daddiu $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1); TEST2("daddiu $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3); TEST2("daddiu $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1); TEST2("daddiu $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1); TEST2("daddiu $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1); TEST2("daddiu $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3); TEST2("daddiu $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1); TEST2("daddiu $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1); break; case DADDU: /* No Integer Overflow exception occurs under any circumstances. */ TEST1("daddu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], t0, t1, t2); TEST1("daddu $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], s0, s1, s2); break; case DCLO: /* No arithmetic exception occurs under any circumstances. */ TEST3("dclo $t0, $t1", reg_val1[i], t0, t1); TEST3("dclo $v0, $v1", reg_val2[i], v0, v1); break; case DCLZ: /* No arithmetic exception occurs under any circumstances. */ TEST3("dclz $t0, $t1", reg_val1[i], t0, t1); TEST3("dclz $v0, $v1", reg_val2[i], v0, v1); break; case DDIV: /* If the divisor in GPR rt is zero, the arithmetic result value is UNPREDICTABLE. */ if (reg_val1[N-i-1] != 0) TEST4("ddiv $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); if (reg_val2[N-i-1] != 0) TEST4("ddiv $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1); break; case DDIVU: /* If the divisor in GPR rt is zero, the arithmetic result value is UNPREDICTABLE. */ if (reg_val1[N-i-1] != 0) TEST4("ddivu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); if (reg_val2[N-i-1] != 0) TEST4("ddivu $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1); break; case DIV: /* If either GPR rt or GPR rs does not contain sign-extended 32-bit values (bits 63..31 equal), then the result of the operation is UNPREDICTABLE. If the divisor in GPR rt is zero, the arithmetic result value is UNPREDICTABLE. */ if (reg_val1[N-i-1] != 0) TEST4("div $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); break; case DIVU: /* If either GPR rt or GPR rs does not contain sign-extended 32-bit values (bits 63..31 equal), then the result of the operation is UNPREDICTABLE. If the divisor in GPR rt is zero, the arithmetic result value is UNPREDICTABLE. */ if (reg_val1[N-i-1] != 0) TEST4("divu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); break; case DMULT: /* No arithmetic exception occurs under any circumstances. */ TEST4("dmult $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); TEST4("dmult $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1); break; case DMULTU: /* No arithmetic exception occurs under any circumstances. */ TEST4("dmultu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); TEST4("dmultu $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1); break; case DSUB: /* If the subtraction results in 64-bit 2âs complement arithmetic overflow, then the destination register is not modified and an Integer Overflow exception occurs. */ TEST1("dsub $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], t0, t1, t2); break; case DSUBU: /* No Integer Overflow exception occurs under any circumstances. */ TEST1("dsubu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], t0, t1, t2); TEST1("dsubu $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], s0, s1, s2); break; case MADD: /* If GPRs rs or rt do not contain sign-extended 32-bit values (bits 63..31 equal), then the results of the operation are UNPREDICTABLE. */ TEST5("madd $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); break; case MADDU: /* If GPRs rs or rt do not contain sign-extended 32-bit values (bits 63..31 equal), then the results of the operation are UNPREDICTABLE. */ TEST5("maddu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); break; case MSUB: /* If GPR rs or rt do not contain a sign-extended 32-bit value (bits 63..31 equal), then the results of the operation are UNPREDICTABLE. */ TEST5("msub $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); break; case MSUBU: /* If GPRs rs or rt do not contain sign-extended 32-bit values (bits 63..31 equal), then the results of the operation are UNPREDICTABLE. This instruction does not provide the capability of writing directly to a target GPR. */ TEST5("msubu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); break; case MUL: /* On 64-bit processors, if either GPR rt or GPR rs does not contain sign-extended 32-bit values (bits 63..31 equal), then the result of the operation is UNPREDICTABLE. */ TEST1("mul $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], t0, t1, t2); break; case MULT: /* On 64-bit processors, if either GPR rt or GPR rs does not contain sign-extended 32-bit values (bits 63..31 equal), then the result of the operation is UNPREDICTABLE. */ TEST4("mult $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); break; case MULTU: /* On 64-bit processors, if either GPR rt or GPR rs does not contain sign-extended 32-bit values (bits 63..31 equal), then the result of the operation is UNPREDICTABLE. */ TEST4("multu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); break; case MOVN: /* The arithmetic comparison does not cause an Integer Overflow exception. */ TEST1("movn $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], t0, t1, t2); TEST1("movn $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], s0, s1, s2); break; case MOVZ: /* The arithmetic comparison does not cause an Integer Overflow exception. */ TEST1("movz $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], t0, t1, t2); TEST1("movz $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], s0, s1, s2); break; case SEB: #if (__mips==64) && (__mips_isa_rev>=2) /* If GPR rt does not contain a sign-extended 32-bit value (bits 63..31 equal), then the result of the operation is UNPREDICTABLE. */ TEST3("seb $t0, $t1", reg_val1[i], t0, t1); #endif break; case SEH: #if (__mips==64) && (__mips_isa_rev>=2) /* If GPR rt does not contain a sign-extended 32-bit value (bits 63..31 equal), then the result of the operation is UNPREDICTABLE. */ TEST3("seh $t0, $t1", reg_val1[i], t0, t1); #endif break; case SLT: /* The arithmetic comparison does not cause an Integer Overflow exception. */ TEST1("slt $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], t0, t1, t2); break; case SLTI: /* The arithmetic comparison does not cause an Integer Overflow exception. */ TEST2("slti $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1); TEST2("slti $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3); TEST2("slti $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1); TEST2("slti $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1); TEST2("slti $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1); TEST2("slti $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3); TEST2("slti $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1); TEST2("slti $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1); break; case SLTIU: /* The arithmetic comparison does not cause an Integer Overflow exception. */ TEST2("sltiu $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1); TEST2("sltiu $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3); TEST2("sltiu $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1); TEST2("sltiu $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1); TEST2("sltiu $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1); TEST2("sltiu $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3); TEST2("sltiu $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1); TEST2("sltiu $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1); break; case SLTU: /* The arithmetic comparison does not cause an Integer Overflow exception. */ TEST1("sltu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], t0, t1, t2); TEST1("sltu $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], s0, s1, s2); break; case SUB: /* On 64-bit processors, if either GPR rt or GPR rs does not contain sign-extended 32-bit values (bits 63..31 equal), then the result of the operation is UNPREDICTABLE. */ if (i < 8 || (i > 15 && i < 22)) TEST1("sub $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], t0, t1, t2); break; case SUBU: /* On 64-bit processors, if either GPR rt or GPR rs does not contain sign-extended 32-bit values (bits 63..31 equal), then the result of the operation is UNPREDICTABLE. */ TEST1("subu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], t0, t1, t2); break; default: printf("Error!\n"); break; } } } return 0; }