예제 #1
0
/**
  * @brief  Configures the TIM2 Trigger as External Clock.
  * @param  TIM2_TIxExternalCLKSource : Specifies Trigger source.
  *   This parameter can be one of the @ref TIM2_TIxExternalCLK1Source_TypeDef enumeration.
  * @param  TIM2_ICPolarity : Specifies the TIx Polarity.
  *   This parameter can be @ref TIM2_ICPolarity_TypeDef enumeration.
  * @param  ICFilter : Specifies the filter value.
  *   This parameter must be a value between 0x00 and 0x0F
  * @retval None
  */
void TIM2_TIxExternalClockConfig(TIM2_TIxExternalCLK1Source_TypeDef TIM2_TIxExternalCLKSource,
                                 TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
                                 uint8_t ICFilter)
{
  /* Check the parameters */
  assert_param(IS_TIM2_TIXCLK_SOURCE(TIM2_TIxExternalCLKSource));
  assert_param(IS_TIM2_IC_POLARITY(TIM2_ICPolarity));
  assert_param(IS_TIM2_IC_FILTER(ICFilter));

  /* Configure the TIM2 Input Clock Source */
  if (TIM2_TIxExternalCLKSource == TIM2_TIxExternalCLK1Source_TI2)
  {
    TI2_Config(TIM2_ICPolarity, TIM2_ICSelection_DirectTI, ICFilter);
  }
  else
  {
    TI1_Config(TIM2_ICPolarity, TIM2_ICSelection_DirectTI, ICFilter);
  }

  /* Select the Trigger source */
  TIM2_SelectInputTrigger((TIM2_TRGSelection_TypeDef)TIM2_TIxExternalCLKSource);

  /* Select the External clock mode1 */
  TIM2->SMCR |= (uint8_t)(TIM2_SlaveMode_External1);
}
예제 #2
0
/**
  * @brief  Configure TIM1,2,3 peripherals 
  * @param  None
  * @retval None
  */
static void TIM_Config(void)
{
  /* TIM1 configuration:
   - TIM1CLK is set to 2 MHz, the TIM2 Prescaler is equal to 15 so the TIM1 counter
   clock used is 2 MHz / (15 + 1) = 125 000 Hz
   - TIM1 Channel 1 output frequency = TIM1CLK / (TIM1_PERIOD + 1) * (TIM1_PRESCALER + 1)
                                    = 2 000 000 / 256 * 16 = 488.28 Hz */
  /* Time Base configuration */
  TIM1_TimeBaseInit(TIM1_PRESCALER, TIM1_CounterMode_Up, TIM1_PERIOD, TIM1_REPETITION_COUNTER);

  /* TIM1 Channel 1 Configuration in PWM2 mode */
  TIM1_OC1Init(TIM1_OCMode_PWM2, TIM1_OutputState_Enable, TIM1_OutputNState_Disable, TIM1_CCR1_VAL,
               TIM1_OCPolarity_Low, TIM1_OCNPolarity_Low, TIM1_OCIdleState_Set, TIM1_OCNIdleState_Set);

  /* Master Mode selection: Update event */
  TIM1_SelectOutputTrigger(TIM1_TRGOSource_Update);

  /* TIM2 configuration:
   - TIM2 is connected to TIM1 Update so TIM2CLK is equal to 
     TIM1 output clock / (TIM1_REPETITION_COUNTER + 1) = 488.28 / 5 = 97.65 Hz
    - TIM2 Prescaler is equal to 1 so the TIM2 counter clock used is 97.65 / 1 = 97.65 Hz
    - TIM2 Channel 1 output frequency = TIM2CLK / (TIM2_PERIOD + 1) * TIM2_Prescaler
                                     = 97.65 / 3 * 1 = 32.55 Hz */
  /* Time Base configuration */
  TIM2_TimeBaseInit(TIM2_Prescaler_1, TIM2_CounterMode_Up, TIM2_PERIOD);

  TIM2_OC1Init(TIM2_OCMode_PWM2, TIM2_OutputState_Enable, TIM2_CCR1_VAL,
               TIM2_OCPolarity_Low, TIM2_OCIdleState_Reset);

  /* TIM2 Slave Mode selection: Gated mode */
  TIM2_SelectSlaveMode(TIM2_SlaveMode_Gated);
  TIM2_SelectInputTrigger(TIM2_TRGSelection_TIM1);

  /* TIM3 configuration:
   - TIM3 is connected to TIM1 Update so TIM3CLK is equal to 
     TIM1 output clock / (TIM1_REPETITION_COUNTER + 1) = 488.28 / 5 = 97.65 Hz
    - TIM3 Prescaler is equal to 1 so the TIM3 counter clock used is 97.65 / 1 = 97.65 Hz
    - TIM3 Channel 1 output frequency = TIM3CLK / (TIM3_PERIOD + 1) * TIM3Prescaler
                                     = 97.65 / 4 * 1 = 24.41 Hz */
  /* Time Base configuration */
  TIM3_TimeBaseInit(TIM3_Prescaler_1, TIM3_CounterMode_Up, TIM3_PERIOD);

  TIM3_OC1Init(TIM3_OCMode_PWM2, TIM3_OutputState_Enable, TIM3_CCR1_VAL,
               TIM3_OCPolarity_Low, TIM3_OCIdleState_Reset);

  /* TIM3 Slave Mode selection: Gated mode */
  TIM3_SelectSlaveMode(TIM3_SlaveMode_Gated);
  TIM3_SelectInputTrigger(TIM3_TRGSelection_TIM1);

  /* Main Output Enable */
  TIM1_CtrlPWMOutputs(ENABLE);
  TIM2_CtrlPWMOutputs(ENABLE);
  TIM3_CtrlPWMOutputs(ENABLE);

  /* TIM2 counter enable */
  TIM2_Cmd(ENABLE);
  /* TIM3 counter enable */
  TIM3_Cmd(ENABLE);
  /* TIM1 counter enable */
  TIM1_Cmd(ENABLE);
}