void TM_NRF24L01_GetData(uint8_t* data) {
//Pull down chip select
NRF24L01_CSN_LOW;
//Send read payload command
TM_SPI_Send(NRF24L01_SPI, NRF24L01_R_RX_PAYLOAD_MASK);
//Read payload
TM_SPI_SendMulti(NRF24L01_SPI, data, data, TM_NRF24L01_Struct.PayloadSize);
//Pull up chip select
NRF24L01_CSN_HIGH;
//Reset status register, clear RX_DR interrupt flag
TM_NRF24L01_WriteRegister(NRF24L01_REG_STATUS, (1 << NRF24L01_RX_DR));
}
void TM_NRF24L01_WriteBit(uint8_t reg, uint8_t bit, uint8_t value) {
uint8_t tmp;
/* Read register */
tmp = TM_NRF24L01_ReadRegister(reg);
/* Make operation */
if (value) {
tmp |= 1 << bit;
} else {
tmp &= ~(1 << bit);
}
/* Write back */
TM_NRF24L01_WriteRegister(reg, tmp);
}
void TM_NRF24L01_SetRF(TM_NRF24L01_DataRate_t DataRate, TM_NRF24L01_OutputPower_t OutPwr) {
uint8_t tmp = 0;
TM_NRF24L01_Struct.DataRate = DataRate;
TM_NRF24L01_Struct.OutPwr = OutPwr;
if (DataRate == TM_NRF24L01_DataRate_2M) {
tmp |= 1 << NRF24L01_RF_DR_HIGH;
} else if (DataRate == TM_NRF24L01_DataRate_250k) {
tmp |= 1 << NRF24L01_RF_DR_LOW;
}
/* If 1Mbps, all bits set to 0 */
if (OutPwr == TM_NRF24L01_OutputPower_0dBm) {
tmp |= 3 << NRF24L01_RF_PWR;
} else if (OutPwr == TM_NRF24L01_OutputPower_M6dBm) {
tmp |= 2 << NRF24L01_RF_PWR;
} else if (OutPwr == TM_NRF24L01_OutputPower_M12dBm) {
tmp |= 1 << NRF24L01_RF_PWR;
}
TM_NRF24L01_WriteRegister(NRF24L01_REG_RF_SETUP, tmp);
}
void TM_NRF24L01_SoftwareReset(void) {
uint8_t data[5];
TM_NRF24L01_WriteRegister(NRF24L01_REG_CONFIG, NRF24L01_REG_DEFAULT_VAL_CONFIG);
TM_NRF24L01_WriteRegister(NRF24L01_REG_EN_AA, NRF24L01_REG_DEFAULT_VAL_EN_AA);
TM_NRF24L01_WriteRegister(NRF24L01_REG_EN_RXADDR, NRF24L01_REG_DEFAULT_VAL_EN_RXADDR);
TM_NRF24L01_WriteRegister(NRF24L01_REG_SETUP_AW, NRF24L01_REG_DEFAULT_VAL_SETUP_AW);
TM_NRF24L01_WriteRegister(NRF24L01_REG_SETUP_RETR, NRF24L01_REG_DEFAULT_VAL_SETUP_RETR);
TM_NRF24L01_WriteRegister(NRF24L01_REG_RF_CH, NRF24L01_REG_DEFAULT_VAL_RF_CH);
TM_NRF24L01_WriteRegister(NRF24L01_REG_RF_SETUP, NRF24L01_REG_DEFAULT_VAL_RF_SETUP);
TM_NRF24L01_WriteRegister(NRF24L01_REG_STATUS, NRF24L01_REG_DEFAULT_VAL_STATUS);
TM_NRF24L01_WriteRegister(NRF24L01_REG_OBSERVE_TX, NRF24L01_REG_DEFAULT_VAL_OBSERVE_TX);
TM_NRF24L01_WriteRegister(NRF24L01_REG_RPD, NRF24L01_REG_DEFAULT_VAL_RPD);
//P0
data[0] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_0;
data[1] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_1;
data[2] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_2;
data[3] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_3;
data[4] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_4;
TM_NRF24L01_WriteRegisterMulti(NRF24L01_REG_RX_ADDR_P0, data, 5);
//P1
data[0] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_0;
data[1] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_1;
data[2] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_2;
data[3] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_3;
data[4] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_4;
TM_NRF24L01_WriteRegisterMulti(NRF24L01_REG_RX_ADDR_P1, data, 5);
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_ADDR_P2, NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P2);
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_ADDR_P3, NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P3);
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_ADDR_P4, NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P4);
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_ADDR_P5, NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P5);
//TX
data[0] = NRF24L01_REG_DEFAULT_VAL_TX_ADDR_0;
data[1] = NRF24L01_REG_DEFAULT_VAL_TX_ADDR_1;
data[2] = NRF24L01_REG_DEFAULT_VAL_TX_ADDR_2;
data[3] = NRF24L01_REG_DEFAULT_VAL_TX_ADDR_3;
data[4] = NRF24L01_REG_DEFAULT_VAL_TX_ADDR_4;
TM_NRF24L01_WriteRegisterMulti(NRF24L01_REG_TX_ADDR, data, 5);
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_PW_P0, NRF24L01_REG_DEFAULT_VAL_RX_PW_P0);
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_PW_P1, NRF24L01_REG_DEFAULT_VAL_RX_PW_P1);
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_PW_P2, NRF24L01_REG_DEFAULT_VAL_RX_PW_P2);
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_PW_P3, NRF24L01_REG_DEFAULT_VAL_RX_PW_P3);
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_PW_P4, NRF24L01_REG_DEFAULT_VAL_RX_PW_P4);
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_PW_P5, NRF24L01_REG_DEFAULT_VAL_RX_PW_P5);
TM_NRF24L01_WriteRegister(NRF24L01_REG_FIFO_STATUS, NRF24L01_REG_DEFAULT_VAL_FIFO_STATUS);
TM_NRF24L01_WriteRegister(NRF24L01_REG_DYNPD, NRF24L01_REG_DEFAULT_VAL_DYNPD);
TM_NRF24L01_WriteRegister(NRF24L01_REG_FEATURE, NRF24L01_REG_DEFAULT_VAL_FEATURE);
}
void TM_NRF24L01_PowerUpTx(void) {
NRF24L01_CLEAR_INTERRUPTS;
TM_NRF24L01_WriteRegister(NRF24L01_REG_CONFIG, NRF24L01_CONFIG | (0 << NRF24L01_PRIM_RX) | (1 << NRF24L01_PWR_UP));
}
uint8_t TM_NRF24L01_Init(uint8_t channel, uint8_t payload_size) {
/* Initialize CE and CSN pins */
TM_NRF24L01_InitPins();
/* Initialize SPI */
TM_SPI_Init(NRF24L01_SPI, NRF24L01_SPI_PINS);
/* Max payload is 32bytes */
if (payload_size > 32) {
payload_size = 32;
}
/* Fill structure */
TM_NRF24L01_Struct.Channel = !channel; /* Set channel to some different value for TM_NRF24L01_SetChannel() function */
TM_NRF24L01_Struct.PayloadSize = payload_size;
TM_NRF24L01_Struct.OutPwr = TM_NRF24L01_OutputPower_0dBm;
TM_NRF24L01_Struct.DataRate = TM_NRF24L01_DataRate_2M;
/* Reset nRF24L01+ to power on registers values */
TM_NRF24L01_SoftwareReset();
/* Channel select */
TM_NRF24L01_SetChannel(channel);
/* Set pipeline to max possible 32 bytes */
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_PW_P0, TM_NRF24L01_Struct.PayloadSize); // Auto-ACK pipe
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_PW_P1, TM_NRF24L01_Struct.PayloadSize); // Data payload pipe
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_PW_P2, TM_NRF24L01_Struct.PayloadSize);
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_PW_P3, TM_NRF24L01_Struct.PayloadSize);
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_PW_P4, TM_NRF24L01_Struct.PayloadSize);
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_PW_P5, TM_NRF24L01_Struct.PayloadSize);
/* Set RF settings (2mbps, output power) */
TM_NRF24L01_SetRF(TM_NRF24L01_Struct.DataRate, TM_NRF24L01_Struct.OutPwr);
/* Config register */
TM_NRF24L01_WriteRegister(NRF24L01_REG_CONFIG, NRF24L01_CONFIG);
/* Enable auto-acknowledgment for all pipes */
TM_NRF24L01_WriteRegister(NRF24L01_REG_EN_AA, 0x3F);
/* Enable RX addresses */
TM_NRF24L01_WriteRegister(NRF24L01_REG_EN_RXADDR, 0x3F);
/* Auto retransmit delay: 1000 (4x250) us and Up to 15 retransmit trials */
TM_NRF24L01_WriteRegister(NRF24L01_REG_SETUP_RETR, 0x4F);
/* Dynamic length configurations: No dynamic length */
TM_NRF24L01_WriteRegister(NRF24L01_REG_DYNPD, (0 << NRF24L01_DPL_P0) | (0 << NRF24L01_DPL_P1) | (0 << NRF24L01_DPL_P2) | (0 << NRF24L01_DPL_P3) | (0 << NRF24L01_DPL_P4) | (0 << NRF24L01_DPL_P5));
/* Clear FIFOs */
NRF24L01_FLUSH_TX;
NRF24L01_FLUSH_RX;
/* Clear interrupts */
NRF24L01_CLEAR_INTERRUPTS;
/* Go to RX mode */
TM_NRF24L01_PowerUpRx();
/* Return OK */
return 1;
}
uint8_t TM_NRF24L01_Init(uint8_t channel, uint8_t payload_size) {
//Initialize CE and CSN pins
TM_NRF24L01_InitPins();
//Initialize SPI
TM_SPI_Init(NRF24L01_SPI, NRF24L01_SPI_PINS);
//Max payload is 32bytes
if (payload_size > 32) {
payload_size = 32;
}
TM_NRF24L01_Struct.Channel = channel;
TM_NRF24L01_Struct.PayloadSize = payload_size;
TM_NRF24L01_Struct.OutPwr = TM_NRF24L01_OutputPower_0dBm;
TM_NRF24L01_Struct.DataRate = TM_NRF24L01_DataRate_2M;
//Reset nRF24L01+ to power on registers values
TM_NRF24L01_SoftwareReset();
//Channel select
TM_NRF24L01_SetChannel(TM_NRF24L01_Struct.Channel);
//Set pipeline to max possible 32 bytes
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_PW_P0, TM_NRF24L01_Struct.PayloadSize); // Auto-ACK pipe
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_PW_P1, TM_NRF24L01_Struct.PayloadSize); // Data payload pipe
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_PW_P2, 0x00);
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_PW_P3, 0x00);
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_PW_P4, 0x00);
TM_NRF24L01_WriteRegister(NRF24L01_REG_RX_PW_P5, 0x00);
//Set RF settings (2mbps, output power)
TM_NRF24L01_SetRF(TM_NRF24L01_Struct.DataRate, TM_NRF24L01_Struct.OutPwr);
//Config register
TM_NRF24L01_WriteRegister(NRF24L01_REG_CONFIG, NRF24L01_CONFIG);
//Enable auto-acknowledgment for all pipes
TM_NRF24L01_WriteRegister(NRF24L01_REG_EN_AA, 0xFF);
// Enable RX addresses
TM_NRF24L01_WriteRegister(NRF24L01_REG_EN_RXADDR, 0xFF);
//Auto retransmit delay: 1000 (4x250) us and Up to 15 retransmit trials
TM_NRF24L01_WriteRegister(NRF24L01_REG_SETUP_RETR, 0x4F);
// Dynamic length configurations: No dynamic length
TM_NRF24L01_WriteRegister(NRF24L01_REG_DYNPD, (0 << NRF24L01_DPL_P0) | (0 << NRF24L01_DPL_P1) | (0 << NRF24L01_DPL_P2) | (0 << NRF24L01_DPL_P3) | (0 << NRF24L01_DPL_P4) | (0 << NRF24L01_DPL_P5));
//Clear FIFOs
NRF24L01_FLUSH_TX;
NRF24L01_FLUSH_RX;
//Go to RX mode
TM_NRF24L01_PowerUpRx();
return 1;
}
void TM_NRF24L01_SetChannel(uint8_t channel) {
if (channel <= 125) {
TM_NRF24L01_Struct.Channel = channel;
TM_NRF24L01_WriteRegister(NRF24L01_REG_RF_CH, channel);
}
}
void TM_NRF24L01_Clear_Interrupts(void) {
TM_NRF24L01_WriteRegister(0x07, 0x70);
}
void TM_NRF24L01_PowerUpTx(void) {
TM_NRF24L01_Clear_Interrupts();
TM_NRF24L01_WriteRegister(NRF24L01_REG_CONFIG, NRF24L01_CONFIG | (0 << NRF24L01_PRIM_RX) | (1 << NRF24L01_PWR_UP));
}
