/*---------------------------------------------------------------------------*/ void rtimer_arch_schedule(rtimer_clock_t t) { PRINTF("rtimer_arch_schedule time 0x%4x\n",(unsigned int)t); #if RTIMER_CONF_USE_LPTMR RT_DISABLE(); /* Disable LPTMR to write to CMR register */ LPTMR0_CMR = LPTMR_CMR_COMPARE(t); /* enable LPTMR interrupts and clear interrupt flag */ LPTMR0_CSR |= (LPTMR_CSR_TCF_MASK | LPTMR_CSR_TIE_MASK); RT_ENABLE(); /* Re-enable LPTMR */ #else RT_MODE_CAPTURE(); TPM0_C0V = TPM_CnV_VAL(t); RT_MODE_COMPARE(); /* enable tmp0 channel 0 interrupts */ TPM0_C0SC |= TPM_CnSC_CHIE_MASK; TPM0_STATUS = (TPM_STATUS_CH0F_MASK | TPM_STATUS_CH1F_MASK | TPM_STATUS_CH2F_MASK | TPM_STATUS_CH3F_MASK | TPM_STATUS_CH4F_MASK | TPM_STATUS_CH5F_MASK | TPM_STATUS_TOF_MASK); #endif /* RTIMER_CONF_USE_LPTMR */ }
/*---------------------------------------------------------------------------*/ void rtimer_arch_init(void) { #if RTIMER_CONF_USE_LPTMR /* SIM_SCGC5: LPTMR=1 */ SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK; LPTMR0_CSR = (LPTMR_CSR_TCF_MASK | LPTMR_CSR_TPS(0x00) | LPTMR_CSR_TFC_MASK); /* Clear control register */ LPTMR0_CMR = LPTMR_CMR_COMPARE(LPTMR_CMR_COMPARE_MASK); /* Set up compare register */ LPTMR0_PSR = LPTMR_PSR_PRESCALE(0x00) | LPTMR_PSR_PBYP_MASK | LPTMR_PSR_PCS(0x01); /* Set up prescaler register */ LPTMR0_CSR = (LPTMR_CSR_TPS(0x00) | LPTMR_CSR_TEN_MASK); /* Set up control register */ #else /* SIM_SCGC6: TPM0=1 */ SIM_SCGC6 |= SIM_SCGC6_TPM0_MASK; TPM0_SC = (TPM_SC_CMOD(0x00) | TPM_SC_PS(0x00)); /* Clear status and control register */ TPM0_CNT = TPM_CNT_COUNT(0x00); /* Reset counter register */ TPM0_C1SC = 0x00U; /* Clear channel status and control register */ TPM0_C2SC = 0x00U; /* Clear channel status and control register */ TPM0_C3SC = 0x00U; /* Clear channel status and control register */ TPM0_C4SC = 0x00U; /* Clear channel status and control register */ TPM0_C5SC = 0x00U; /* Clear channel status and control register */ TPM0_MOD = TPM_MOD_MOD(0xFFFF); /* Set up modulo register */ TPM0_C0SC = (TPM_CnSC_CHIE_MASK | TPM_CnSC_MSA_MASK); /* Set up channel status and control register */ TPM0_C0V = TPM_CnV_VAL(0x00); /* Set up channel value register */ TPM0_SC = (TPM_SC_CMOD(0x01) | TPM_SC_PS(0x05)); /* Set up status and control register */ #endif /* RTIMER_CONF_USE_LPTMR */ PRINTF("rtimer_arch_init done\n"); }
void tpm_init(void){ PORTD->PCR[5] = PORT_PCR_MUX(4); //TPM0_CH5 PORTE->PCR[29] = PORT_PCR_MUX(3); //TPM0_CH2 SIM->SCGC6 |= SIM_SCGC6_TPM0_MASK; //dolaczenie sygnalu taktujacego do modulu TMP SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK); //dolaczenie sygnalu taktujacego do portu D i E, zrobione tez w leds initializze SIM->SOPT2 |= SIM_SOPT2_TPMSRC(1); // MCGFLLCLK clock or MCGPLLCLK/2 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCGPLLCLK clock with fixed divide by two TPM0->MOD = TPM_MOD_MOD(4095); TPM0->CNT |= TPM_CNT_COUNT_SHIFT; //reset counter //edge aligned pwm TPM0->CONTROLS[2].CnSC |= TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK; //high true pulses TPM0->CONTROLS[5].CnSC |= TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_ELSA_MASK; //low true pulses //edge aligned pwm end //center aligned PWM /* TPM0->CONTROLS[2].CnSC |= TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK; //high-true pulses TPM0->CONTROLS[5].CnSC |= TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK; //low true pulses */ //center aligned PWM end TPM0->CONTROLS[2].CnV = TPM_CnV_VAL(0); //poczatkowa wartosc wspolczyynika wypelninia TPM0->CONTROLS[5].CnV = TPM_CnV_VAL(0); //poczatkowa wartosc wspolczyynika wypelninia TPM0->SC = TPM_SC_PS(0x07) | TPM_SC_CPWMS_MASK | TPM_SC_CMOD(0x01); //divide by 128 !! //upcounting //increment every counter clock }
/* ===================================================================*/ LDD_TDeviceData* TU2_Init(LDD_TUserData *UserDataPtr) { TU2_TDeviceData *DeviceDataPrv; if (PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU2_ID] == NULL) { /* Allocate device structure */ /* {FreeRTOS RTOS Adapter} Driver memory allocation: RTOS function call is defined by FreeRTOS RTOS Adapter property */ DeviceDataPrv = (TU2_TDeviceData *)pvPortMalloc(sizeof(TU2_TDeviceData)); #if FreeRTOS_CHECK_MEMORY_ALLOCATION_ERRORS if (DeviceDataPrv == NULL) { return (NULL); } #endif DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr = 1U; /* First initialization */ } else { /* Memory is already allocated */ DeviceDataPrv = (TU2_TDeviceDataPtr) PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU2_ID]; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr++; /* Increment counter of initialization */ return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ } /* SIM_SCGC6: TPM1=1 */ SIM_SCGC6 |= SIM_SCGC6_TPM1_MASK; /* TPM1_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DMA=0,TOF=0,TOIE=0,CPWMS=0,CMOD=0,PS=0 */ TPM1_SC = (TPM_SC_CMOD(0x00) | TPM_SC_PS(0x00)); /* Clear status and control register */ /* TPM1_CNT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNT=0 */ TPM1_CNT = TPM_CNT_COUNT(0x00); /* Reset counter register */ /* TPM1_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ TPM1_C0SC = 0x00U; /* Clear channel status and control register */ /* TPM1_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ TPM1_C1SC = 0x00U; /* Clear channel status and control register */ /* TPM1_MOD: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MOD=0x02B3 */ TPM1_MOD = TPM_MOD_MOD(0x02B3); /* Set up modulo register */ /* TPM1_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=1,MSA=0,ELSB=1,ELSA=1,??=0,DMA=0 */ TPM1_C0SC = (TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_ELSA_MASK); /* Set up channel status and control register */ /* TPM1_C0V: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,VAL=0 */ TPM1_C0V = TPM_CnV_VAL(0x00); /* Set up channel value register */ /* PORTE_PCR20: ISF=0,MUX=3 */ PORTE_PCR20 = (uint32_t)((PORTE_PCR20 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x04) )) | (uint32_t)( PORT_PCR_MUX(0x03) )); DeviceDataPrv->Source = TPM_PDD_SYSTEM; /* Store clock source */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU2_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ }
/* ===================================================================*/ LDD_TDeviceData* TU1_Init(LDD_TUserData *UserDataPtr) { TU1_TDeviceData *DeviceDataPrv; if (PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID] == NULL) { /* Allocate device structure */ /* {FreeRTOS RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr = 1U; /* First initialization */ } else { /* Memory is already allocated */ DeviceDataPrv = (TU1_TDeviceDataPtr) PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID]; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr++; /* Increment counter of initialization */ return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ } /* SIM_SCGC6: TPM1=1 */ SIM_SCGC6 |= SIM_SCGC6_TPM1_MASK; /* TPM1_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DMA=0,TOF=0,TOIE=0,CPWMS=0,CMOD=0,PS=0 */ TPM1_SC = (TPM_SC_CMOD(0x00) | TPM_SC_PS(0x00)); /* Clear status and control register */ /* TPM1_CNT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNT=0 */ TPM1_CNT = TPM_CNT_COUNT(0x00); /* Reset counter register */ /* TPM1_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ TPM1_C0SC = 0x00U; /* Clear channel status and control register */ /* TPM1_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ TPM1_C1SC = 0x00U; /* Clear channel status and control register */ /* TPM1_MOD: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MOD=0xCCCC */ TPM1_MOD = TPM_MOD_MOD(0xCCCC); /* Set up modulo register */ /* TPM1_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=1,MSA=0,ELSB=1,ELSA=1,??=0,DMA=0 */ TPM1_C1SC = (TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_ELSA_MASK); /* Set up channel status and control register */ /* TPM1_C1V: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,VAL=0x0F5C */ TPM1_C1V = TPM_CnV_VAL(0x0F5C); /* Set up channel value register */ /* PORTA_PCR13: ISF=0,MUX=3 */ PORTA_PCR13 = (uint32_t)((PORTA_PCR13 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x04) )) | (uint32_t)( PORT_PCR_MUX(0x03) )); DeviceDataPrv->Source = TPM_PDD_SYSTEM; /* Store clock source */ /* TPM1_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DMA=0,TOF=0,TOIE=0,CPWMS=0,CMOD=1,PS=3 */ TPM1_SC = (TPM_SC_CMOD(0x01) | TPM_SC_PS(0x03)); /* Set up status and control register */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU1_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ }
/* TMP1 interrupt handler * We need to read TPM registers to find out which TMP1 interrupt this is; * */ void FTM1_IRQHandler() { volatile uint16_t tmp; // Channel interrupt? if ( (TPM1_C0SC & TPM_CnSC_CHF_MASK) != 0 ) { // channel 0 interrupt occurred TPM1_C0SC |= TPM_CnSC_CHF_MASK; // clear the interrupt flag // is it rising or falling edge? // We check separate pin which is used as GPIO and connected to the // SMT160 output as well. if ( (GPIOA_PDIR & (1 << SMT160_INPUT_PIN_NO)) != 0 ) { /* RISING edge detected */ if ( gsmt_start == 0 ) { /* start of pulse - first after our init */ gsmt_start = TPM_CnV_VAL(TPM1_C0V); } else { /* end of period */ tmp = TPM_CnV_VAL(TPM1_C0V); if ( tmp > gsmt_start ) tmp = tmp - gsmt_start; else /* overflow of counter while measuring */ tmp = (0xffff - gsmt_start) + tmp; //gsmt_period = tmp; /* save period */ /* save to sums if valid */ if ( tmp > SMT160_MIN_PERIOD && tmp < SMT160_MAX_PERIOD && gsmt_tmp_pulse > SMT160_MIN_PERIOD && gsmt_tmp_pulse < SMT160_MAX_PERIOD ) { // pokusne vyrazeno prumerovani... //gsmt_period = tmp; //gsmt_pulse = gsmt_tmp_pulse; gsmt_period_sum += tmp; gsmt_pulses += gsmt_tmp_pulse; gsmt_sumcnt++; if ( gsmt_sumcnt >= SMT160_SUM_NUMBER ) { gsmt_period = gsmt_period_sum / gsmt_sumcnt; gsmt_pulse = gsmt_pulses / gsmt_sumcnt; gsmt_sumcnt = 0; gsmt_period_sum = 0; gsmt_pulses = 0; } } /* end of period means also start of a new period */ gsmt_start = TPM_CnV_VAL(TPM1_C0V); } } else { /* falling edge detected */ /* = end of pulse. Wait for rising edge to measure the period */ if ( gsmt_start != 0 ) { /* end of pulse */ tmp = TPM_CnV_VAL(TPM1_C0V); if ( tmp > gsmt_start ) tmp = tmp - gsmt_start; else /* overflow of counter while measuring */ tmp = (0xffff - gsmt_start) + tmp; gsmt_tmp_pulse = tmp; //gsmt_period = 0; /* invalidate the period */ } } } // end of channel 0 interrupt /* test for TOF interrupt if ( (TPM1_SC & TPM_SC_TOF_MASK) != 0 ) { // TOF occurred TPM1_SC |= TPM_SC_TOF_MASK; // clear TOF by writing 1 }*/ }
/* ===================================================================*/ LDD_TDeviceData* TU2_Init(LDD_TUserData *UserDataPtr) { TU2_TDeviceData *DeviceDataPrv; if (PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU2_ID] == NULL) { /* Allocate device structure */ /* {FreeRTOS RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr = 1U; /* First initialization */ } else { /* Memory is already allocated */ DeviceDataPrv = (TU2_TDeviceDataPtr) PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU2_ID]; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr++; /* Increment counter of initialization */ return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ } /* Interrupt vector(s) allocation */ /* {FreeRTOS RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_TPM1__BAREBOARD_RTOS_ISRPARAM = DeviceDataPrv; /* SIM_SCGC6: TPM1=1 */ SIM_SCGC6 |= SIM_SCGC6_TPM1_MASK; /* TPM1_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DMA=0,TOF=0,TOIE=0,CPWMS=0,CMOD=0,PS=0 */ TPM1_SC = (TPM_SC_CMOD(0x00) | TPM_SC_PS(0x00)); /* Clear status and control register */ /* TPM1_CNT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNT=0 */ TPM1_CNT = TPM_CNT_COUNT(0x00); /* Reset counter register */ /* TPM1_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ TPM1_C0SC = 0x00U; /* Clear channel status and control register */ /* TPM1_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ TPM1_C1SC = 0x00U; /* Clear channel status and control register */ /* TPM1_MOD: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MOD=0xFFFF */ TPM1_MOD = TPM_MOD_MOD(0xFFFF); /* Set up modulo register */ /* TPM1_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=1,MSB=1,MSA=0,ELSB=1,ELSA=1,??=0,DMA=0 */ TPM1_C1SC = TPM_CnSC_CHIE_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_ELSA_MASK; /* Set up channel status and control register */ /* TPM1_C1V: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,VAL=0 */ TPM1_C1V = TPM_CnV_VAL(0x00); /* Set up channel value register */ /* PORTB_PCR1: ISF=0,MUX=3 */ PORTB_PCR1 = (uint32_t)((PORTB_PCR1 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x04) )) | (uint32_t)( PORT_PCR_MUX(0x03) )); DeviceDataPrv->EnEvents = 0x01U; /* Enable selected events */ DeviceDataPrv->Source = TPM_PDD_SYSTEM; /* Store clock source */ /* NVIC_IPR4: PRI_18=0x80 */ NVIC_IPR4 = (uint32_t)((NVIC_IPR4 & (uint32_t)~(uint32_t)( NVIC_IP_PRI_18(0x7F) )) | (uint32_t)( NVIC_IP_PRI_18(0x80) )); /* NVIC_ISER: SETENA|=0x00040000 */ NVIC_ISER |= NVIC_ISER_SETENA(0x00040000); /* TPM1_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DMA=0,TOF=0,TOIE=0,CPWMS=0,CMOD=0,PS=4 */ TPM1_SC = (TPM_SC_CMOD(0x00) | TPM_SC_PS(0x04)); /* Set up status and control register */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU2_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ }