void SiiMhlTxDrvTmdsControl (bool_t enable)
{
if (enable)
{
tmdsPowRdy = true;
SiiRegModify(REG_AUDP_TXCTRL, BIT0, SET_BITS);
if (1)//(SiiVideoInputIsValid())
{
SiiRegModify(REG_TMDS_CCTRL, TMDS_OE, SET_BITS);
SendAudioInfoFrame();
SendAviInfoframe();
TX_DEBUG_PRINT(("TMDS Output Enabled\n"));
}
else
{
TX_DEBUG_PRINT(("TMDS Output not Enabled due to invalid input\n"));
}
}
else
{
SiiRegModify(REG_TMDS_CCTRL, TMDS_OE, CLEAR_BITS);
SiiRegModify(REG_AUDP_TXCTRL, BIT0, CLEAR_BITS);
tmdsPowRdy = false;
TX_DEBUG_PRINT(("TMDS Ouput Disabled\n"));
}
}
static void Int5Isr (void)
{
uint8_t int5Status;
int5Status = SiiRegRead(REG_INTR5);
if (int5Status)
{
#if (SYSTEM_BOARD == SB_STARTER_KIT_X01)
if((int5Status & BIT3) || (int5Status & BIT2))
{
TX_DEBUG_PRINT (("** Apply MHL FIFO Reset\n"));
SiiRegModify(REG_SRST, BIT4, SET_BITS);
SiiRegModify(REG_SRST, BIT4, CLEAR_BITS);
}
#endif
if (int5Status & BIT4)
{
TX_DEBUG_PRINT (("** PXL Format changed\n"));
#ifndef __KERNEL__
SiiOsBumpMhlTxEvent();
#else
//SiiTriggerExtInt();
#endif
}
SiiRegWrite(REG_INTR5, int5Status);
}
}
static void Int1Isr(void)
{
uint8_t regIntr1;
regIntr1 = SiiRegRead(REG_INTR1);
if (regIntr1)
{
SiiRegWrite(REG_INTR1,regIntr1);
if (BIT6 & regIntr1)
{
uint8_t cbusStatus;
cbusStatus = SiiRegRead(REG_MSC_REQ_ABORT_REASON);
TX_DEBUG_PRINT(("Drv: dsHpdStatus =%02X\n", (int) dsHpdStatus));
if(BIT6 & (dsHpdStatus ^ cbusStatus))
{
uint8_t status = cbusStatus & BIT6;
TX_DEBUG_PRINT(("Drv: Downstream HPD changed to: %02X\n", (int) cbusStatus));
SiiMhlTxNotifyDsHpdChange( status );
if(status)
{
AudioVideoIsr(true);
}
dsHpdStatus = cbusStatus;
}
}
if(BIT7 & regIntr1)
{
TX_DEBUG_PRINT(("MHL soft interrupt triggered \n"));
}
}
}
void SiiMhlTxDeviceIsr( void )
{
uint8_t intMStatus, i;
#ifdef TRACE_INT_TIME
unsigned long K1;
unsigned long K2;
printk("-------------------SiiMhlTxDeviceIsr start -----------------\n");
K1 = get_jiffies_64();
#endif
i=0;
do
{
if( POWER_STATE_D0_MHL != fwPowerState )
{
if(I2C_INACCESSIBLE == Int4Isr())
{
TX_DEBUG_PRINT(("Drv: I2C_INACCESSIBLE in Int4Isr in not D0 mode\n"));
return;
}
}
else if( POWER_STATE_D0_MHL == fwPowerState )
{
if(I2C_INACCESSIBLE == Int4Isr())
{
TX_DEBUG_PRINT(("Drv: I2C_INACCESSIBLE in Int4Isr in D0 mode\n"));
return;
}
MhlCbusIsr();
Int5Isr();
Int1Isr();
Int2Isr();
}
if( POWER_STATE_D3 != fwPowerState )
{
MhlTxProcessEvents();
}
intMStatus = SiiRegRead(REG_INTR_STATE);
if(0xFF == intMStatus)
{
intMStatus = 0;
TX_DEBUG_PRINT(("Drv: EXITING ISR DUE TO intMStatus - 0xFF loop = [%02X] intMStatus = [%02X] \n\n", (int) i, (int)intMStatus));
}
i++;
intMStatus &= 0x01;
if(i>60)
{
TX_DEBUG_PRINT(("force exit SiiMhlTxDeviceIsr \n"));
break;
}
else if(i> 50)
{
TX_DEBUG_PRINT(("something error in SiiMhlTxDeviceIsr \n"));
}
} while (intMStatus);
#ifdef TRACE_INT_TIME
K2 = get_jiffies_64();
printk("-------------------SiiMhlTxDeviceIsr last %d ms----------------\n",(int)(K2 - K1));
#endif
}
static int Int4Isr( void )
{
uint8_t int4Status;
int4Status = SiiRegRead(REG_INTR4);
if(!int4Status)
{
}
else if(0xFF == int4Status)
{
return I2C_INACCESSIBLE;
}else
{
TX_DEBUG_PRINT(("INT4 Status = %02X\n", (int) int4Status));
if(int4Status & BIT0)
{
ProcessScdtStatusChange();
}
if(int4Status & BIT2)
{
MhlTxDrvProcessConnection();
}
else if(int4Status & BIT3)
{
TX_DEBUG_PRINT(("uUSB-A type device detected.\n"));
SiiRegWrite(REG_DISC_STAT2, 0x80);
SwitchToD3();
return I2C_INACCESSIBLE;
}
if (int4Status & BIT5)
{
MhlTxDrvProcessDisconnection();
return I2C_INACCESSIBLE;
}
if((POWER_STATE_D0_MHL != fwPowerState) && (int4Status & BIT6))
{
SwitchToD0();
ProcessRgnd();
}
if(fwPowerState != POWER_STATE_D3)
{
if (int4Status & BIT4)
{
TX_DEBUG_PRINT(("CBus Lockout\n"));
ForceUsbIdSwitchOpen();
ReleaseUsbIdSwitchOpen();
}
}
}
SiiRegWrite(REG_INTR4, int4Status);
return I2C_ACCESSIBLE;
}
///////////////////////////////////////////////////////////////////////////////
//
// SiiMhlTxDrvTmdsControl
//
// Control the TMDS output. MhlTx uses this to support RAP content on and off.
//
void SiiMhlTxDrvTmdsControl (bool_t enable)
{
if( enable )
{
SET_BIT(REG_TMDS_CCTRL, 4);
TX_DEBUG_PRINT(("Drv: TMDS Output Enabled\n"));
SiiMhlTxDrvReleaseUpstreamHPDControl(); // this triggers an EDID read
}
else
{
CLR_BIT(REG_TMDS_CCTRL, 4);
TX_DEBUG_PRINT(("Drv: TMDS Ouput Disabled\n"));
}
}
///////////////////////////////////////////////////////////////////////////////
//
// SiiMhlTxDrvReleaseUpstreamHPDControl
//
// Release the direct control of Upstream HPD.
//
void SiiMhlTxDrvReleaseUpstreamHPDControl (void)
{
// Un-force HPD (it was kept low, now propagate to source
// let HPD float by clearing reg_hpd_out_ovr_en
CLR_BIT(REG_INT_CTRL, 4);
TX_DEBUG_PRINT(("Drv: Upstream HPD released.\n"));
}
static uint8_t QualifyPathEnable(void)
{
uint8_t retVal = 0;
if (MHL_STATUS_PATH_ENABLED & mhlTxConfig.status_1) {
TX_DEBUG_PRINT(("\t\t\tMHL_STATUS_PATH_ENABLED\n"));
retVal = 1;
} else {
if (0x10 == mhlTxConfig.aucDevCapCache[DEVCAP_OFFSET_MHL_VERSION]) {
if (0x44 == mhlTxConfig.aucDevCapCache[DEVCAP_OFFSET_INT_STAT_SIZE]) {
retVal = 1;
TX_DEBUG_PRINT(("\t\t\tLegacy Support for MHL_STATUS_PATH_ENABLED\n"));
}
}
}
return retVal;
}
void SiiMhlTxTmdsEnable(void)
{
TX_DEBUG_PRINT(("MhlTx:SiiMhlTxTmdsEnable\n"));
if (MHL_RSEN & mhlTxConfig.mhlHpdRSENflags) {
TX_DEBUG_PRINT(("\tMHL_RSEN\n"));
if (MHL_HPD & mhlTxConfig.mhlHpdRSENflags) {
TX_DEBUG_PRINT(("\t\tMHL_HPD\n"));
if (QualifyPathEnable()) {
if (RAP_CONTENT_ON & mhlTxConfig.rapFlags) {
TX_DEBUG_PRINT(("\t\t\t\tRAP CONTENT_ON\n"));
SiiMhlTxDrvTmdsControl(true);
}
}
}
}
}
bool_t SiiMhlTxChipInitialize ( void )
{
unsigned int initState = 0;
tmdsPowRdy = false;
mscCmdInProgress = false;
dsHpdStatus = 0;
fwPowerState = POWER_STATE_D0_NO_MHL;
SI_OS_DISABLE_DEBUG_CHANNEL(SII_OSAL_DEBUG_SCHEDULER);
//memset(&video_data, 0x00, sizeof(video_data));
video_data.inputColorSpace = COLOR_SPACE_RGB;
video_data.outputColorSpace = COLOR_SPACE_RGB;
video_data.outputVideoCode = 2;
video_data.inputcolorimetryAspectRatio = 0x18;
video_data.outputcolorimetryAspectRatio = 0x18;
video_data.output_AR = 0;
//SiiMhlTxHwReset(TX_HW_RESET_PERIOD,TX_HW_RESET_DELAY);
//SiiCraInitialize();
initState = (SiiRegRead(TX_PAGE_L0 | 0x03) << 8) | SiiRegRead(TX_PAGE_L0 | 0x02);
//TX_DEBUG_PRINT(("Drv: SiiMhlTxChipInitialize: %02X%02x\n",
// SiiRegRead(TX_PAGE_L0 | 0x03),
// SiiRegRead(TX_PAGE_L0 | 0x02)));
TX_DEBUG_PRINT(("Drv: SiiMhlTxChipInitialize: 0x%04X\n", initState));
WriteInitialRegisterValues();
#ifndef __KERNEL__
SiiOsMhlTxInterruptEnable();
#endif
SwitchToD3();
if (0xFFFF == initState)//0x8356
{
return false;
}
return true;
}
cbus_req_t *GetNextCBusTransactionWrapper(char *pszFunction)
{
TX_DEBUG_PRINT(("MhlTx:GetNextCBusTransaction: %s depth: %d head: %d tail: %d\n",
pszFunction,
(int)QUEUE_DEPTH(CBusQueue), (int)CBusQueue.head, (int)CBusQueue.tail));
return GetNextCBusTransactionImpl();
}
void CbusReset (void)
{
uint8_t idx;
TX_DEBUG_PRINT( ("CBUS reset!!!\n"));
SET_BIT(REG_SRST, 3);
HalTimerWait(2);
CLR_BIT(REG_SRST, 3);
mscCmdInProgress = false;
UNMASK_INTR_4_INTERRUPTS;
#if (SYSTEM_BOARD == SB_STARTER_KIT_X01)
UNMASK_INTR_1_INTERRUPTS;
UNMASK_INTR_2_INTERRUPTS;
UNMASK_INTR_5_INTERRUPTS;
#else
MASK_INTR_1_INTERRUPTS;
MASK_INTR_5_INTERRUPTS;
#endif
UNMASK_CBUS1_INTERRUPTS;
UNMASK_CBUS2_INTERRUPTS;
for(idx=0; idx < 4; idx++)
{
WriteByteCBUS((0xE0 + idx), 0xFF);
WriteByteCBUS((0xF0 + idx), 0xFF);
}
}
static void MhlTxDrvProcessConnection ( void )
{
TX_DEBUG_PRINT (("MHL Cable Connected. CBUS:0x0A = %02X\n", (int) SiiRegRead(REG_CBUS_BUS_STATUS)));
if( POWER_STATE_D0_MHL == fwPowerState )
{
return;
}
#ifdef __KERNEL__
//HalGpioSetPin(GPIO_M2U_VBUS_CTRL,0);
#else
pinM2uVbusCtrlM = 0;
#endif
#if (SYSTEM_BOARD == SB_EPV5_MARK_II)
pinMhlConn = 0;
pinUsbConn = 1;
#elif (SYSTEM_BOARD == SB_STARTER_KIT_X01)
#ifdef __KERNEL__
//HalGpioSetPin(GPIO_MHL_USB,0);
#else
pinMhlUsb = 0;
#endif
#endif
SiiRegWrite(REG_MHLTX_CTL1, 0x10);
fwPowerState = POWER_STATE_D0_MHL;
// change TMDS termination to 50 ohm termination(default)
//bits 1:0 set to 00
SiiRegWrite(TX_PAGE_2|0x0001, 0x00);
ENABLE_DISCOVERY;
SiiMhlTxNotifyConnection(true);
}
bool_t PutPriorityCBusTransactionWrapper(cbus_req_t *pReq)
{
bool_t retVal;
TX_DEBUG_PRINT(("MhlTx: PutPriorityCBusTransaction %02X %02X %02X depth:%d head: %d tail:%d\n", (int)pReq->command, (int)((MHL_MSC_MSG == pReq->command) ? pReq->payload_u.msgData[0] : pReq->offsetData)
,
(int)((MHL_MSC_MSG ==
pReq->command) ? pReq->payload_u.msgData[1] : pReq->payload_u.
msgData[0])
, (int)QUEUE_DEPTH(CBusQueue)
, (int)CBusQueue.head, (int)CBusQueue.tail));
retVal = PutPriorityCBusTransactionImpl(pReq);
if (!retVal) {
TX_DEBUG_PRINT(("MhlTx: PutPriorityCBusTransaction queue full, when adding event 0x%02X\n", (int)pReq->command));
}
return retVal;
}
void ProcessRgnd (void)
{
uint8_t rgndImpedance;
rgndImpedance = SiiRegRead(REG_DISC_STAT2) & 0x03;
TX_DEBUG_PRINT(("RGND = %02X : \n", (int)rgndImpedance));
if (0x02 == rgndImpedance)
{
TX_DEBUG_PRINT(("(MHL Device)\n"));
SiiMhlTxNotifyRgndMhl();
}
else
{
SiiRegModify(REG_DISC_CTRL9, BIT3, BIT3);
TX_DEBUG_PRINT(("(Non-MHL Device)\n"));
}
}
void SiiMhlTxDrvPowBitChange (bool_t enable)
{
if (enable)
{
SiiRegModify(REG_DISC_CTRL8, BIT2, SET_BITS);
TX_DEBUG_PRINT(("POW bit 0->1, set DISC_CTRL8[2] = 1\n"));
}
}
void SwitchToD0( void )
{
TX_DEBUG_PRINT(("Switch to D0\n"));
WriteInitialRegisterValues();
STROBE_POWER_ON;
fwPowerState = POWER_STATE_D0_NO_MHL;
AudioVideoIsr(true);
}
///////////////////////////////////////////////////////////////////////////
//
// MhlTxDrvProcessConnection
//
///////////////////////////////////////////////////////////////////////////
static void MhlTxDrvProcessConnection (void)
{
TX_DEBUG_PRINT (("Drv: MHL Cable Connected. CBUS:0x0A = %02X\n", (int) SiiRegRead(TX_PAGE_CBUS | 0x000A)));
if( POWER_STATE_D0_MHL == fwPowerState )
{
return;
}
// VBUS control gpio
//pinM2uVbusCtrlM = 0;
//pinMhlConn = 0;
//pinUsbConn = 1;
//
// Discovery over-ride: reg_disc_ovride
//
SiiRegWrite(REG_MHLTX_CTL1, 0x10);
fwPowerState = POWER_STATE_D0_MHL;
//
// Increase DDC translation layer timer (uint8_t mode)
// Setting DDC Byte Mode
//
SiiRegWrite(REG_CBUS_COMMON_CONFIG, 0xF2);
// Enable segment pointer safety
//SET_BIT(0x0C44, 1);
// Un-force HPD (it was kept low, now propagate to source
//CLR_BIT(REG_INT_CTRL, 4);
// Enable TMDS
//SiiMhlTxDrvTmdsControl( true );
// Change TMDS termination to 50 ohm termination (default)
// Bits 1:0 set to 00
SiiRegWrite(TX_PAGE_2 | 0x0001, 0x00);
// Keep the discovery enabled. Need RGND interrupt
ENABLE_DISCOVERY
// Wait T_SRC_RXSENSE_CHK ms to allow connection/disconnection to be stable (MHL 1.0 specs)
// TX_DEBUG_PRINT (("[%d] Drv: Wait T_SRC_RXSENSE_CHK (%d ms) before checking RSEN\n",
// (int) (HalTimerElapsed( ELAPSED_TIMER ) * MONITORING_PERIOD),
// (int) T_SRC_RXSENSE_CHK) );
//
// Ignore RSEN interrupt for T_SRC_RXSENSE_CHK duration.
// Get the timer started
//
// HalTimerSet(TIMER_TO_DO_RSEN_CHK, T_SRC_RXSENSE_CHK);
// Notify upper layer of cable connection
SiiMhlTxNotifyConnection(mhlConnected = true);
}
//------------------------------------------------------------------------------
// Function Name: siMhlTx_AudioSet()
// Function Description: Set the 9022/4 audio interface to basic audio.
//
// Accepts: none
// Returns: Success message if audio changed successfully.
// Error Code if resolution change failed
// Globals: mhlTxAv
//------------------------------------------------------------------------------
uint8_t siMhlTx_AudioSet (void)
{
TX_DEBUG_PRINT(("[MHL]: >>siMhlTx_AudioSet()\n"));
//SetAudioMute(AUDIO_MUTE_MUTED); // mute output
SetAudioMode(AVmode.audio_mode);
SetACRNValue();
return 0;
}
/*
SiiMhlTxDrvMscMsgNacked
returns:
0 - message was not NAK'ed
non-zero message was NAK'ed
*/
int SiiMhlTxDrvMscMsgNacked(void)
{
if (SiiRegRead(REG_MSC_WRITE_BURST_LEN) & MSC_MT_DONE_NACK_MASK)
{
TX_DEBUG_PRINT(("MSC MSG NAK'ed - retrying...\n\n"));
return 1;
}
return 0;
}
///////////////////////////////////////////////////////////////////////////
// ProcessRgnd
//
// H/W has detected impedance change and interrupted.
// We look for appropriate impedance range to call it MHL and enable the
// hardware MHL discovery logic. If not, disable MHL discovery to allow
// USB to work appropriately.
//
// In current chip a firmware driven slow wake up pulses are sent to the
// sink to wake that and setup ourselves for full D0 operation.
///////////////////////////////////////////////////////////////////////////
void ProcessRgnd (void)
{
uint8_t rgndImpedance;
//
// Impedance detection has completed - process interrupt
//
rgndImpedance = SiiRegRead(REG_DISC_STAT2) & 0x03;
TX_DEBUG_PRINT(("Drv: RGND = %02X : \n", (int)rgndImpedance));
//
// 00, 01 or 11 means USB.
// 10 means 1K impedance (MHL)
//
// If 1K, then only proceed with wake up pulses
if (0x02 == rgndImpedance)
{
TX_DEBUG_PRINT(("(MHL Device)\n"));
SiiMhlTxNotifyRgndMhl(); // this will call the application and then optionally call
//The sequence of events during MHL discovery is as follows:
// (i) SiI9244 blocks on RGND interrupt (Page0:0x74[6]).
// (ii) System firmware turns off its own VBUS if present.
// (iii) System firmware waits for about 200ms (spec: TVBUS_CBUS_STABLE, 100 - 1000ms), then checks for the presence of
// VBUS from the Sink.
// (iv) If VBUS is present then system firmware proceed to drive wake pulses to the Sink as described in previous
// section.
// (v) If VBUS is absent the system firmware turns on its own VBUS, wait for an additional 200ms (spec:
// TVBUS_OUT_TO_STABLE, 100 - 1000ms), and then proceed to drive wake pulses to the Sink as described in above.
// AP need to check VBUS power present or absent in here // by oscar 20110527
#if (VBUS_POWER_CHK == ENABLE) // Turn on VBUS output.
AppVbusControl( vbusPowerState = false );
#endif
TX_DEBUG_PRINT(("[MHL]: Waiting T_SRC_VBUS_CBUS_TO_STABLE (%d ms)\n", (int)T_SRC_VBUS_CBUS_TO_STABLE));
//HalTimerWait(T_SRC_VBUS_CBUS_TO_STABLE);
}
else
{
SiiRegModify(REG_DISC_CTRL9, BIT3, BIT3); // USB Established
TX_DEBUG_PRINT(("(Non-MHL Device)\n"));
}
}
bool_t PutPriorityCBusTransactionImpl(cbus_req_t *pReq)
{
if (QUEUE_FULL(CBusQueue)) {
TX_DEBUG_PRINT(("MhlTx Queque is full\n"));
return false;
}
RETREAT_QUEUE_HEAD(CBusQueue)
CBusQueue.queue[CBusQueue.head] = *pReq;
return true;
}
void SwitchToD3( void )
{
if(POWER_STATE_D3 != fwPowerState)
{
TX_DEBUG_PRINT(("Switch To D3\n"));
#ifdef __KERNEL__
//HalGpioSetPin(GPIO_M2U_VBUS_CTRL,1);
#else
pinM2uVbusCtrlM = 1;
#endif
#if (SYSTEM_BOARD == SB_EPV5_MARK_II)
pinMhlConn = 1;
pinUsbConn = 0;
#elif (SYSTEM_BOARD == SB_STARTER_KIT_X01)
#ifdef __KERNEL__
//HalGpioSetPin(GPIO_MHL_USB,1);
#else
pinMhlUsb = 1;
#endif
#endif
// change TMDS termination to high impedance
//bits 1:0 set to 03
SiiRegWrite(TX_PAGE_2|0x0001, 0x03);
SiiRegWrite(REG_MHLTX_CTL1, 0xD0);
// clear all interrupt here before go into D3 mode by oscar
SiiRegWrite(REG_INTR1,0xFF);
SiiRegWrite(REG_INTR2,0xFF);
SiiRegWrite(REG_INTR4,0xFF);
SiiRegWrite(REG_INTR5,0xFF);
SiiRegWrite(REG_CBUS_INTR_STATUS,0xFF);
SiiRegWrite(REG_CBUS_MSC_INT2_STATUS,0xFF);
#ifndef __KERNEL__
//if(HalGpioGetPin(pinAllowD3))
{
#endif
ForceUsbIdSwitchOpen();
HalTimerWait(50);
ReleaseUsbIdSwitchOpen();
//HalTimerWait(50);
CLR_BIT(REG_POWER_EN, 0);
CBusQueueReset();
fwPowerState = POWER_STATE_D3;
#ifndef __KERNEL__
}/*else
{
//fwPowerState = POWER_STATE_D0_NO_MHL;
}
*/
#endif
}
}
static void SetAudioMode(inAudioTypes_t audiomode)
{
if (audiomode >= AUD_TYP_NUM)
audiomode = I2S_48;
SiiRegWrite(REG_AUDP_TXCTRL, audioData[audiomode].regAUD_path);
SiiRegWrite(TX_PAGE_L1 | 0x14, audioData[audiomode].regAUD_mode);
SiiRegWrite(TX_PAGE_L1 | 0x1D, audioData[audiomode].regAUD_ctrl);
SiiRegWrite(TX_PAGE_L1 | 0x21, audioData[audiomode].regAUD_freq);
SiiRegWrite(TX_PAGE_L1 | 0x23, audioData[audiomode].regAUD_src);
SiiRegWrite(TX_PAGE_L1 | 0x28, audioData[audiomode].regAUD_tdm_ctrl);
// SiiRegWrite(TX_PAGE_L1 | 0x22, 0x0B);
//0x02 for word length=16bits
SiiRegWrite(TX_PAGE_L1 | 0x22, 0x02);
SiiRegWrite(TX_PAGE_L1 | 0x24,0x02);
SiiRegWrite(TX_PAGE_L1 | 0x15, 0x00);
//0x7A:0x24 = 0x0B for word lenth is defult 24bit
TX_DEBUG_PRINT(("SiiRegRead(TX_PAGE_L1 | 0x21)=0x%x\n",SiiRegRead(TX_PAGE_L1 | 0x21)));
TX_DEBUG_PRINT(("SiiRegRead(TX_PAGE_L1 | 0x1D)=0x%x\n",SiiRegRead(TX_PAGE_L1 | 0x1D)));
}
//------------------------------------------------------------------------------
// Function: SendAddr
// Description:
//------------------------------------------------------------------------------
static uint8_t I2CSendAddr(uint8_t addr, uint8_t read)
{
volatile uint8_t x = 0; //delay variable
//generate START condition
SET_SCL();
#if 0
if(GET_SCL)
TX_DEBUG_PRINT(("GET_SCL is high rightly \n"));
else
TX_DEBUG_PRINT(("GET_SCL is low wrong\n"));
#endif
x++; //short delay to keep setup times in spec
CLEAR_SDA();
#if 0
if(!GET_SDA)
TX_DEBUG_PRINT(("GET_SDA is low rightly\n"));
else
TX_DEBUG_PRINT(("GET_SDA is high wrong\n"));
#endif
x++;
x++;
x++;
CLEAR_SCL();
#if 0
if(!GET_SCL)
TX_DEBUG_PRINT(("GET_SCL is low rightly\n"));
else
TX_DEBUG_PRINT(("GET_SCL is high wrong\n"));
#endif
x++;
return (I2CSendByte(addr|read)); //send address uint8_t with read/write bit
}
///////////////////////////////////////////////////////////////////////////////
//
// Function Name: MHLSinkOrDonglePowerStatusCheck()
//
// Function Description: Check MHL device is dongle or sink to set inputting current limitation.
//
void MHLSinkOrDonglePowerStatusCheck (void)
{
uint8_t RegValue;
if( POWER_STATE_D0_MHL == fwPowerState )
{
SiiRegWrite( REG_CBUS_PRI_ADDR_CMD, MHL_DEV_CATEGORY_OFFSET ); // DevCap 0x02
SiiRegWrite( REG_CBUS_PRI_START, MSC_START_BIT_READ_REG ); // execute DevCap reg read command
RegValue = SiiRegRead( REG_CBUS_PRI_RD_DATA_1ST );
TX_DEBUG_PRINT(("[MHL]: Device Category register=0x%02X...\n", (int)RegValue));
if( MHL_DEV_CAT_DONGLE == (RegValue & 0x0F) )
{
TX_DEBUG_PRINT(("[MHL]: DevTypeValue=0x%02X, the peer is a dongle, please limit the VBUS current input from dongle to be 100mA...\n", (int)RegValue));
}
else if( MHL_DEV_CAT_SINK == (RegValue & 0x0F) )
{
TX_DEBUG_PRINT(("[MHL]: DevTypeValue=0x%02X, the peer is a sink, limit the VBUS current input from sink to be 500mA...\n", (int)RegValue));
}
}
}
static void MhlTxDrvProcessDisconnection ( void )
{
TX_DEBUG_PRINT(("MhlTxDrvProcessDisconnection\n"));
SiiRegWrite(REG_INTR4, SiiRegRead(REG_INTR4));
dsHpdStatus &= ~BIT6;
SiiRegWrite(REG_MSC_REQ_ABORT_REASON, dsHpdStatus);
SiiMhlTxNotifyDsHpdChange(0);
if( POWER_STATE_D0_MHL == fwPowerState )
{
SiiMhlTxNotifyConnection(false);
}
SwitchToD3();
}
static void SendAviInfoframe (void)
{
uint8_t ifData[SIZE_AVI_INFOFRAME];
extern uint8_t VIDEO_CAPABILITY_D_BLOCK_found;
ifData[0] = 0x82;
ifData[1] = 0x02;
ifData[2] = 0x0D;
ifData[3] = 0x00;
ifData[4] = video_data.outputColorSpace << 5;
ifData[5] = video_data.outputcolorimetryAspectRatio;
if(VIDEO_CAPABILITY_D_BLOCK_found){
ifData[6] = 0x04;
TX_DEBUG_PRINT(("VIDEO_CAPABILITY_D_BLOCK_found = true, limited range\n"));
}
else{
ifData[6] = 0x00;
TX_DEBUG_PRINT(("VIDEO_CAPABILITY_D_BLOCK_found= false. defult range\n"));
}
//ifData[4] = video_data.outputColorSpace << 5;
ifData[7] = video_data.inputVideoCode;
TX_DEBUG_PRINT(("video_data.inputVideoCode:0x%02x, video_data.outputVideoCode=0x%x\n",(int)video_data.inputVideoCode,video_data.outputVideoCode));
//ifData[7] = video_data.outputVideoCode;
ifData[8] = 0x00;
ifData[9] = 0x00;
ifData[10] = 0x00;
ifData[11] = 0x00;
ifData[12] = 0x00;
ifData[13] = 0x00;
ifData[14] = 0x00;
ifData[15] = 0x00;
ifData[16] = 0x00;
ifData[3] = CalculateInfoFrameChecksum(ifData);
SiiRegModify(TX_PAGE_L1 | 0x3E, BIT0|BIT1, CLEAR_BITS);
SiiRegWriteBlock(TX_PAGE_L1 | 0x0040, ifData, SIZE_AVI_INFOFRAME);
SiiRegModify(TX_PAGE_L1 | 0x3E, BIT0|BIT1, SET_BITS);
}
static irqreturn_t Sii8334_mhl_interrupt(int irq, void *dev_id)
{
unsigned long lock_flags = 0;
disable_irq_nosync(irq);
spin_lock_irqsave(&sii8334_lock, lock_flags);
//printk("The sii8334 interrupt handeler is working..\n");
TX_DEBUG_PRINT(("The most of sii8334 interrupt work will be done by following tasklet..\n"));
schedule_work(sii8334work);
//printk("The sii8334 interrupt's top_half has been done and bottom_half will be processed..\n");
spin_unlock_irqrestore(&sii8334_lock, lock_flags);
return IRQ_HANDLED;
}
static void ProcessScdtStatusChange(void)
{
uint8_t scdtStatus;
uint8_t mhlFifoStatus;
scdtStatus = SiiRegRead(REG_TMDS_CSTAT);
TX_DEBUG_PRINT(("Drv: ProcessScdtStatusChange scdtStatus: 0x%02x\n", scdtStatus));
if (scdtStatus & 0x02)
{
mhlFifoStatus = SiiRegRead(REG_INTR5);
TX_DEBUG_PRINT(("MHL FIFO status: 0x%02x\n", mhlFifoStatus));
if (mhlFifoStatus & 0x0C)
{
SiiRegWrite(REG_INTR5, 0x0C);
TX_DEBUG_PRINT(("** Apply MHL FIFO Reset\n"));
SiiRegWrite(REG_SRST, 0x94);
SiiRegWrite(REG_SRST, 0x84);
}
}
}