OPTL_NOINLINE void init() { clk::enable(); rxpin::clock::enable(); txpin::clock::enable(); rxpin::init_alternate(afnum::af); txpin::init_alternate(afnum::af); rxpin::driver_pushpull(); txpin::driver_pushpull(); USART_BRR(base) = ((2 * cpuclock) + baudrate) / (2 * baudrate); USART_CR1(base) &= ~USART_CR1_M; /* 8 data bits */ USART_CR1(base) = (USART_CR1(base) & ~USART_PARITY_MASK) | USART_PARITY_NONE; USART_CR2(base) = (USART_CR2(base) & ~USART_CR2_STOPBITS_MASK) | USART_STOPBITS_1; USART_CR3(base) = (USART_CR3(base) & ~USART_FLOWCONTROL_MASK) | USART_FLOWCONTROL_NONE; USART_CR1(base) = (USART_CR1(base) & ~USART_MODE_MASK) | USART_MODE_TX_RX; }
void usart_set_flow_control(uint32_t usart, uint32_t flowcontrol) { uint32_t reg32; reg32 = USART_CR3(usart); reg32 = (reg32 & ~USART_FLOWCONTROL_MASK) | flowcontrol; USART_CR3(usart) = reg32; }
void usart_set_flow_control(u32 usart, u32 flowcontrol) { u32 reg32; reg32 = USART_CR3(usart); reg32 = (reg32 & ~USART_FLOWCONTROL_MASK) | flowcontrol; USART_CR3(usart) = reg32; }
void UART_SetDuplex(uart_duplex duplex) { // no libopencm3 function for duplex if (duplex == UART_DUPLEX_FULL) USART_CR3(UART_CFG.uart) &= ~USART_CR3_HDSEL; else USART_CR3(UART_CFG.uart) |= USART_CR3_HDSEL; }
bool usart_get_interrupt_source(u32 usart, u32 flag) { u32 flag_set = (USART_SR(usart) & flag); /* IDLE, RXNE, TC, TXE interrupts */ if ((flag >= USART_SR_IDLE) && (flag <= USART_SR_TXE)) return ((flag_set & USART_CR1(usart)) != 0); /* Overrun error */ else if (flag == USART_SR_ORE) return (flag_set && (USART_CR3(usart) & USART_CR3_CTSIE)); return (false); }
bool usart_get_interrupt_source(uint32_t usart, uint32_t flag) { uint32_t flag_set = (USART_ISR(usart) & flag); /* IDLE, RXNE, TC, TXE interrupts */ if ((flag >= USART_ISR_IDLE) && (flag <= USART_ISR_TXE)) { return ((flag_set & USART_CR1(usart)) != 0); /* Overrun error */ } else if (flag == USART_ISR_ORE) { return flag_set && (USART_CR3(usart) & USART_CR3_CTSIE); } return false; }
/******************************************************************************* * int bsp_uart_dma_init(u32 iuart, u32 baud, u32 rxbuffsize, u32 txbuffsize, u32 dmastreamrx, u32 dmastreamtx, u32 dma_tx_int_priority); * @brief : Initialize USART/UART for DMA transfers * @param : iuart: pointer to UART base, e.g. 'USART1' * @param : baud: name says it all, e.g. '921600' * @param : rxbuffsize: number of bytes in a circular tx buffer * @param : txbuffsize" number of bytes in a circular rx buffer * @param : dmastreamrx: DMA stream number for RX (0 - 7) * @param : dmastreamtx: DMA stream number for TX (0 - 7) * @param : dma_tx_int_priority: interrupt priority, (0x00 - 0xf0) e.g. 0xc0, low 4 bits zero * @return : 0 = success; fail traps to 'panic_leds' *******************************************************************************/ int bsp_uart_dma_init(u32 iuart, u32 baud, u32 rxbuffsize, u32 txbuffsize, u32 dmastreamrx, u32 dmastreamtx, u32 dma_tx_int_priority) { u32 cb_Idx; // Used "everywhere" to index into the control block array int tmp; struct UARTPINS uartpins; struct IRQNUM dma_irq_number_tx; struct IRQNUM dma_irq_number_rx; u32 dma_x; u32 dma_channel_number_rx = 4; // Initialize to prevent compiler warning u32 dma_channel_number_tx = 5; /* Be sure arguments passed are within range */ if (dmastreamrx > 7) bsp_panic(-1); if (dmastreamtx > 7) bsp_panic(-2); if ((dma_tx_int_priority & 0xffffff0f) != 0) bsp_panic(-3); // Bogus priority cb_Idx = mapindex(iuart); // Map usart/uart register base to control block index /* Convert dma stream to dma base and irq number */ dma_irq_number_tx = irq_given_datastream(iuart, dmastreamtx); // TX dma_irq_number_rx = irq_given_datastream(iuart, dmastreamrx); // RX /* The DMA determined should be the same...mostly a debugging issue. */ if (dma_irq_number_tx.dma != dma_irq_number_rx.dma) bsp_panic(-333); dma_x = dma_irq_number_tx.dma; // Lazy way of dealing with it later /* Set dma stream interrupt to revector to this routine; check if dma is in use. */ tmp = nvic_dma_stream_vector_add( (void(*)(u32*))&DMA_UART_IRQHandler, (u32*)&cb_uart[cb_Idx], dma_irq_number_tx.num, dmastreamtx); if (tmp != 0) bsp_panic(-30 + tmp); /* RX doesn't interrupt, but we need to show that the stream has been taken */ tmp = nvic_dma_stream_vector_add( (void(*)(u32*))&DMA_UART_IRQHandler, (u32*)&cb_uart[cb_Idx], dma_irq_number_rx.num, dmastreamrx); if (tmp != 0) bsp_panic(-130 + tmp); /* Load some parameters that might be important. */ cb_uart[cb_Idx].idma = dma_x; // Save dma register base address cb_uart[cb_Idx].rxdma_stream = dmastreamrx; // Save stream number cb_uart[cb_Idx].txdma_stream = dmastreamtx; // Save stream number cb_uart[cb_Idx].iuart = iuart; // Save uart register base address cb_uart[cb_Idx].flag = 2; // Show this setup for dma driven /* Find DMA channel numbers for RX and TX, given stream number */ switch (dma_x) { case DMA1_BASE: if (dma1_rxstreamtbl_4[dmastreamrx & 0x7] == iuart) {dma_channel_number_rx = 4; break;} if (dma1_rxstreamtbl_5[dmastreamrx & 0x7] == iuart) {dma_channel_number_rx = 5; break;} bsp_panic(-6); // RX stream specified is not compatible with UART/DMA1 case DMA2_BASE: if (dma2_rxstreamtbl_4[dmastreamrx & 0x7] == iuart) {dma_channel_number_rx = 4; break;} if (dma2_rxstreamtbl_5[dmastreamrx & 0x7] == iuart) {dma_channel_number_rx = 5; break;} bsp_panic(-7); // RX stream specified is not compatible with UART/DMA2 default: bsp_panic(-8); // Something seriously wrong here! } switch (dma_x) { case DMA1_BASE: if (dma1_txstreamtbl_4[dmastreamtx & 0x7] == iuart) {dma_channel_number_tx = 4; break;} if (dma1_txstreamtbl_5[dmastreamtx & 0x7] == iuart) {dma_channel_number_tx = 5; break;} if (dma1_txstreamtbl_7[dmastreamtx & 0x7] == iuart) {dma_channel_number_tx = 7; break;} bsp_panic(-9); // TX stream specified is not compatible with UART/DMA1 case DMA2_BASE: if (dma2_txstreamtbl_4[dmastreamtx & 0x7] == iuart) {dma_channel_number_tx = 4; break;} if (dma2_txstreamtbl_5[dmastreamtx & 0x7] == iuart) {dma_channel_number_tx = 5; break;} bsp_panic(-10); // TX stream specified is not compatible with UART/DMA2 default: bsp_panic(-11); // Something seriously wrong here! } static u32 qqq; qqq = dma_channel_number_rx; /* At this point we (should!) have a good DMA channel and stream that associates with the UART. */ /* Set up UART pins, port & uart clockings. THIS IS BOARD SPECIFIC */ if (uart_pins(iuart, &uartpins) != 0) bsp_panic(-15); /* Setup baud rate */ usartx_setbaud (iuart, uartpins.pclk, baud); /* Obtain some buffer space */ getbuff(cb_Idx, rxbuffsize, txbuffsize); /* ---------- Set up UART ----------------------------------------------------------------------------------- */ /* Set up CR1 ---------------------------------------------------- */ USART_CR1(iuart) |= (1<<13) | (1<<3) | (1<<2);// Set Usart enable, tx enable, rx enable /* Hook up usart tx and rx to dma channels */ USART_CR3(iuart) |= (1<<7) | (1<<6); /* Setup CR2 ------------------------------------------------------------------- */ /* After reset CR2 is 0x0000 and this is just fine */ /* --------- Set up the DMA channels ------------------------------------------------------------------------ */ /* Set peripheral address for RX */ DMA_SPAR(dma_x,dmastreamrx) = (u32*)(iuart + 0x04); // Address of uart DR register /* Set peripheral address for TX */ DMA_SPAR(dma_x,dmastreamtx) = (u32*)(iuart + 0x04); // Address of uart DR register /* DMA stream configuration register--RX p 325 */ // Channel number | MINC | CIRC | Per->Mem DMA_SCR(dma_x,dmastreamrx) = ( (dma_channel_number_rx<< 25) | (1<<10) | (1<<8) | (0x0<<6) ); /* DMA stream configuration register--TX */ // Channel number | MINC | CIRC | Mem->per | priority DMA_SCR(dma_x,dmastreamtx) = ( (dma_channel_number_tx<< 25) | (1<<10) | (0<<8) | (0x1<<6) | (1<<16)); /* Set RX memory address (stays forever) */ DMA_SM0AR(dma_x,dmastreamrx) = cb_uart[cb_Idx].rxbuff_base; /* Set the number of bytes in the RX buff */ DMA_SNDTR(dma_x,dmastreamrx) = cb_uart[cb_Idx].rxbuff_size; /* DMA for TX interrupts */ NVICIPR (dma_irq_number_tx.num,dma_tx_int_priority); // Set dma interrupt priority (tx) NVICISER(dma_irq_number_tx.num); // Enable dma interrupt (tx) /* Final enabling of DMA */ DMA_SCR(dma_x,dmastreamrx) |= (0x1); // Enable rx stream DMA_SCR(dma_x,dmastreamtx) |= ((1<<4)); // TCIE (xfer complete interrupt), not enable stream return 0; // SUCCESS! }
void usart_disable_error_interrupt(u32 usart) { USART_CR3(usart) &= ~USART_CR3_EIE; }
void usart_enable_error_interrupt(u32 usart) { USART_CR3(usart) |= USART_CR3_EIE; }
void usart_disable_tx_dma(u32 usart) { USART_CR3(usart) &= ~USART_CR3_DMAT; }
void usart_enable_tx_dma(u32 usart) { USART_CR3(usart) |= USART_CR3_DMAT; }
void usart_enable_rx_dma(u32 usart) { USART_CR3(usart) |= USART_CR3_DMAR; }
/** @brief USART Enable Half-duplex - The TX and RX lines are internally connected. - The RX pin is no longer used - The TX pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in reception. It means that the I/O must be configured so that TX is configured as alternate function open-drain with an external pull-up. Apart from this, the communication protocol is similar to normal USART mode. Any conflicts on the line must be managed by software @This bit field can only be written when the USART is disabled. @param[in] usart USART block register address base @ref usart_reg_base */ void usart_enable_halfduplex(uint32_t usart) { USART_CR3(usart) |= USART_CR3_HDSEL; }
/** @brief USART Disable Half-duplex @This bit field can only be written when the USART is disabled. @param[in] usart USART block register address base @ref usart_reg_base */ void usart_disable_halfduplex(uint32_t usart) { USART_CR3(usart) &= ~USART_CR3_HDSEL; }
void usart_set_flow_control(uint32_t usart, uint32_t flowctrl) { USART_CR3(usart) = (USART_CR3(usart) & ~USART_FLOWCONTROL) | flowctrl; }
void usart_disable_tx_dma(uint32_t usart) { USART_CR3(usart) &= ~USART_CR3_DMAT; }
void usart_enable_tx_dma(uint32_t usart) { USART_CR3(usart) |= USART_CR3_DMAT; }