/*! \brief wakeup method in mute mode configure \param[in] usart_periph: USARTx(x=0,1) \param[in] wmehtod: two method be used to enter or exit the mute mode. \arg USART_WM_IDLE: Idle Line \arg USART_WM_ADDR: address mark \param[out] none \retval none */ void usart_mute_mode_wakeup_config(uint32_t usart_periph,uint32_t wmehtod) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); USART_CTL0(usart_periph) &=~(USART_CTL0_WM ); USART_CTL0(usart_periph) |= wmehtod; }
/** Check whether the serial is in busy state * * @return 0: all the serial is free to use, 1: some serial is in busy in transfer */ int serial_busy_state_check(void) { #if defined(USART0) if ((USART_CTL0(USART0) & USART_CTL0_UEN) && !(USART_STAT0(USART0) & USART_STAT0_TC)) { return 1; } #endif #if defined(USART1) if ((USART_CTL0(USART1) & USART_CTL0_UEN) && !(USART_STAT0(USART1) & USART_STAT0_TC)) { return 1; } #endif #if defined(USART2) if ((USART_CTL0(USART2) & USART_CTL0_UEN) && !(USART_STAT0(USART2) & USART_STAT0_TC)) { return 1; } #endif #if defined(UART3) if ((USART_CTL0(UART3) & USART_CTL0_UEN) && !(USART_STAT0(UART3) & USART_STAT0_TC)) { return 1; } #endif #if defined(UART4) if ((USART_CTL0(UART4) & USART_CTL0_UEN) && !(USART_STAT0(UART4) & USART_STAT0_TC)) { return 1; } #endif /* no serial is in busy state */ return 0; }
/*! \brief driver enable de-assertion time configure \param[in] usart_periph: USARTx(x=0) \param[in] dedtime: driver enable de-assertion time \param[out] none \retval none */ void usart_driver_deassertime_config(uint32_t usart_periph,uint32_t dedtime) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); USART_CTL0(usart_periph) &=~(USART_CTL0_DED); USART_CTL0(usart_periph) |=(USART_CTL0_DED & ((dedtime)<<16)); }
/*! \brief driver enable assertion time configure \param[in] usart_periph: USARTx(x=0) \param[in] deatime: driver enable assertion time \param[out] none \retval none */ void usart_driver_assertime_config(uint32_t usart_periph,uint32_t deatime) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); USART_CTL0(usart_periph) &=~(USART_CTL0_DEA); USART_CTL0(usart_periph) |=(USART_CTL0_DEA & ((deatime)<<21)); }
/*! \brief configure the USART oversample mode \param[in] usart_periph: USARTx(x=0,1) \param[in] oversamp: oversample value \arg USART_OVSMOD_8: 8 bits \arg USART_OVSMOD_16: 16 bits \param[out] none \retval none */ void usart_oversample_config(uint32_t usart_periph,uint32_t oversamp) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); /* clear OM bit */ USART_CTL0(usart_periph) &=~(USART_CTL0_OVSMOD); USART_CTL0(usart_periph) |= oversamp; }
/*! \brief configure usart word length \param[in] usart_periph: USARTx(x=0.1) \param[in] wlen: usart word length configure \arg USART_WL_8BIT: 8 bits \arg USART_WL_9BIT: 9 bits \param[out] none \retval none */ void usart_word_length_set(uint32_t usart_periph,uint32_t wlen) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); /* clear USART_CTL0 WL bit */ USART_CTL0(usart_periph) &=~USART_CTL0_WL; /* configure usart word length */ USART_CTL0(usart_periph) |=wlen ; }
/*! \brief configure usart parity function \param[in] usart_periph: USARTx(x=0.1) \param[in] paritycfg: usart parity configure \arg USART_PM_NONE: no parity \arg USART_PM_ODD: odd parity \arg USART_PM_EVEN: even parity \param[out] none \retval none */ void usart_parity_config(uint32_t usart_periph,uint32_t paritycfg) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); /* clear USART_CTL0 PM,PCEN Bits */ USART_CTL0(usart_periph) &=~(USART_CTL0_PM|USART_CTL0_PCEN); /* configure usart parity mode */ USART_CTL0(usart_periph) |=paritycfg ; }
/*! \brief NACK disable in smartcard mode \param[in] usart_periph: USARTx(x=0) \param[out] none \retval none */ void usart_smartcard_mode_nack_disable(uint32_t usart_periph) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); USART_CTL2(usart_periph) &=~(USART_CTL2_NKEN); }
/*! \brief address detection mode configure \param[in] usart_periph: USARTx(x=0,1) \param[in] addmod: address detection mode \arg USART_ADDM_4B: 4bits \arg USART_ADDM_7B: 7bits \param[out] none \retval none */ void usart_address_detection_mode_config(uint32_t usart_periph,uint32_t addmod) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); USART_CTL1(usart_periph) &=~(USART_CTL1_ADDM ); USART_CTL1(usart_periph) |= (USART_CTL1_ADDM & (addmod)); }
/*! \brief clock disable \param[in] usart_periph: USARTx(x=0) \param[out] none \retval none */ void usart_clock_disable(uint32_t usart_periph) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); USART_CTL1(usart_periph) &=~(USART_CTL1_CKEN); }
/*! \brief disable usart interrupt \param[in] usart_periph: USARTx(x=0) \param[in] inttype: interrupt type \arg USART_INT_IDLEIE: idle interrupt \arg USART_INT_RBNEIE: read data buffer not empty interrupt and overrun error interrupt \arg USART_INT_TCIE: transmission complete interrupt \arg USART_INT_TBEIE: transmit data register empty interrupt \arg USART_INT_PERRIE: parity error interrupt \arg USART_INT_AMIE: address match interrupt \arg USART_INT_RTIE: receiver timeout interrupt \arg USART_INT_EBIE: end of block interrupt \arg USART_INT_LBDIE: LIN break detection interrupt \arg USART_INT_ERRIE: error interrupt enable in multibuffer communication \arg USART_INT_CTSIE: CTS interrupt \arg USART_INT_WUIE: wakeup from deep-sleep mode interrupt \param[out] none \retval none */ void usart_interrupt_disable(uint32_t usart_periph,uint32_t inttype) { uint32_t reg=0,intdex; /* get the interrupt register */ reg=(BITS(28,29)&(inttype)); /* get the interrupt */ intdex=((~BITS(28,19))&(inttype)); switch(reg){ /* CTL0 */ case USART_CTL0_INDEX: USART_CTL0(usart_periph) &=~(intdex); break; /* CTL1 */ case USART_CTL1_INDEX: USART_CTL1(usart_periph) &=~(intdex); break; /* CTL2 */ case USART_CTL2_INDEX: USART_CTL2(usart_periph) &=~(intdex); break; default: break; } }
/*! \brief lin break detection length \param[in] usart_periph: USARTx(x=0) \param[in] lblen: lin break detection length \arg USART_LBLEN_10B: 10 bits break detection \arg USART_LBLEN_11B: 11 bits break detection \param[out] none \retval none */ void usart_lin_break_dection_length_config(uint32_t usart_periph,uint32_t lblen) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); USART_CTL1(usart_periph) |=(USART_CTL1_LBLEN & (lblen)); }
/*! \brief half-duplex disable \param[in] usart_periph: USARTx(x=0) \param[out] none \retval none */ void usart_halfduplex_disable(uint32_t usart_periph) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); USART_CTL2(usart_periph) &=~(USART_CTL2_HDEN); }
/*! \brief RS485 driver disable \param[in] usart_periph: USARTx(x=0,1) \param[out] none \retval none */ void usart_rs485_driver_disable(uint32_t usart_periph) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); USART_CTL2(usart_periph) &=~(USART_CTL2_DEM); }
/*! \brief IrDA low-power configure \param[in] usart_periph: USARTx(x=0) \param[in] irlp: IrDA low-power or normal \arg USART_IRLP_LOW: low-power \arg USART_IRLP_NORMAL: normal \param[out] none \retval none */ void usart_irda_lowpower_config(uint32_t usart_periph,uint32_t irlp) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); USART_CTL2(usart_periph) |=(USART_CTL2_IRLP & irlp); }
/*! \brief get usart interrupt status \param[in] usart_periph: USARTx(x=0) \param[in] state: status type \arg USART_STAT_PERR: PE state \arg USART_STAT_FERR: FE state \arg USART_STAT_NERR: NE state \arg USART_STAT_ORERR: ORE state \arg USART_STAT_IDLEF: idle state \arg USART_STAT_RBNE: RBNE state \arg USART_STAT_TC: TC state \arg USART_STAT_TBE: TBE state \arg USART_STAT_LBDF: LBDF state \arg USART_STAT_CTSF: CTSF state \arg USART_STAT_RTF: receive timeout state \arg USART_STAT_EBF: end of block state \arg USART_STAT_AMF: address match flag state \arg USART_STAT_WUF: wakeup from deep-sleep mode flag \param[in] inttype: interrupt type \arg USART_INT_IDLEIE: idle interrupt \arg USART_INT_RBNEIE: read data buffer not empty interrupt and overrun error interrupt \arg USART_INT_TCIE: transmission complete interrupt \arg USART_INT_TBEIE: transmit data register empty interrupt \arg USART_INT_PERRIE: parity error interrupt \arg USART_INT_AMIE: address match interrupt \arg USART_INT_RTIE: receiver timeout interrupt \arg USART_INT_EBIE: end of block interrupt \arg USART_INT_LBDIE: LIN break detection interrupt \arg USART_INT_ERRIE: error interrupt in multibuffer communication \arg USART_INT_CTSIE: CTS interrupt \arg USART_INT_WUIE: wakeup from deep-sleep mode interrupt \param[out] none \retval state of stat bit */ FlagStatus usart_interrupt_flag_get(uint32_t usart_periph,uint32_t state,uint32_t inttype) { uint32_t reg=0,intdex,intenable=0,intstate=0; /* get the interrupt register */ reg=(BITS(28,29)&(inttype)); reg=reg>>28; /* get the interrupt */ intdex=((~BITS(28,29))&(inttype)); switch(reg){ /* CTL0 */ case USART_CTL0_INDEX: intenable=USART_CTL0(usart_periph) & (intdex); break; /* CTL1 */ case USART_CTL1_INDEX: intenable=USART_CTL1(usart_periph) & (intdex); break; /* CTL2 */ case USART_CTL2_INDEX: intenable=USART_CTL2(usart_periph) & (intdex); break; default: break; } intstate=USART_STAT(usart_periph)&(state); if(intstate && intenable) return SET; return RESET; }
/*! \brief USART inverted configure \param[in] usart_periph: USARTx(x=0,1) \param[in] invertpara: refer to enum USART_INVERT_CONFIG \param[out] none \retval none */ void usart_invert_config(uint32_t usart_periph,usart_invert_enum invertpara) { USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); /* inverted or not the specified siginal */ switch(invertpara){ case USART_DINV_ENABLE: USART_CTL1(usart_periph) |= USART_CTL1_DINV; break; case USART_DINV_DISABLE: USART_CTL1(usart_periph) &=~(USART_CTL1_DINV); break; case USART_TXPIN_DISABLE: USART_CTL1(usart_periph) &=~(USART_CTL1_TINV); break; case USART_RXPIN_DISABLE: USART_CTL1(usart_periph) &=~(USART_CTL1_RINV); break; case USART_SWAP_DISABLE: USART_CTL1(usart_periph) &=~(USART_CTL1_STRP); break; case USART_TXPIN_ENABLE: USART_CTL1(usart_periph) |= USART_CTL1_TINV; break; case USART_RXPIN_ENABLE: USART_CTL1(usart_periph) |= USART_CTL1_RINV; break; case USART_SWAP_ENABLE: USART_CTL1(usart_periph) |= USART_CTL1_STRP; break; default: break; } }
/*! \brief sample bit method configure \param[in] usart_periph: USARTx(x=0,1) \param[in] osb: sample bit \arg USART_OSB_1bit: 1 bit \arg USART_OSB_3bit: 3 bits \param[out] none \retval none */ void usart_sample_bit_config(uint32_t usart_periph,uint32_t osb) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); USART_CTL2(usart_periph) &=~(USART_CTL2_OSB); USART_CTL2(usart_periph) |= (osb); }
/*! \brief IrDA mode disable \param[in] usart_periph: USARTx(x=0) \param[out] none \retval none */ void usart_irda_mode_disable(uint32_t usart_periph) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); USART_CTL2(usart_periph) &=~(USART_CTL2_IREN); }
/*! \brief address of the USART terminal \param[in] usart_periph: USARTx(x=0,1) \param[in] usartaddr: address of usart node \param[out] none \retval none */ void usart_address_config(uint32_t usart_periph,uint8_t usartaddr) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); USART_CTL1(usart_periph) &=~(USART_CTL1_ADDR); USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & ((usartaddr)<<24)); }
/*! \brief hardware flow control configure \param[in] usart_periph: USARTx(x=0,1) \param[in] hardwareflow: RTS or CTS \arg USART_CTSRTS_NONE: no hardware flow control \arg USART_RTS_ENABLE: RTS enable \arg USART_CTS_ENABLE: CTS enable \arg USART_RTS_DISABLE: RTS disable \arg USART_CTS_DISABLE: CTS disable \arg USART_CTSRTS_ENABLE: RTS,CTS enable \param[out] none \retval none */ void usart_hardware_flow_config(uint32_t usart_periph,usart_hardware_flow_enum hardwareflow) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); switch(hardwareflow){ case USART_CTSRTS_ENABLE: USART_CTL2(usart_periph) |=(USART_CTL2_RTSEN|USART_CTL2_CTSEN); break; case USART_RTS_ENABLE: USART_CTL2(usart_periph) |=USART_CTL2_RTSEN; break; case USART_CTS_ENABLE: USART_CTL2(usart_periph) |=USART_CTL2_CTSEN; break; case USART_CTS_DISABLE: USART_CTL2(usart_periph) &=(~USART_CTL2_CTSEN); break; case USART_RTS_DISABLE: USART_CTL2(usart_periph) &=(~USART_CTL2_RTSEN); break; case USART_CTSRTS_NONE: USART_CTL2(usart_periph) &=(~(USART_CTL2_CTSEN|USART_CTL2_RTSEN)); break; default: break; } }
/*! \brief configure usart baud rate value \param[in] usart_periph: USARTx(x=0,1) \param[in] baudval: baud rate value \param[out] none \retval none */ void usart_baudrate_set(uint32_t usart_periph,uint32_t baudval) { uint32_t uclk=0,intdiv=0,fradiv=0,udiv=0; switch(usart_periph){ case USART0: uclk=rcu_clock_freq_get(CK_USART); break; case USART1: uclk=rcu_clock_freq_get(CK_APB1); break; default: break; } if(USART_CTL0(usart_periph)&USART_CTL0_OVSMOD){ /* when oversampling by 8,configure the value of USART_BAUD */ udiv=((2*uclk)+baudval/2)/baudval; intdiv=udiv&0xfff0; fradiv=udiv&0x7; USART_BAUD(usart_periph) |=((USART_BAUD_FRADIV|USART_BAUD_INTDIV)&( intdiv|fradiv)); }else{ /* when oversampling by 16,configure the value of USART_BAUD */ udiv=(uclk+baudval/2)/baudval; intdiv=udiv&0xfff0; fradiv=udiv&0xf; USART_BAUD(usart_periph) |=((USART_BAUD_FRADIV|USART_BAUD_INTDIV) &( intdiv|fradiv)); } }
/*! \brief smartcard mode enable \param[in] usart_periph: USARTx(x=0) \param[out] none \retval none */ void usart_smartcard_mode_enable(uint32_t usart_periph) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); USART_CTL2(usart_periph) |=USART_CTL2_SCEN; }
/** Configure the format. Set the number of bits, parity and the number of stop bits * * @param obj The serial object * @param data_bits The number of data bits * @param parity The parity * @param stop_bits The number of stop bits */ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { uint16_t uen_flag = 0U; struct serial_s *p_obj = GET_SERIAL_S(obj); /* store the UEN flag */ uen_flag = USART_CTL0(p_obj->uart) & USART_CTL0_UEN; /* disable the UART clock first */ usart_disable(p_obj->uart); /* configurate the UART parity */ switch (parity) { case ParityOdd: p_obj->parity = USART_PM_ODD; usart_parity_config(p_obj->uart, USART_PM_ODD); break; case ParityEven: p_obj->parity = USART_PM_EVEN; usart_parity_config(p_obj->uart, USART_PM_EVEN); break; case ParityForced0: case ParityForced1: default: p_obj->parity = USART_PM_NONE; usart_parity_config(p_obj->uart, USART_PM_NONE); break; } if (p_obj->parity == USART_PM_NONE) { if (data_bits == 9) { usart_word_length_set(p_obj->uart, USART_WL_9BIT); } else if (data_bits == 8) { usart_word_length_set(p_obj->uart, USART_WL_8BIT); } else if (data_bits == 7) { return; } } else { if (data_bits == 9) { return; } else if (data_bits == 8) { usart_word_length_set(p_obj->uart, USART_WL_9BIT); } else if (data_bits == 7) { usart_word_length_set(p_obj->uart, USART_WL_8BIT); } } if (stop_bits == 2) { usart_stop_bit_set(p_obj->uart, USART_STB_2BIT); } else { usart_stop_bit_set(p_obj->uart, USART_STB_1BIT); } /* restore the UEN flag */ if (RESET != uen_flag) { usart_enable(p_obj->uart); } }
/*! \brief guard time value configure in smartcard mode \param[in] usart_periph: USARTx(x=0) \param[in] guat: guard time value \param[out] none \retval none */ void usart_guard_time_config(uint32_t usart_periph,uint32_t guat) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); USART_GP(usart_periph) &=~(USART_GP_GUAT); USART_GP(usart_periph) |=(USART_GP_GUAT & ((guat)<<8)); }
/*! \brief block length configure \param[in] usart_periph: USARTx(x=0) \param[in] bl: guard time value \param[out] none \retval none */ void usart_block_length_config(uint32_t usart_periph,uint32_t bl) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); USART_RT(usart_periph) &=~(USART_RT_BL); USART_RT(usart_periph) |=(USART_RT_BL & ((bl)<<24)); }
/** Configure the serial for the flow control. It sets flow control in the hardware * if a serial peripheral supports it, otherwise software emulation is used. * * @param obj The serial object * @param type The type of the flow control. Look at the available FlowControl types. * @param rxflow The TX pin name * @param txflow The RX pin name */ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { uint16_t uen_flag = 0U; struct serial_s *p_obj = GET_SERIAL_S(obj); /* store the UEN flag */ uen_flag = USART_CTL0(p_obj->uart) & USART_CTL0_UEN; UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS); UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS); p_obj->uart = (UARTName)pinmap_merge(uart_cts, uart_rts); MBED_ASSERT(p_obj->uart != (UARTName)NC); /* disable USART to modify CTS/RTS configuration */ usart_disable(p_obj->uart); if (type == FlowControlNone) { p_obj->hw_flow_ctl = USART_HWCONTROL_NONE; usart_hardware_flow_cts_config(p_obj->uart, USART_CTS_DISABLE); usart_hardware_flow_rts_config(p_obj->uart, USART_RTS_DISABLE); } if (type == FlowControlRTS) { MBED_ASSERT(uart_rts != (UARTName)NC); p_obj->hw_flow_ctl = USART_HWCONTROL_RTS; p_obj->pin_rts = rxflow; pinmap_pinout(rxflow, PinMap_UART_RTS); usart_hardware_flow_cts_config(p_obj->uart, USART_CTS_DISABLE); usart_hardware_flow_rts_config(p_obj->uart, USART_RTS_ENABLE); } if (type == FlowControlCTS) { MBED_ASSERT(uart_cts != (UARTName)NC); p_obj->hw_flow_ctl = USART_HWCONTROL_CTS; p_obj->pin_cts = txflow; pinmap_pinout(txflow, PinMap_UART_CTS); usart_hardware_flow_rts_config(p_obj->uart, USART_RTS_DISABLE); usart_hardware_flow_cts_config(p_obj->uart, USART_CTS_ENABLE); } if (type == FlowControlRTSCTS) { MBED_ASSERT(uart_rts != (UARTName)NC); MBED_ASSERT(uart_cts != (UARTName)NC); p_obj->hw_flow_ctl = USART_HWCONTROL_RTS_CTS; p_obj->pin_rts = rxflow; p_obj->pin_cts = txflow; pinmap_pinout(txflow, PinMap_UART_CTS); pinmap_pinout(rxflow, PinMap_UART_RTS); usart_hardware_flow_cts_config(p_obj->uart, USART_CTS_ENABLE); usart_hardware_flow_rts_config(p_obj->uart, USART_RTS_ENABLE); } /* restore the UEN flag */ if (RESET != uen_flag) { usart_enable(p_obj->uart); } }
/*! \brief USART transfer config \param[in] usart_periph: USARTx(x=0,1) \param[in] rtconfig: REN or TEN \arg USART_RTEN_DISABLE: transmit function and receiver function disable \arg USART_REN_ENABLE: enable for reception \arg USART_TEN_ENABLE: enable for transmission \arg USART_REN_DISABLE: disable for reception \arg USART_TEN_DISABLE: disable for transmission \arg USART_RTEN_ENABLE: enable for transmission and reception \param[out] none \retval none */ void usart_transfer_config(uint32_t usart_periph,usart_transfer_enum rtconfig) { switch(rtconfig){ case USART_RTEN_ENABLE: USART_CTL0(usart_periph) |=(USART_CTL0_REN|USART_CTL0_TEN); break; case USART_REN_ENABLE: USART_CTL0(usart_periph) |=USART_CTL0_REN; break; case USART_TEN_ENABLE: USART_CTL0(usart_periph) |=USART_CTL0_TEN; break; case USART_REN_DISABLE: USART_CTL0(usart_periph) &=(~USART_CTL0_REN); break; case USART_TEN_DISABLE: USART_CTL0(usart_periph) &=(~USART_CTL0_TEN); break; case USART_RTEN_DISABLE: USART_CTL0(usart_periph) &=(~(USART_CTL0_REN|USART_CTL0_TEN)); break; default: break; } USART_CTL0(usart_periph) |=USART_CTL0_UEN; }
/*! \brief configure usart stop bit length \param[in] usart_periph: USARTx(x=0.1) \param[in] stblen: usart stop bit configure \arg USART_STB_1BIT: 1 bit \arg USART_STB_2BIT: 2 bit \arg USART_STB_1_5BIT: 1.5bit \param[out] none \retval none */ void usart_stop_bit_set(uint32_t usart_periph,uint32_t stblen) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); /* clear USART_CTL1 STB bits */ USART_CTL1(usart_periph) &=~USART_CTL1_STB; USART_CTL1(usart_periph) |=stblen; }
/*! \brief wakeup mode from deep-sleep mode \param[in] usart_periph: USARTx(x=0) \param[in] wum: wakeup mode \arg USART_WUM_ADDR: WUF active on address match \arg USART_WUM_STARTB: WUF active on start bit \arg USART_WUM_RBNE: WUF active on RBNE \param[out] none \retval none */ void usart_wakeup_mode_config(uint32_t usart_periph,uint32_t wum) { /* disable USART */ USART_CTL0(usart_periph) &=~(USART_CTL0_UEN); /* reset USART_CTL2 DEP bit */ USART_CTL2(usart_periph) &=~(USART_CTL2_WUM); USART_CTL2(usart_periph) |=(USART_CTL2_WUM & (wum)) ; }