static void __init
ehci_orion_conf_mbus_windows(struct usb_hcd *hcd,
const struct mbus_dram_target_info *dram)
{
int i;
for (i = 0; i < 4; i++) {
wrl(USB_WINDOW_CTRL(i), 0);
wrl(USB_WINDOW_BASE(i), 0);
}
for (i = 0; i < dram->num_cs; i++) {
const struct mbus_dram_window *cs = dram->cs + i;
wrl(USB_WINDOW_CTRL(i), ((cs->size - 1) & 0xffff0000) |
(cs->mbus_attr << 8) |
(dram->mbus_dram_target_id << 4) | 1);
wrl(USB_WINDOW_BASE(i), cs->base);
}
}
/*
* Once all the older Marvell SoC's (Orion, Kirkwood) are converted
* to the common mvebu archticture including the mbus setup, this
* will be the only function needed to configure the access windows
*/
static void usb_brg_adrdec_setup(int index)
{
const struct mbus_dram_target_info *dram;
int i;
dram = mvebu_mbus_dram_info();
for (i = 0; i < 4; i++) {
writel(0, MVUSB_BASE(index) + USB_WINDOW_CTRL(i));
writel(0, MVUSB_BASE(index) + USB_WINDOW_BASE(i));
}
for (i = 0; i < dram->num_cs; i++) {
const struct mbus_dram_window *cs = dram->cs + i;
/* Write size, attributes and target id to control register */
writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
(dram->mbus_dram_target_id << 4) | 1,
MVUSB_BASE(index) + USB_WINDOW_CTRL(i));
/* Write base address to base register */
writel(cs->base, MVUSB_BASE(index) + USB_WINDOW_BASE(i));
}
}
static void usb_brg_adrdec_setup(int index)
{
int i;
u32 size, base, attrib;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
/* Enable DRAM bank */
switch (i) {
case 0:
attrib = MVUSB0_CPU_ATTR_DRAM_CS0;
break;
case 1:
attrib = MVUSB0_CPU_ATTR_DRAM_CS1;
break;
case 2:
attrib = MVUSB0_CPU_ATTR_DRAM_CS2;
break;
case 3:
attrib = MVUSB0_CPU_ATTR_DRAM_CS3;
break;
default:
/* invalide bank, disable access */
attrib = 0;
break;
}
size = gd->bd->bi_dram[i].size;
base = gd->bd->bi_dram[i].start;
if ((size) && (attrib))
writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
attrib, MVCPU_WIN_ENABLE),
MVUSB0_BASE + USB_WINDOW_CTRL(i));
else
writel(MVCPU_WIN_DISABLE,
MVUSB0_BASE + USB_WINDOW_CTRL(i));
writel(base, MVUSB0_BASE + USB_WINDOW_BASE(i));
}
}
/*
* USB 2.0 Bridge Address Decoding registers setup
*/
static void usb_brg_adrdec_setup(void)
{
int i;
u32 size, attrib;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
/* Enable DRAM bank */
switch (i) {
case 0:
attrib = KWCPU_ATTR_DRAM_CS0;
break;
case 1:
attrib = KWCPU_ATTR_DRAM_CS1;
break;
case 2:
attrib = KWCPU_ATTR_DRAM_CS2;
break;
case 3:
attrib = KWCPU_ATTR_DRAM_CS3;
break;
default:
/* invalide bank, disable access */
attrib = 0;
break;
}
size = kw_sdram_bs(i);
if ((size) && (attrib))
wrl(USB_WINDOW_CTRL(i),
KWCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
attrib, KWCPU_WIN_ENABLE));
else
wrl(USB_WINDOW_CTRL(i), KWCPU_WIN_DISABLE);
wrl(USB_WINDOW_BASE(i), kw_sdram_bar(i));
}
}