bool twi::ReadBytes(U8 slave_address, U8 *bytes, U8 length)
{
slave_address |= 0x01;
_error_state = TWI_RESULT_OKAY;
SendStart();
if(!SetAddress(slave_address))
{
_error_state = TWI_RESULT_NO_ACK_ON_ADDRESS;
return false;
}
do
{
SDA.set_input();
*(bytes++) = USI_TWI_Master_Transfer( true );
//*(bytes++) = 0x22;
if(length == 1) // If transmission of last byte was performed.
SendNACK();
else
SendACK();
}while(--length > 0);
SendStop();
return true;
}
bool twi::WriteBytes(U8 slave_address, U8* bytes, U8 length)
{
_error_state = TWI_RESULT_OKAY;
SendStart();
if(!SetAddress(slave_address))
{
_error_state = TWI_RESULT_NO_ACK_ON_ADDRESS;
return false;
}
/*Write address and Read/Write data */
do
{
/* Write a byte */
PullPin(&SCL);
USIDR = (*(bytes++));
USI_TWI_Master_Transfer( true ); // Send 8 bits on bus.
/* Clock and verify (N)ACK from slave */
if(!ACK_received())
{
_error_state = TWI_RESULT_NO_ACK_ON_DATA;
return false;
}
}while(--length > 0);
SendStop();
return true;
}
bool twi::WriteByte(U8 b)
{
/* Write a byte */
PullPin(&SCL);
USIDR = b;
USI_TWI_Master_Transfer( true ); // Send 8 bits on bus.
/* Clock and verify (N)ACK from slave */
if(!ACK_received())
return false;
return true;
}
void twi::ReadByte(U8 *b, bool EndOfTransmission)
{
/* Read a data byte */
SDA.set_input();
*(b) = USI_TWI_Master_Transfer( true );
/* Prepare to generate ACK (or NACK in case of End Of Transmission) */
if(EndOfTransmission) // If transmission of last byte was performed.
{
SendNACK();
}
else
{
SendACK();
}
}
/*---------------------------------------------------------------
USI Transmit and receive function. LSB of first byte in data
indicates if a read or write cycles is performed. If set a read
operation is performed.
Function generates (Repeated) Start Condition, sends address and
R/W, Reads/Writes Data, and verifies/sends ACK.
Success or error code is returned. Error codes are defined in
USI_TWI_Master.h
---------------------------------------------------------------*/
unsigned char USI_TWI_Start_Transceiver_With_Data(unsigned char addr, unsigned char *msg, unsigned char msgSize)
{
unsigned char tempUSISR_8bit = (1<<USISIF)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| // Prepare register value to: Clear flags, and
(0x0<<USICNT0); // set USI to shift 8 bits i.e. count 16 clock edges.
unsigned char tempUSISR_1bit = (1<<USISIF)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| // Prepare register value to: Clear flags, and
(0xE<<USICNT0); // set USI to shift 1 bit i.e. count 2 clock edges.
USI_TWI_state.errorState = 0;
USI_TWI_state.addressMode = TRUE;
#ifdef PARAM_VERIFICATION
if(msg > (unsigned char*)RAMEND) // Test if address is outside SRAM space
{
USI_TWI_state.errorState = USI_TWI_DATA_OUT_OF_BOUND;
return (FALSE);
}
if(msgSize <= 1) // Test if the transmission buffer is empty
{
USI_TWI_state.errorState = USI_TWI_NO_DATA;
return (FALSE);
}
#endif
#ifdef NOISE_TESTING // Test if any unexpected conditions have arrived prior to this execution.
if( USISR & (1<<USISIF) )
{
USI_TWI_state.errorState = USI_TWI_UE_START_CON;
return (FALSE);
}
if( USISR & (1<<USIPF) )
{
USI_TWI_state.errorState = USI_TWI_UE_STOP_CON;
return (FALSE);
}
if( USISR & (1<<USIDC) )
{
USI_TWI_state.errorState = USI_TWI_UE_DATA_COL;
return (FALSE);
}
#endif
if ( !(addr & (1<<TWI_READ_BIT)) ) // The LSB in the address byte determines if is a masterRead or masterWrite operation.
{
USI_TWI_state.masterWriteDataMode = TRUE;
}
/* Release SCL to ensure that (repeated) Start can be performed */
PORT_USI |= (1<<PIN_USI_SCL); // Release SCL.
while( !(PIN_USI & (1<<PIN_USI_SCL)) ); // Verify that SCL becomes high.
#ifdef TWI_FAST_MODE
_delay_us( T4_TWI/4 ); // Delay for T4TWI if TWI_FAST_MODE
#else
_delay_us( T2_TWI/4 ); // Delay for T2TWI if TWI_STANDARD_MODE
#endif
/* Generate Start Condition */
PORT_USI &= ~(1<<PIN_USI_SDA); // Force SDA LOW.
_delay_us( T4_TWI/4 );
PORT_USI &= ~(1<<PIN_USI_SCL); // Pull SCL LOW.
PORT_USI |= (1<<PIN_USI_SDA); // Release SDA.
#ifdef SIGNAL_VERIFY
if( !(USISR & (1<<USISIF)) )
{
USI_TWI_state.errorState = USI_TWI_MISSING_START_CON;
return (FALSE);
}
#endif
/*Write address and Read/Write data */
do
{
/* If masterWrite cycle (or inital address tranmission)*/
if (USI_TWI_state.addressMode || USI_TWI_state.masterWriteDataMode)
{
/* Write a byte */
PORT_USI &= ~(1<<PIN_USI_SCL); // Pull SCL LOW.
if ( USI_TWI_state.addressMode ) {
USIDR = addr;
msgSize++; /* adjust for later decrement. */
} else {
USIDR = *(msg++); // Setup data.
}
USI_TWI_Master_Transfer( tempUSISR_8bit ); // Send 8 bits on bus.
/* Clock and verify (N)ACK from slave */
DDR_USI &= ~(1<<PIN_USI_SDA); // Enable SDA as input.
if( USI_TWI_Master_Transfer( tempUSISR_1bit ) & (1<<TWI_NACK_BIT) )
{
if ( USI_TWI_state.addressMode )
USI_TWI_state.errorState = USI_TWI_NO_ACK_ON_ADDRESS;
else
USI_TWI_state.errorState = USI_TWI_NO_ACK_ON_DATA;
return (FALSE);
}
USI_TWI_state.addressMode = FALSE; // Only perform address transmission once.
}
/* Else masterRead cycle*/
else
{
/* Read a data byte */
DDR_USI &= ~(1<<PIN_USI_SDA); // Enable SDA as input.
*(msg++) = USI_TWI_Master_Transfer( tempUSISR_8bit );
/* Prepare to generate ACK (or NACK in case of End Of Transmission) */
if( msgSize == 1) // If transmission of last byte was performed.
{
USIDR = 0xFF; // Load NACK to confirm End Of Transmission.
}
else
{
USIDR = 0x00; // Load ACK. Set data register bit 7 (output for SDA) low.
}
USI_TWI_Master_Transfer( tempUSISR_1bit ); // Generate ACK/NACK.
}
}while( --msgSize) ; // Until all data sent/received.
USI_TWI_Master_Stop(); // Send a STOP condition on the TWI bus.
/* Transmission successfully completed*/
return (TRUE);
}
/*---------------------------------------------------------------
USI Transmit and receive function. LSB of first byte in buffer
indicates if a read or write cycles is performed. If set a read
operation is performed.
Function generates (Repeated) Start Condition, sends address and
R/W, Reads/Writes Data, and verifies/sends ACK.
This function also handles Random Read function if the memReadMode
bit is set. In that case, the function will:
The address in memory will be the second
byte and is written *without* sending a STOP.
Then the Read bit is set (lsb of first byte), the byte count is
adjusted (if needed), and the function function starts over by sending
the slave address again and reading the data.
Success or error code is returned. Error codes are defined in
USI_TWI_Master.h
---------------------------------------------------------------*/
unsigned char USI_TWI_Start_Transceiver_With_Data( unsigned char *msg, unsigned char msgSize)
{
unsigned char const tempUSISR_8bit = (1<<USISIF)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| // Prepare register value to: Clear flags, and
(0x0<<USICNT0); // set USI to shift 8 bits i.e. count 16 clock edges.
unsigned char const tempUSISR_1bit = (1<<USISIF)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| // Prepare register value to: Clear flags, and
(0xE<<USICNT0); // set USI to shift 1 bit i.e. count 2 clock edges.
unsigned char *savedMsg;
unsigned char savedMsgSize;
//This clear must be done before calling this function so that memReadMode can be specified.
// USI_TWI_state.errorState = 0; // Clears all mode bits also
USI_TWI_state.addressMode = TRUE; // Always true for first byte
#ifdef PARAM_VERIFICATION
if(msg > (unsigned char*)RAMEND) // Test if address is outside SRAM space
{
USI_TWI_state.errorState = USI_TWI_DATA_OUT_OF_BOUND;
return (FALSE);
}
if(msgSize <= 1) // Test if the transmission buffer is empty
{
USI_TWI_state.errorState = USI_TWI_NO_DATA;
return (FALSE);
}
#endif
#ifdef NOISE_TESTING // Test if any unexpected conditions have arrived prior to this execution.
if( USISR & (1<<USISIF) )
{
USI_TWI_state.errorState = USI_TWI_UE_START_CON;
return (FALSE);
}
if( USISR & (1<<USIPF) )
{
USI_TWI_state.errorState = USI_TWI_UE_STOP_CON;
return (FALSE);
}
if( USISR & (1<<USIDC) )
{
USI_TWI_state.errorState = USI_TWI_UE_DATA_COL;
return (FALSE);
}
#endif
if ( !(*msg & (1<<TWI_READ_BIT)) ) // The LSB in the address byte determines if is a masterRead or masterWrite operation.
{
USI_TWI_state.masterWriteDataMode = TRUE;
}
// if (USI_TWI_state.memReadMode)
// {
savedMsg = msg;
savedMsgSize = msgSize;
// }
if ( !USI_TWI_Master_Start( ))
{
return (FALSE); // Send a START condition on the TWI bus.
}
/*Write address and Read/Write data */
do
{
/* If masterWrite cycle (or inital address tranmission)*/
if (USI_TWI_state.addressMode || USI_TWI_state.masterWriteDataMode)
{
/* Write a byte */
PORT_USI &= ~(1<<PIN_USI_SCL); // Pull SCL LOW.
USIDR = *(msg++); // Setup data.
USI_TWI_Master_Transfer( tempUSISR_8bit ); // Send 8 bits on bus.
/* Clock and verify (N)ACK from slave */
DDR_USI &= ~(1<<PIN_USI_SDA); // Enable SDA as input.
if( USI_TWI_Master_Transfer( tempUSISR_1bit ) & (1<<TWI_NACK_BIT) )
{
if ( USI_TWI_state.addressMode )
USI_TWI_state.errorState = USI_TWI_NO_ACK_ON_ADDRESS;
else
USI_TWI_state.errorState = USI_TWI_NO_ACK_ON_DATA;
return (FALSE);
}
if ((!USI_TWI_state.addressMode) && USI_TWI_state.memReadMode)// means memory start address has been written
{
msg = savedMsg; // start at slave address again
*(msg) |= (TRUE<<TWI_READ_BIT); // set the Read Bit on Slave address
USI_TWI_state.errorState = 0;
USI_TWI_state.addressMode = TRUE; // Now set up for the Read cycle
msgSize = savedMsgSize; // Set byte count correctly
// NOte that the length should be Slave adrs byte + # bytes to read + 1 (gets decremented below)
if ( !USI_TWI_Master_Start( ))
{
USI_TWI_state.errorState = USI_TWI_BAD_MEM_READ;
return (FALSE); // Send a START condition on the TWI bus.
}
}
else
{
USI_TWI_state.addressMode = FALSE; // Only perform address transmission once.
}
}
/* Else masterRead cycle*/
else
{
/* Read a data byte */
DDR_USI &= ~(1<<PIN_USI_SDA); // Enable SDA as input.
*(msg++) = USI_TWI_Master_Transfer( tempUSISR_8bit );
/* Prepare to generate ACK (or NACK in case of End Of Transmission) */
if( msgSize == 1) // If transmission of last byte was performed.
{
USIDR = 0xFF; // Load NACK to confirm End Of Transmission.
}
else
{
USIDR = 0x00; // Load ACK. Set data register bit 7 (output for SDA) low.
}
USI_TWI_Master_Transfer( tempUSISR_1bit ); // Generate ACK/NACK.
}
}while( --msgSize) ; // Until all data sent/received.
if (!USI_TWI_Master_Stop())
{
return (FALSE); // Send a STOP condition on the TWI bus.
}
/* Transmission successfully completed*/
return (TRUE);
}
/*---------------------------------------------------------------
USI Transmit and receive function. LSB of first byte in data
indicates if a read or write cycles is performed. If set a read
operation is performed.
Function generates (Repeated) Start Condition, sends address and
R/W, Reads/Writes Data, and verifies/sends ACK.
Success or error code is returned. Error codes are defined in
USI_TWI_Master.h
---------------------------------------------------------------*/
bool twi_master::USI_TWI_Start_Transceiver_With_Data( unsigned char *msg, unsigned char msgSize)
{
unsigned char tempUSISR_8bit = (1<<USISIF)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| // Prepare register value to: Clear flags, and
(0x0<<USICNT0); // set USI to shift 8 bits i.e. count 16 clock edges.
unsigned char tempUSISR_1bit = (1<<USISIF)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| // Prepare register value to: Clear flags, and
(0xE<<USICNT0); // set USI to shift 1 bit i.e. count 2 clock edges.
USI_TWI_state.errorState = 0;
USI_TWI_state.addressMode = TRUE;
if ( !(*msg & (1<<TWI_READ_BIT)) ) // The LSB in the address byte determines if is a masterRead or masterWrite operation.
{
USI_TWI_state.masterWriteDataMode = TRUE;
}
/* Release SCL to ensure that (repeated) Start can be performed */
PORT_USI |= (1<<PIN_USI_SCL); // Release SCL.
while( !(PIN_USI & (1<<PIN_USI_SCL)) ); // Verify that SCL becomes high.
_delay_us( T4_TWI/4 ); // Delay for T4TWI if TWI_FAST_MODE
/* Generate Start Condition */
PORT_USI &= ~(1<<PIN_USI_SDA); // Force SDA LOW.
_delay_us( T4_TWI/4 );
PORT_USI &= ~(1<<PIN_USI_SCL); // Pull SCL LOW.
PORT_USI |= (1<<PIN_USI_SDA); // Release SDA.
/*Write address and Read/Write data */
do
{
/* If masterWrite cycle (or inital address tranmission)*/
if (USI_TWI_state.addressMode || USI_TWI_state.masterWriteDataMode)
{
/* Write a byte */
PORT_USI &= ~(1<<PIN_USI_SCL); // Pull SCL LOW.
USIDR = *(msg++); // Setup data.
USI_TWI_Master_Transfer( tempUSISR_8bit ); // Send 8 bits on bus.
/* Clock and verify (N)ACK from slave */
DDR_USI &= ~(1<<PIN_USI_SDA); // Enable SDA as input.
if( USI_TWI_Master_Transfer( tempUSISR_1bit ) & (1<<TWI_NACK_BIT) )
{
if ( USI_TWI_state.addressMode )
USI_TWI_state.errorState = USI_TWI_NO_ACK_ON_ADDRESS;
else
USI_TWI_state.errorState = USI_TWI_NO_ACK_ON_DATA;
return false;
}
USI_TWI_state.addressMode = FALSE; // Only perform address transmission once.
}
/* Else masterRead cycle*/
else
{
/* Read a data byte */
DDR_USI &= ~(1<<PIN_USI_SDA); // Enable SDA as input.
*(msg++) = USI_TWI_Master_Transfer( tempUSISR_8bit );
/* Prepare to generate ACK (or NACK in case of End Of Transmission) */
if( msgSize == 1) // If transmission of last byte was performed.
{
USIDR = 0xFF; // Load NACK to confirm End Of Transmission.
}
else
{
USIDR = 0x00; // Load ACK. Set data register bit 7 (output for SDA) low.
}
USI_TWI_Master_Transfer( tempUSISR_1bit ); // Generate ACK/NACK.
}
}while( --msgSize) ; // Until all data sent/received.
USI_TWI_Master_Stop(); // Send a STOP condition on the TWI bus.
/* Transmission successfully completed*/
return true;
}
void twi::SendNACK()
{
USIDR = 0xFF;
USI_TWI_Master_Transfer( false ); // Generate ACK/NACK.
}
