void __init s5p_init_irq(u32 *vic, u32 num_vic)
{
struct irq_chip *chip;
int irq;
/* initialize the VICs */
for (irq = 0; irq < num_vic; irq++)
vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
#ifdef CONFIG_PM
/* Register wakeup source. */
for (irq = 0; irq < ARRAY_SIZE(wakeup_source); irq++) {
chip = get_irq_chip(wakeup_source[irq]);
chip->set_wake = s3c_irq_wake;
}
#endif
}
void __init s5p_init_irq(u32 *vic, u32 num_vic)
{
#ifdef CONFIG_ARM_VIC
int irq;
/* initialize the VICs */
for (irq = 0; irq < num_vic; irq++)
vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
#endif
s3c_init_vic_timer_irq(5, IRQ_TIMER0);
}
void __init s5p_init_irq(u32 *vic, u32 num_vic)
{
int irq;
/* initialize the VICs */
for (irq = 0; irq < num_vic; irq++)
vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
}
void __init s5p_init_irq(u32 *vic, u32 num_vic)
{
struct irq_chip *chip;
int irq;
#ifdef CONFIG_ARM_VIC
/* initialize the VICs */
for (irq = 0; irq < num_vic; irq++)
vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
#endif
s3c_init_vic_timer_irq(5, IRQ_TIMER0);
s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
/* Register wakeup source. */
for (irq = 0; irq < ARRAY_SIZE(wakeup_source); irq++) {
chip = irq_get_chip(wakeup_source[irq]);
chip->irq_set_wake = s3c_irq_wake;
}
}