static void decon_commit(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = crtc->ctx; struct drm_display_mode *mode = &crtc->base.mode; u32 val; if (ctx->suspended) return; /* enable clock gate */ val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F; writel(val, ctx->addr + DECON_CMU); /* lcd on and use command if */ val = VIDOUT_LCD_ON; if (ctx->i80_if) val |= VIDOUT_COMMAND_IF; else val |= VIDOUT_RGB_IF; writel(val, ctx->addr + DECON_VIDOUTCON0); val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | VIDTCON2_HOZVAL(mode->hdisplay - 1); writel(val, ctx->addr + DECON_VIDTCON2); if (!ctx->i80_if) { val = VIDTCON00_VBPD_F( mode->crtc_vtotal - mode->crtc_vsync_end) | VIDTCON00_VFPD_F( mode->crtc_vsync_start - mode->crtc_vdisplay); writel(val, ctx->addr + DECON_VIDTCON00); val = VIDTCON01_VSPW_F( mode->crtc_vsync_end - mode->crtc_vsync_start); writel(val, ctx->addr + DECON_VIDTCON01); val = VIDTCON10_HBPD_F( mode->crtc_htotal - mode->crtc_hsync_end) | VIDTCON10_HFPD_F( mode->crtc_hsync_start - mode->crtc_hdisplay); writel(val, ctx->addr + DECON_VIDTCON10); val = VIDTCON11_HSPW_F( mode->crtc_hsync_end - mode->crtc_hsync_start); writel(val, ctx->addr + DECON_VIDTCON11); } decon_setup_trigger(ctx); /* enable output and display signal */ val = VIDCON0_ENVID | VIDCON0_ENVID_F; writel(val, ctx->addr + DECON_VIDCON0); }
static void decon_commit(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = crtc->ctx; struct drm_display_mode *m = &crtc->base.mode; u32 val; if (test_bit(BIT_SUSPENDED, &ctx->flags)) return; if (ctx->out_type == IFTYPE_HDMI) { m->crtc_hsync_start = m->crtc_hdisplay + 10; m->crtc_hsync_end = m->crtc_htotal - 92; m->crtc_vsync_start = m->crtc_vdisplay + 1; m->crtc_vsync_end = m->crtc_vsync_start + 1; } decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID, 0); /* enable clock gate */ val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F; writel(val, ctx->addr + DECON_CMU); /* lcd on and use command if */ val = VIDOUT_LCD_ON; if (ctx->out_type == IFTYPE_I80) val |= VIDOUT_COMMAND_IF; else val |= VIDOUT_RGB_IF; writel(val, ctx->addr + DECON_VIDOUTCON0); val = VIDTCON2_LINEVAL(m->vdisplay - 1) | VIDTCON2_HOZVAL(m->hdisplay - 1); writel(val, ctx->addr + DECON_VIDTCON2); if (ctx->out_type != IFTYPE_I80) { val = VIDTCON00_VBPD_F( m->crtc_vtotal - m->crtc_vsync_end - 1) | VIDTCON00_VFPD_F( m->crtc_vsync_start - m->crtc_vdisplay - 1); writel(val, ctx->addr + DECON_VIDTCON00); val = VIDTCON01_VSPW_F( m->crtc_vsync_end - m->crtc_vsync_start - 1); writel(val, ctx->addr + DECON_VIDTCON01); val = VIDTCON10_HBPD_F( m->crtc_htotal - m->crtc_hsync_end - 1) | VIDTCON10_HFPD_F( m->crtc_hsync_start - m->crtc_hdisplay - 1); writel(val, ctx->addr + DECON_VIDTCON10); val = VIDTCON11_HSPW_F( m->crtc_hsync_end - m->crtc_hsync_start - 1); writel(val, ctx->addr + DECON_VIDTCON11); } decon_setup_trigger(ctx); /* enable output and display signal */ decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0); }