prom[i] = s->conf.macaddr.a[i]; checksum += prom[i]; if (checksum > 0xff) { checksum = (checksum + 1) & 0xff; } } prom[7] = 0xff - checksum; } static const VMStateDescription vmstate_dp8393x = { .name = "dp8393x", .version_id = 0, .minimum_version_id = 0, .fields = (VMStateField []) { VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6), VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40), VMSTATE_END_OF_LIST() } }; static Property dp8393x_properties[] = { DEFINE_NIC_PROPERTIES(dp8393xState, conf), DEFINE_PROP_PTR("dma_mr", dp8393xState, dma_mr), DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0), DEFINE_PROP_END_OF_LIST(), }; static void dp8393x_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass);
VMSTATE_UINT32(intmask, PXA2xxMMCIState), VMSTATE_UINT32(intreq, PXA2xxMMCIState), VMSTATE_INT32(cmd, PXA2xxMMCIState), VMSTATE_UINT32(arg, PXA2xxMMCIState), VMSTATE_INT32(cmdreq, PXA2xxMMCIState), VMSTATE_INT32(active, PXA2xxMMCIState), VMSTATE_INT32(bytesleft, PXA2xxMMCIState), VMSTATE_UINT32(tx_start, PXA2xxMMCIState), VMSTATE_UINT32(tx_len, PXA2xxMMCIState), VMSTATE_UINT32(rx_start, PXA2xxMMCIState), VMSTATE_UINT32(rx_len, PXA2xxMMCIState), VMSTATE_UINT32(resp_len, PXA2xxMMCIState), VMSTATE_VALIDATE("fifo size incorrect", pxa2xx_mmci_vmstate_validate), VMSTATE_UINT8_ARRAY(tx_fifo, PXA2xxMMCIState, 64), VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxMMCIState, 32), VMSTATE_UINT16_ARRAY(resp_fifo, PXA2xxMMCIState, 9), VMSTATE_END_OF_LIST() } }; #define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */ #define MMC_STAT 0x04 /* MMC Status register */ #define MMC_CLKRT 0x08 /* MMC Clock Rate register */ #define MMC_SPI 0x0c /* MMC SPI Mode register */ #define MMC_CMDAT 0x10 /* MMC Command/Data register */ #define MMC_RESTO 0x14 /* MMC Response Time-Out register */ #define MMC_RDTO 0x18 /* MMC Read Time-Out register */ #define MMC_BLKLEN 0x1c /* MMC Block Length register */ #define MMC_NUMBLK 0x20 /* MMC Number of Blocks register */ #define MMC_PRTBUF 0x24 /* MMC Buffer Partly Full register */ #define MMC_I_MASK 0x28 /* MMC Interrupt Mask register */
SysBusDevice *sbd = SYS_BUS_DEVICE(obj); ZynqXADCState *s = ZYNQ_XADC(obj); memory_region_init_io(&s->iomem, obj, &xadc_ops, s, "zynq-xadc", ZYNQ_XADC_MMIO_SIZE); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->qemu_irq); } static const VMStateDescription vmstate_zynq_xadc = { .name = "zynq-xadc", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, ZynqXADCState, ZYNQ_XADC_NUM_IO_REGS), VMSTATE_UINT16_ARRAY(xadc_regs, ZynqXADCState, ZYNQ_XADC_NUM_ADC_REGS), VMSTATE_UINT16_ARRAY(xadc_dfifo, ZynqXADCState, ZYNQ_XADC_FIFO_DEPTH), VMSTATE_UINT16(xadc_read_reg_previous, ZynqXADCState), VMSTATE_UINT16(xadc_dfifo_entries, ZynqXADCState), VMSTATE_END_OF_LIST() } }; static void zynq_xadc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->vmsd = &vmstate_zynq_xadc; dc->reset = zynq_xadc_reset; }
static const VMStateDescription vmstate_gic = { .name = "arm_gic", .version_id = 12, .minimum_version_id = 12, .pre_save = gic_pre_save, .post_load = gic_post_load, .fields = (VMStateField[]) { VMSTATE_UINT32(ctlr, GICState), VMSTATE_UINT32_ARRAY(cpu_ctlr, GICState, GIC_NCPU), VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1, vmstate_gic_irq_state, gic_irq_state), VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ), VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU), VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL), VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU), VMSTATE_UINT16_ARRAY(priority_mask, GICState, GIC_NCPU), VMSTATE_UINT16_ARRAY(running_priority, GICState, GIC_NCPU), VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU), VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU), VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU), VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU), VMSTATE_UINT32_2DARRAY(nsapr, GICState, GIC_NR_APRS, GIC_NCPU), VMSTATE_END_OF_LIST() } }; void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler, const MemoryRegionOps *ops) { SysBusDevice *sbd = SYS_BUS_DEVICE(s); int i = s->num_irq - GIC_INTERNAL;
s->lp[0] ^= ~s->count; s->lp[1] ^= s->count; } s->count ++; return sample; } /* Reinitialise the counters. */ void ecc_reset(ECCState *s) { s->lp[0] = 0x0000; s->lp[1] = 0x0000; s->cp = 0x00; s->count = 0; } /* Save/restore */ VMStateDescription vmstate_ecc_state = { .name = "ecc-state", .version_id = 0, .minimum_version_id = 0, .minimum_version_id_old = 0, .fields = (VMStateField []) { VMSTATE_UINT8(cp, ECCState), VMSTATE_UINT16_ARRAY(lp, ECCState, 2), VMSTATE_UINT16(count, ECCState), VMSTATE_END_OF_LIST(), }, };