/*
* Description:
* Software Reset MAC
*
* Parameters:
* In:
* dwIoBase - Base Address for MAC
* Out:
* none
*
* Return Value: true if Reset Success; otherwise false
*
*/
bool MACbSoftwareReset(void __iomem *dwIoBase)
{
unsigned char byData;
unsigned short ww;
// turn on HOSTCR_SOFTRST, just write 0x01 to reset
VNSvOutPortB(dwIoBase + MAC_REG_HOSTCR, 0x01);
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
VNSvInPortB(dwIoBase + MAC_REG_HOSTCR, &byData);
if (!(byData & HOSTCR_SOFTRST))
break;
}
if (ww == W_MAX_TIMEOUT)
return false;
return true;
}
/*
* Description:
* Turn Off MAC Tx
*
* Parameters:
* In:
* dwIoBase - Base Address for MAC
* Out:
* none
*
* Return Value: true if success; otherwise false
*
*/
bool MACbSafeTxOff(void __iomem *dwIoBase)
{
unsigned short ww;
unsigned long dwData;
unsigned char byData;
/* Clear TX DMA */
/* Tx0 */
VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_CLRRUN);
/* AC0 */
VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_CLRRUN);
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData);
if (!(dwData & DMACTL_RUN))
break;
}
if (ww == W_MAX_TIMEOUT) {
pr_debug(" DBG_PORT80(0x20)\n");
return false;
}
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData);
if (!(dwData & DMACTL_RUN))
break;
}
if (ww == W_MAX_TIMEOUT) {
pr_debug(" DBG_PORT80(0x21)\n");
return false;
}
/* try to safe shutdown TX */
MACvRegBitsOff(dwIoBase, MAC_REG_HOSTCR, HOSTCR_TXON);
/* W_MAX_TIMEOUT is the timeout period */
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
VNSvInPortB(dwIoBase + MAC_REG_HOSTCR, &byData);
if (!(byData & HOSTCR_TXONST))
break;
}
if (ww == W_MAX_TIMEOUT) {
pr_debug(" DBG_PORT80(0x24)\n");
return false;
}
return true;
}
VOID GMACvGetVCAMMask(DWORD dwIoBase, PBYTE pbyMask)
{
BYTE byOrgCAMCR, byData;
/* modify CAMCR to select CAM MASK regs */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byOrgCAMCR);
byData = (BYTE)((byOrgCAMCR & ~CAMCR_PS1) | CAMCR_PS0);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byData);
/* select VCAM Mask */
VNSvOutPortB(dwIoBase + MAC_REG_CAMADDR, CAMADDR_VCAMSL);
VNSvInPortD(dwIoBase + MAC_REG_CAM, (PDWORD)pbyMask);
VNSvInPortD(dwIoBase + MAC_REG_CAM + 4, (PDWORD)(pbyMask + 4));
/* restore to original CAMCR */
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byOrgCAMCR);
}
/*
* Description:
* Turn Off MAC Rx
*
* Parameters:
* In:
* dwIoBase - Base Address for MAC
* Out:
* none
*
* Return Value: true if success; otherwise false
*
*/
bool MACbSafeRxOff(void __iomem *dwIoBase)
{
unsigned short ww;
unsigned long dwData;
unsigned char byData;
/* turn off wow temp for turn off Rx safely */
/* Clear RX DMA0,1 */
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_CLRRUN);
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_CLRRUN);
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData);
if (!(dwData & DMACTL_RUN))
break;
}
if (ww == W_MAX_TIMEOUT) {
pr_debug(" DBG_PORT80(0x10)\n");
return false;
}
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData);
if (!(dwData & DMACTL_RUN))
break;
}
if (ww == W_MAX_TIMEOUT) {
pr_debug(" DBG_PORT80(0x11)\n");
return false;
}
/* try to safe shutdown RX */
MACvRegBitsOff(dwIoBase, MAC_REG_HOSTCR, HOSTCR_RXON);
/* W_MAX_TIMEOUT is the timeout period */
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
VNSvInPortB(dwIoBase + MAC_REG_HOSTCR, &byData);
if (!(byData & HOSTCR_RXONST))
break;
}
if (ww == W_MAX_TIMEOUT) {
pr_debug(" DBG_PORT80(0x12)\n");
return false;
}
return true;
}
VOID GMACvSetTqIndex(DWORD dwIoBase, BYTE byTxQue, WORD wTdIdx)
{
BYTE byData;
/* Clear RUN */
VNSvOutPortB(dwIoBase + MAC_REG_TDCSR_CLR + (byTxQue / 2), (BYTE)(TRDCSR_RUN << ((byTxQue % 2)*4)));
/* Wait for RUN clear */
while (TRUE) {
VNSvInPortB(dwIoBase + MAC_REG_TDCSR_SET + (byTxQue / 2), &byData);
if (BITbIsBitOff(byData, TRDCSR_RUN << ((byTxQue % 2)*4)))
break;
}
/* Set TdIdx */
VNSvOutPortW(dwIoBase + MAC_REG_TDINDX + byTxQue*2, wTdIdx);
/* Set RUN */
VNSvOutPortB(dwIoBase + MAC_REG_TDCSR_SET + (byTxQue / 2), (BYTE)(TRDCSR_RUN << ((byTxQue % 2)*4)));
}
/*
* Description:
* Micro Second Delay via MAC
*
* Parameters:
* In:
* dwIoBase - Base Address for MAC
* uDelay - Delay time (timer resolution is 4 us)
* Out:
* none
*
* Return Value: none
*
*/
void MACvTimer0MicroSDelay(void __iomem *dwIoBase, unsigned int uDelay)
{
unsigned char byValue;
unsigned int uu, ii;
VNSvOutPortB(dwIoBase + MAC_REG_TMCTL0, 0);
VNSvOutPortD(dwIoBase + MAC_REG_TMDATA0, uDelay);
VNSvOutPortB(dwIoBase + MAC_REG_TMCTL0, (TMCTL_TMD | TMCTL_TE));
for (ii = 0; ii < 66; ii++) { // assume max PCI clock is 66Mhz
for (uu = 0; uu < uDelay; uu++) {
VNSvInPortB(dwIoBase + MAC_REG_TMCTL0, &byValue);
if ((byValue == 0) ||
(byValue & TMCTL_TSUSP)) {
VNSvOutPortB(dwIoBase + MAC_REG_TMCTL0, 0);
return;
}
}
}
VNSvOutPortB(dwIoBase + MAC_REG_TMCTL0, 0);
}
VOID GMACvGetMCAMMask(DWORD dwIoBase, PBYTE pbyMask)
{
BYTE byOrgCAMCR, byData;
/* modify CAMCR to select CAM MASK regs */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byOrgCAMCR);
byData = (BYTE)((byOrgCAMCR & ~CAMCR_PS1) | CAMCR_PS0);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byData);
/* Select MCAM Mask */
VNSvOutPortB(dwIoBase + MAC_REG_CAMADDR, 0);
/* select CAM and read CAM mask data (don't need to set CAMEN) */
VNSvOutPortB(dwIoBase + MAC_REG_CAMADDR, 0);
VNSvInPortD(dwIoBase + MAC_REG_CAM, (PDWORD)pbyMask);
VNSvInPortD(dwIoBase + MAC_REG_CAM + 4, (PDWORD)(pbyMask + 4));
/* restore to original CAMCR */
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byOrgCAMCR);
}
VOID GMACvSetMCAMMask(DWORD dwIoBase, PBYTE pbyMask)
{
BYTE byOrgCAMCR, byData;
/* DWORD dwData; */
/* modify CAMCR to select CAM MASK regs */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byOrgCAMCR);
byData = (BYTE)((byOrgCAMCR & ~CAMCR_PS1) | CAMCR_PS0);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byData);
/* Select MCAM Mask */
VNSvOutPortB(dwIoBase + MAC_REG_CAMADDR, 0);
VNSvOutPortD(dwIoBase + MAC_REG_CAM, *(PDWORD)pbyMask);
/* VNSvInPortD(dwIoBase + MAC_REG_CAM, &dwData); */
VNSvOutPortD(dwIoBase + MAC_REG_CAM + 4, *((PDWORD)(pbyMask + 4)));
/* VNSvInPortD(dwIoBase + MAC_REG_CAM + 4, &dwData); */
/* restore to original CAMCR */
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byOrgCAMCR);
}
VOID GMACvSetMCAMMaskByBR(DWORD dwIoBase, PBYTE pbyMask)
{
BYTE byOrgCAMCR, byData;
/* modify CAMCR to select CAM MASK regs */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byOrgCAMCR);
byData = (BYTE)((byOrgCAMCR & ~CAMCR_PS1) | CAMCR_PS0);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byData);
/* Select MCAM Mask */
VNSvOutPortB(dwIoBase + MAC_REG_CAMADDR, 0);
UINT uu;
for (uu = 0; uu < 8; uu++) {
VNSvOutPortB(dwIoBase + MAC_REG_CAM + uu, *(pbyMask + uu));
/* PATCH...Read back for delay */
/* VNSvInPortB(dwIoBase + MAC_REG_CAM + uu, &byData); */
}
/* restore to original CAMCR */
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byOrgCAMCR);
}
bool MACbPSWakeup(void __iomem *dwIoBase)
{
unsigned char byOrgValue;
unsigned int ww;
/* Read PSCTL */
if (MACbIsRegBitsOff(dwIoBase, MAC_REG_PSCTL, PSCTL_PS))
return true;
/* Disable PS */
MACvRegBitsOff(dwIoBase, MAC_REG_PSCTL, PSCTL_PSEN);
/* Check if SyncFlushOK */
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
VNSvInPortB(dwIoBase + MAC_REG_PSCTL, &byOrgValue);
if (byOrgValue & PSCTL_WAKEDONE)
break;
}
if (ww == W_MAX_TIMEOUT) {
pr_debug(" DBG_PORT80(0x33)\n");
return false;
}
return true;
}
static void s_vInit(
PSAdapterInfo pAdapter,
UINT uTotalNum,
UINT uIdx
)
{
int ii;
unsigned char check;
pAdapter->cbTotalAdapterNum = uTotalNum;
pAdapter->uAdapterIndex = uIdx;
/* Save Memory Mapped IO base address */
switch (uIdx) {
case 0:
pAdapter->dwIoBase = BA_MAC0;
break;
case 1:
pAdapter->dwIoBase = BA_MAC1;
break;
default:
break;
}
MacDump(MACDBG_INFO, ("Memory mapped IO base address:%08X\n", pAdapter->dwIoBase));
/* check vee oe pee */
VNSvInPortB(pAdapter->dwIoBase+0x77, &check);
if (check & 0x40){
/* Issue AUTOLD in EECSR to reload eeprom to ensure right data from eeprom */
MACvRegBitsOn(pAdapter->dwIoBase, MAC_REG_EECSR, EECSR_AUTOLD);
/* set VEELD */
VNSvOutPortB(pAdapter->dwIoBase+PCI_Configuration_Space_Offset+VMSTS, 0x1);
/* wait until VEELD is set */
ii = 0;
while (1) {
VNSvInPortB(pAdapter->dwIoBase+PCI_Configuration_Space_Offset+VMSTS, &check);
if (check&0x2 || ii == MaxTimeOut)
break;
ii++;
}
/* clear VEELD */
VNSvOutPortB(pAdapter->dwIoBase+PCI_Configuration_Space_Offset+VMSTS, 0x0);
} else {
/* Issue AUTOLD in EECSR to reload eeprom to ensure right data from eeprom */
MACvRegBitsOn(pAdapter->dwIoBase, MAC_REG_EECSR, EECSR_AUTOLD);
/* Wait until EEPROM loading complete */
while (TRUE) {
BYTE byData;
VNSvInPortB(pAdapter->dwIoBase + MAC_REG_EECSR, &byData);
if (BITbIsBitOff(byData, EECSR_AUTOLD))
break;
}
}
/* Get Device ID from PCI configuration space */
VPCIvReadW(pAdapter->dwIoBase, PCI_REG_DEVICE_ID, &pAdapter->wDevId);
MacDump(MACDBG_INFO, ("Device ID:%04X\n", pAdapter->wDevId));
if (pAdapter->wDevId != W_DEVICE_ID_3106A && pAdapter->wDevId != W_DEVICE_ID_3053A)
return;
/* Get Revision ID from PCI configuration */
VPCIvReadB(pAdapter->dwIoBase, PCI_REG_REV_ID, &pAdapter->byRevId);
MacDump(MACDBG_INFO, ("Revision ID:%02X\n", pAdapter->byRevId));
/* Clear sticky bits */
if (g_sOptions.ulInitCmds & INIT_CMD_CLEAR_STICKHW)
MACvClearStckDS(pAdapter->dwIoBase);
if (g_sOptions.byRevId != 0)
pAdapter->byRevId = g_sOptions.byRevId;
/* Set RD,TD number for this adapter now */
/* For 3065, 3106J, 3206 */
pAdapter->cbRD = (g_sOptions.iRDescNum) ? g_sOptions.iRDescNum : CB_INIT_RD_NUM;
pAdapter->cbTD = (g_sOptions.iTDescNum) ? g_sOptions.iTDescNum : CB_INIT_TD_NUM;
/* Save IRQ number */
switch (uIdx) {
case 0:
pAdapter->byIrqLevel = IRQ_ETH0;
/* pAdapter->pvAdapterIsr = ISRvIsrForMAC0; */
break;
case 1:
pAdapter->byIrqLevel = IRQ_ETH1;
/* pAdapter->pvAdapterIsr = ISRvIsrForMAC1; */
break;
default:
break;
}
g_sOptions.uiBuffsize = (g_sOptions.uiBuffsize) ? g_sOptions.uiBuffsize : CB_MAX_BUF_SIZE;
/* Get the offset of PM Capability and save it from pci configuration space */
VPCIvReadB(pAdapter->dwIoBase, PCI_REG_CAP, &pAdapter->byPMRegOffset);
/* Get PHY address */
pAdapter->byPhyId = MACbyGetPhyId(pAdapter->dwIoBase);
MacDump(MACDBG_INFO, ("PHY Address:%02X\n", pAdapter->byPhyId));
/* Get Ethernet address */
for (ii = 0; ii < U_ETHER_ADDR_LEN; ii++)
VNSvInPortB(pAdapter->dwIoBase + MAC_REG_PAR, pAdapter->abyEtherAddr + ii);
/* Allocate RD/TD poiter array & DescBuf array data structure */
if (!g_bInit) {
if (!ADPbDynaAllocBuf(pAdapter)) {
printf("ADPbDynaAllocBuf() can't allocate buffer.\n");
return;
}
}
pAdapter->dwCacheLineSize = sizeof(DWORD) * 4;
/* Set default value of connection type to MEDIA_AUTO */
pAdapter->uConnectionType = MEDIA_AUTO;
/* Init default descriptor number per packet in monitor mode */
pAdapter->uTxDescNumPerPacket = 1;
/* Background timer send as default */
pAdapter->bTxContFunTest = TRUE;
}
BOOL GMACbIsRegBitsOff(DWORD dwIoBase, BYTE byRegOfs, BYTE byTestBits)
{
BYTE byData;
VNSvInPortB(dwIoBase + byRegOfs, &byData);
return BITbIsAllBitsOff(byData, byTestBits);
}
VOID GMACvInitialize(PSAdapterInfo pAdapter, DWORD dwIoBase, BYTE byRevId)
{
BYTE byTemp;
BYTE check;
/* clear sticky bits */
MACvClearStckDS(dwIoBase);
/* disable force PME-enable */
VNSvOutPortB(dwIoBase + MAC_REG_WOLCFG_CLR, WOLCFG_PMEOVR);
/* disable power-event config bit */
MACvPwrEvntDisable(dwIoBase);
/* clear power status */
VNSvOutPortW(dwIoBase + MAC_REG_WOLSR0_CLR, 0xFFFF);
/* do reset */
GMACbSoftwareReset(dwIoBase, byRevId);
/* for AUTOLD be effect, safe delay time */
PCAvDelayByIO(CB_DELAY_SOFT_RESET);
VNSvInPortB(dwIoBase + MAC_REG_JMPSR1, &check);
/* VNSvInPortB(pAdapter->dwIoBase+Gmac_Jumper_Strapping3, &check) */
/* if (!(check & JMPSR1_J_VEESEL))
GMACLoadVEE(dwIoBase);
else { */
if (check & JMPSR1_J_VEESEL) {
/* issue RELOAD in EECSR to reload eeprom */
MACvRegBitsOn(dwIoBase, MAC_REG_EECSR, EECSR_RELOAD);
/* wait until EEPROM loading complete */
while (TRUE) {
if (GMACbIsRegBitsOff(dwIoBase, MAC_REG_EECSR, EECSR_RELOAD))
break;
}
}
/* EEPROM reloaded will cause bit 0 in MAC_REG_CFGA turned on. */
/* it makes MAC receive magic packet automatically. So, driver turn it off. */
MACvRegBitsOff(dwIoBase, MAC_REG_CFGA, CFGA_PACPI);
/* set rx-FIFO/DMA threshold */
/* set rx threshold, 128 bytes */
/*GMACvSetRxThreshold(dwIoBase, 3);*/
/* set DMA length, 16 DWORDs = 64 bytes */
/*GMACvSetDmaLength(dwIoBase, 1);*/
/* suspend-well accept broadcast, multicast */
VNSvOutPortB(dwIoBase + MAC_REG_WOLCFG_SET, WOLCFG_SAM | WOLCFG_SAB);
/* back off algorithm use original IEEE standard */
MACvRegBitsOff(dwIoBase, MAC_REG_CFGB, CFGB_CRANDOM | CFGB_CAP | CFGB_MBA | CFGB_BAKOPT);
/* set packet filter */
/* receive directed and broadcast address */
GMACvSetPacketFilter(dwIoBase, PKT_TYPE_DIRECTED | PKT_TYPE_BROADCAST);
/* Eric */
#if defined(__USE_GMASK1__)
VNSvOutPortD(dwIoBase + MAC_REG_IMR, IMR_MASK_VALUE);
#else
/* Turn on GenIntMask1 */
VNSvOutPortB(dwIoBase + MAC_REG_CR3_SET, CR3_GINTMSK1);
#endif
#if 0
VNSvInPortB(dwIoBase, &byTemp);
printf("address0 = %x\n ", byTemp);
VNSvInPortB(dwIoBase + 1, &byTemp);
printf("address1 = %x\n ", byTemp);
VNSvInPortB(dwIoBase + 2, &byTemp);
printf("address2 = %x\n ", byTemp);
VNSvInPortB(dwIoBase + 3, &byTemp);
printf("address3 = %x\n ", byTemp);
VNSvInPortB(dwIoBase + 4, &byTemp);
printf("address4 = %x\n ", byTemp);
VNSvInPortB(dwIoBase + 5, &byTemp);
printf("address6 = %x\n ", byTemp);
#endif
/* Adaptive Interrupt: Init is disabled */
/* Select page to interrupt hold timer */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byTemp);
byTemp &= ~(CAMCR_PS0 | CAMCR_PS1);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byTemp);
/* Set Interrupt hold timer = 0 */
VNSvOutPortB(dwIoBase + MAC_REG_ISR_HOTMR, 0x00);
/* Select Page to Tx-sup threshold */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byTemp);
byTemp = (BYTE)((byTemp | CAMCR_PS0) & ~CAMCR_PS1);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byTemp);
/* Set Tx interrupt suppression threshold = 0 */
VNSvOutPortB(dwIoBase + MAC_REG_ISR_TSUPTHR, 0x00);
/* Select Page to Rx-sup threshold */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byTemp);
byTemp = (BYTE)((byTemp | CAMCR_PS1) & ~CAMCR_PS0);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byTemp);
/* Set Rx interrupt suppression threshold = 0 */
VNSvOutPortB(dwIoBase + MAC_REG_ISR_RSUPTHR, 0x00);
/* Select page to interrupt hold timer */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byTemp);
byTemp &= ~(CAMCR_PS0 | CAMCR_PS1);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byTemp);
/* enable MIICR_MAUTO */
GMACvEnableMiiAutoPoll(dwIoBase);
}
VOID GMACvGetDmaLength(DWORD dwIoBase, PBYTE pbyDmaLength)
{
/* get DCFG0 */
VNSvInPortB(dwIoBase + MAC_REG_DCFG0, pbyDmaLength);
*pbyDmaLength &= 0x07;
}
static irqreturn_t device_intr(int irq, void *dev_instance)
{
struct vnt_private *pDevice = dev_instance;
int max_count = 0;
unsigned long dwMIBCounter = 0;
unsigned char byOrgPageSel = 0;
int handled = 0;
unsigned long flags;
MACvReadISR(pDevice->PortOffset, &pDevice->dwIsr);
if (pDevice->dwIsr == 0)
return IRQ_RETVAL(handled);
if (pDevice->dwIsr == 0xffffffff) {
pr_debug("dwIsr = 0xffff\n");
return IRQ_RETVAL(handled);
}
handled = 1;
MACvIntDisable(pDevice->PortOffset);
spin_lock_irqsave(&pDevice->lock, flags);
//Make sure current page is 0
VNSvInPortB(pDevice->PortOffset + MAC_REG_PAGE1SEL, &byOrgPageSel);
if (byOrgPageSel == 1)
MACvSelectPage0(pDevice->PortOffset);
else
byOrgPageSel = 0;
MACvReadMIBCounter(pDevice->PortOffset, &dwMIBCounter);
// TBD....
// Must do this after doing rx/tx, cause ISR bit is slow
// than RD/TD write back
// update ISR counter
STAvUpdate802_11Counter(&pDevice->s802_11Counter, &pDevice->scStatistic, dwMIBCounter);
while (pDevice->dwIsr != 0) {
STAvUpdateIsrStatCounter(&pDevice->scStatistic, pDevice->dwIsr);
MACvWriteISR(pDevice->PortOffset, pDevice->dwIsr);
if (pDevice->dwIsr & ISR_FETALERR) {
pr_debug(" ISR_FETALERR\n");
VNSvOutPortB(pDevice->PortOffset + MAC_REG_SOFTPWRCTL, 0);
VNSvOutPortW(pDevice->PortOffset + MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPECTI);
device_error(pDevice, pDevice->dwIsr);
}
if (pDevice->dwIsr & ISR_TBTT) {
if (pDevice->vif &&
pDevice->op_mode != NL80211_IFTYPE_ADHOC)
vnt_check_bb_vga(pDevice);
pDevice->bBeaconSent = false;
if (pDevice->bEnablePSMode)
PSbIsNextTBTTWakeUp((void *)pDevice);
if ((pDevice->op_mode == NL80211_IFTYPE_AP ||
pDevice->op_mode == NL80211_IFTYPE_ADHOC) &&
pDevice->vif->bss_conf.enable_beacon) {
MACvOneShotTimer1MicroSec(pDevice->PortOffset,
(pDevice->vif->bss_conf.beacon_int - MAKE_BEACON_RESERVED) << 10);
}
/* TODO: adhoc PS mode */
}
if (pDevice->dwIsr & ISR_BNTX) {
if (pDevice->op_mode == NL80211_IFTYPE_ADHOC) {
pDevice->bIsBeaconBufReadySet = false;
pDevice->cbBeaconBufReadySetCnt = 0;
}
pDevice->bBeaconSent = true;
}
if (pDevice->dwIsr & ISR_RXDMA0)
max_count += device_rx_srv(pDevice, TYPE_RXDMA0);
if (pDevice->dwIsr & ISR_RXDMA1)
max_count += device_rx_srv(pDevice, TYPE_RXDMA1);
if (pDevice->dwIsr & ISR_TXDMA0)
max_count += device_tx_srv(pDevice, TYPE_TXDMA0);
if (pDevice->dwIsr & ISR_AC0DMA)
max_count += device_tx_srv(pDevice, TYPE_AC0DMA);
if (pDevice->dwIsr & ISR_SOFTTIMER1) {
if (pDevice->vif) {
if (pDevice->vif->bss_conf.enable_beacon)
vnt_beacon_make(pDevice, pDevice->vif);
}
}
/* If both buffers available wake the queue */
if (pDevice->vif) {
if (AVAIL_TD(pDevice, TYPE_TXDMA0) &&
AVAIL_TD(pDevice, TYPE_AC0DMA) &&
ieee80211_queue_stopped(pDevice->hw, 0))
ieee80211_wake_queues(pDevice->hw);
}
MACvReadISR(pDevice->PortOffset, &pDevice->dwIsr);
MACvReceive0(pDevice->PortOffset);
MACvReceive1(pDevice->PortOffset);
if (max_count > pDevice->sOpts.int_works)
break;
}
if (byOrgPageSel == 1)
MACvSelectPage1(pDevice->PortOffset);
spin_unlock_irqrestore(&pDevice->lock, flags);
MACvIntEnable(pDevice->PortOffset, IMR_MASK_VALUE);
return IRQ_RETVAL(handled);
}
static void device_init_registers(struct vnt_private *pDevice)
{
unsigned long flags;
unsigned int ii;
unsigned char byValue;
unsigned char byCCKPwrdBm = 0;
unsigned char byOFDMPwrdBm = 0;
MACbShutdown(pDevice->PortOffset);
BBvSoftwareReset(pDevice);
/* Do MACbSoftwareReset in MACvInitialize */
MACbSoftwareReset(pDevice->PortOffset);
pDevice->bAES = false;
/* Only used in 11g type, sync with ERP IE */
pDevice->bProtectMode = false;
pDevice->bNonERPPresent = false;
pDevice->bBarkerPreambleMd = false;
pDevice->wCurrentRate = RATE_1M;
pDevice->byTopOFDMBasicRate = RATE_24M;
pDevice->byTopCCKBasicRate = RATE_1M;
/* Target to IF pin while programming to RF chip. */
pDevice->byRevId = 0;
/* init MAC */
MACvInitialize(pDevice->PortOffset);
/* Get Local ID */
VNSvInPortB(pDevice->PortOffset + MAC_REG_LOCALID, &pDevice->byLocalID);
spin_lock_irqsave(&pDevice->lock, flags);
SROMvReadAllContents(pDevice->PortOffset, pDevice->abyEEPROM);
spin_unlock_irqrestore(&pDevice->lock, flags);
/* Get Channel range */
pDevice->byMinChannel = 1;
pDevice->byMaxChannel = CB_MAX_CHANNEL;
/* Get Antena */
byValue = SROMbyReadEmbedded(pDevice->PortOffset, EEP_OFS_ANTENNA);
if (byValue & EEP_ANTINV)
pDevice->bTxRxAntInv = true;
else
pDevice->bTxRxAntInv = false;
byValue &= (EEP_ANTENNA_AUX | EEP_ANTENNA_MAIN);
/* if not set default is All */
if (byValue == 0)
byValue = (EEP_ANTENNA_AUX | EEP_ANTENNA_MAIN);
if (byValue == (EEP_ANTENNA_AUX | EEP_ANTENNA_MAIN)) {
pDevice->byAntennaCount = 2;
pDevice->byTxAntennaMode = ANT_B;
pDevice->dwTxAntennaSel = 1;
pDevice->dwRxAntennaSel = 1;
if (pDevice->bTxRxAntInv)
pDevice->byRxAntennaMode = ANT_A;
else
pDevice->byRxAntennaMode = ANT_B;
} else {
pDevice->byAntennaCount = 1;
pDevice->dwTxAntennaSel = 0;
pDevice->dwRxAntennaSel = 0;
if (byValue & EEP_ANTENNA_AUX) {
pDevice->byTxAntennaMode = ANT_A;
if (pDevice->bTxRxAntInv)
pDevice->byRxAntennaMode = ANT_B;
else
pDevice->byRxAntennaMode = ANT_A;
} else {
pDevice->byTxAntennaMode = ANT_B;
if (pDevice->bTxRxAntInv)
pDevice->byRxAntennaMode = ANT_A;
else
pDevice->byRxAntennaMode = ANT_B;
}
}
/* Set initial antenna mode */
BBvSetTxAntennaMode(pDevice, pDevice->byTxAntennaMode);
BBvSetRxAntennaMode(pDevice, pDevice->byRxAntennaMode);
/* zonetype initial */
pDevice->byOriginalZonetype = pDevice->abyEEPROM[EEP_OFS_ZONETYPE];
/* Get RFType */
pDevice->byRFType = SROMbyReadEmbedded(pDevice->PortOffset, EEP_OFS_RFTYPE);
/* force change RevID for VT3253 emu */
if ((pDevice->byRFType & RF_EMU) != 0)
pDevice->byRevId = 0x80;
pDevice->byRFType &= RF_MASK;
pr_debug("pDevice->byRFType = %x\n", pDevice->byRFType);
if (!pDevice->bZoneRegExist)
pDevice->byZoneType = pDevice->abyEEPROM[EEP_OFS_ZONETYPE];
pr_debug("pDevice->byZoneType = %x\n", pDevice->byZoneType);
/* Init RF module */
RFbInit(pDevice);
/* Get Desire Power Value */
pDevice->byCurPwr = 0xFF;
pDevice->byCCKPwr = SROMbyReadEmbedded(pDevice->PortOffset, EEP_OFS_PWR_CCK);
pDevice->byOFDMPwrG = SROMbyReadEmbedded(pDevice->PortOffset, EEP_OFS_PWR_OFDMG);
/* Load power Table */
for (ii = 0; ii < CB_MAX_CHANNEL_24G; ii++) {
pDevice->abyCCKPwrTbl[ii + 1] =
SROMbyReadEmbedded(pDevice->PortOffset,
(unsigned char)(ii + EEP_OFS_CCK_PWR_TBL));
if (pDevice->abyCCKPwrTbl[ii + 1] == 0)
pDevice->abyCCKPwrTbl[ii+1] = pDevice->byCCKPwr;
pDevice->abyOFDMPwrTbl[ii + 1] =
SROMbyReadEmbedded(pDevice->PortOffset,
(unsigned char)(ii + EEP_OFS_OFDM_PWR_TBL));
if (pDevice->abyOFDMPwrTbl[ii + 1] == 0)
pDevice->abyOFDMPwrTbl[ii + 1] = pDevice->byOFDMPwrG;
pDevice->abyCCKDefaultPwr[ii + 1] = byCCKPwrdBm;
pDevice->abyOFDMDefaultPwr[ii + 1] = byOFDMPwrdBm;
}
/* recover 12,13 ,14channel for EUROPE by 11 channel */
for (ii = 11; ii < 14; ii++) {
pDevice->abyCCKPwrTbl[ii] = pDevice->abyCCKPwrTbl[10];
pDevice->abyOFDMPwrTbl[ii] = pDevice->abyOFDMPwrTbl[10];
}
/* Load OFDM A Power Table */
for (ii = 0; ii < CB_MAX_CHANNEL_5G; ii++) {
pDevice->abyOFDMPwrTbl[ii + CB_MAX_CHANNEL_24G + 1] =
SROMbyReadEmbedded(pDevice->PortOffset,
(unsigned char)(ii + EEP_OFS_OFDMA_PWR_TBL));
pDevice->abyOFDMDefaultPwr[ii + CB_MAX_CHANNEL_24G + 1] =
SROMbyReadEmbedded(pDevice->PortOffset,
(unsigned char)(ii + EEP_OFS_OFDMA_PWR_dBm));
}
if (pDevice->byLocalID > REV_ID_VT3253_B1) {
MACvSelectPage1(pDevice->PortOffset);
VNSvOutPortB(pDevice->PortOffset + MAC_REG_MSRCTL + 1,
(MSRCTL1_TXPWR | MSRCTL1_CSAPAREN));
MACvSelectPage0(pDevice->PortOffset);
}
/* use relative tx timeout and 802.11i D4 */
MACvWordRegBitsOn(pDevice->PortOffset,
MAC_REG_CFG, (CFG_TKIPOPT | CFG_NOTXTIMEOUT));
/* set performance parameter by registry */
MACvSetShortRetryLimit(pDevice->PortOffset, pDevice->byShortRetryLimit);
MACvSetLongRetryLimit(pDevice->PortOffset, pDevice->byLongRetryLimit);
/* reset TSF counter */
VNSvOutPortB(pDevice->PortOffset + MAC_REG_TFTCTL, TFTCTL_TSFCNTRST);
/* enable TSF counter */
VNSvOutPortB(pDevice->PortOffset + MAC_REG_TFTCTL, TFTCTL_TSFCNTREN);
/* initialize BBP registers */
BBbVT3253Init(pDevice);
if (pDevice->bUpdateBBVGA) {
pDevice->byBBVGACurrent = pDevice->abyBBVGA[0];
pDevice->byBBVGANew = pDevice->byBBVGACurrent;
BBvSetVGAGainOffset(pDevice, pDevice->abyBBVGA[0]);
}
BBvSetRxAntennaMode(pDevice, pDevice->byRxAntennaMode);
BBvSetTxAntennaMode(pDevice, pDevice->byTxAntennaMode);
/* Set BB and packet type at the same time. */
/* Set Short Slot Time, xIFS, and RSPINF. */
pDevice->wCurrentRate = RATE_54M;
pDevice->bRadioOff = false;
pDevice->byRadioCtl = SROMbyReadEmbedded(pDevice->PortOffset,
EEP_OFS_RADIOCTL);
pDevice->bHWRadioOff = false;
if (pDevice->byRadioCtl & EEP_RADIOCTL_ENABLE) {
/* Get GPIO */
MACvGPIOIn(pDevice->PortOffset, &pDevice->byGPIO);
if (((pDevice->byGPIO & GPIO0_DATA) &&
!(pDevice->byRadioCtl & EEP_RADIOCTL_INV)) ||
(!(pDevice->byGPIO & GPIO0_DATA) &&
(pDevice->byRadioCtl & EEP_RADIOCTL_INV)))
pDevice->bHWRadioOff = true;
}
if (pDevice->bHWRadioOff || pDevice->bRadioControlOff)
CARDbRadioPowerOff(pDevice);
/* get Permanent network address */
SROMvReadEtherAddress(pDevice->PortOffset, pDevice->abyCurrentNetAddr);
pr_debug("Network address = %pM\n", pDevice->abyCurrentNetAddr);
/* reset Tx pointer */
CARDvSafeResetRx(pDevice);
/* reset Rx pointer */
CARDvSafeResetTx(pDevice);
if (pDevice->byLocalID <= REV_ID_VT3253_A1)
MACvRegBitsOn(pDevice->PortOffset, MAC_REG_RCR, RCR_WPAERR);
/* Turn On Rx DMA */
MACvReceive0(pDevice->PortOffset);
MACvReceive1(pDevice->PortOffset);
/* start the adapter */
MACvStart(pDevice->PortOffset);
}
VOID GMACvGetRxThreshold(DWORD dwIoBase, PBYTE pbyThreshold)
{
/* first, get MCFG0 */
VNSvInPortB(dwIoBase + MAC_REG_MCFG0, pbyThreshold);
*pbyThreshold = (BYTE)((*pbyThreshold >> 4) & 0x03);
}