VOID GMACvSaveContext(DWORD dwIoBase, BYTE byRevId, PBYTE pbyCxtBuf)
{
int ii;
/* save RCR,TCR,CR,ISR,IMR... */
for (ii = MAC_REG_PAR; ii < MAC_REG_DEC_BASE_HI; ii++) {
if (ii >= MAC_REG_CR0_CLR && ii <= MAC_REG_CR3_CLR)
continue;
VNSvInPortB(dwIoBase + ii, (PBYTE)(pbyCxtBuf + ii));
}
/* save MAC_REG_DEC_BASE_HI... */
for (ii = MAC_REG_DEC_BASE_HI; ii < MAC_REG_ISR_CTL; ii += 4)
VNSvInPortD(dwIoBase + ii, (PDWORD)(pbyCxtBuf + ii));
/* save ISR_CTL,ISR,IMR,TDCSR,RDCSR.. */
for (ii = MAC_REG_ISR_CTL; ii < MAC_REG_TDCSR_CLR; ii++)
VNSvInPortB(dwIoBase + ii, (PBYTE)(pbyCxtBuf + ii));
/* save MAC_REG_RDBASE_LO,MAC_REG_TDBASE_LO... */
for (ii = MAC_REG_RDBASE_LO; ii < MAC_REG_FIFO_TEST0; ii += 4)
VNSvInPortD(dwIoBase + ii, (PDWORD)(pbyCxtBuf + ii));
/* save MIICFG... */
for (ii = MAC_REG_MIICFG; ii < MAC_REG_TBIST; ii++)
VNSvInPortB(dwIoBase + ii, (PBYTE)(pbyCxtBuf + ii));
/* save GHIPGSR, WOLCR, PWCFG, TestReg, WOLCG ... */
for (ii = MAC_REG_CHIPGSR; ii < MAC_REG_WOLCR0_CLR; ii++)
VNSvInPortB(dwIoBase + ii, (PBYTE)(pbyCxtBuf + ii));
/* save pattern, mask */
for (ii = MAC_REG_PATRN_CRC0; ii < MAC_REG_BYTEMSK3_3 + 4; ii += 4)
VNSvInPortD(dwIoBase + ii, (PDWORD)(pbyCxtBuf + ii));
}
VOID GMACvReadAllRegs(DWORD dwIoBase, PSMacReg pMacRegs, BYTE byRevId)
{
int ii;
PBYTE pbyData = (PBYTE)pMacRegs;
for (ii = 0; ii < MAC_REG_DEC_BASE_HI; ii++) {
VNSvInPortB(dwIoBase + ii, pbyData);
pbyData++;
}
for ( ; ii < MAC_REG_ISR_CTL; ii += sizeof(DWORD), pbyData += sizeof(DWORD))
VNSvInPortD(dwIoBase + ii, (PDWORD)pbyData);
for ( ; ii < MAC_REG_RDBASE_LO; ii++, pbyData++)
VNSvInPortB(dwIoBase + ii, pbyData);
for ( ; ii < MAC_REG_CAMADDR; ii += sizeof(DWORD), pbyData += sizeof(DWORD))
VNSvInPortD(dwIoBase + ii, (PDWORD)pbyData);
for ( ; ii < MAC_REG_MIBREAD; ii++, pbyData++)
VNSvInPortB(dwIoBase + ii, pbyData);
ii += 4;
pbyData += 4; /* skip MIB_READ_PORT, because it may have side effect. */
for ( ; ii < MAC_REG_WOLCR0_SET; ii++, pbyData++)
VNSvInPortB(dwIoBase + ii, pbyData);
for ( ; ii < MAC_REG_BYTEMSK3_3 + 4; ii += sizeof(DWORD), pbyData += sizeof(DWORD))
VNSvInPortD(dwIoBase + ii, (PDWORD)pbyData);
return;
}
/*
* Description:
* Turn Off MAC Tx
*
* Parameters:
* In:
* dwIoBase - Base Address for MAC
* Out:
* none
*
* Return Value: true if success; otherwise false
*
*/
bool MACbSafeTxOff(void __iomem *dwIoBase)
{
unsigned short ww;
unsigned long dwData;
unsigned char byData;
// Clear TX DMA
//Tx0
VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_CLRRUN);
//AC0
VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_CLRRUN);
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData);
if (!(dwData & DMACTL_RUN))
break;
}
if (ww == W_MAX_TIMEOUT) {
DBG_PORT80(0x20);
pr_debug(" DBG_PORT80(0x20)\n");
return false;
}
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData);
if (!(dwData & DMACTL_RUN))
break;
}
if (ww == W_MAX_TIMEOUT) {
DBG_PORT80(0x21);
pr_debug(" DBG_PORT80(0x21)\n");
return false;
}
// try to safe shutdown TX
MACvRegBitsOff(dwIoBase, MAC_REG_HOSTCR, HOSTCR_TXON);
// W_MAX_TIMEOUT is the timeout period
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
VNSvInPortB(dwIoBase + MAC_REG_HOSTCR, &byData);
if (!(byData & HOSTCR_TXONST))
break;
}
if (ww == W_MAX_TIMEOUT) {
DBG_PORT80(0x24);
pr_debug(" DBG_PORT80(0x24)\n");
return false;
}
return true;
}
VOID GMACvGetMCAM(DWORD dwIoBase, BYTE byAddress, PBYTE pbyData)
{
BYTE byOrgCAMCR, byData;
/* modify CAMCR to select CAM DATA regs */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byOrgCAMCR);
byData = (BYTE)((byOrgCAMCR | CAMCR_PS1) & ~CAMCR_PS0);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byData);
/* enable/select MCAM */
VNSvOutPortB(dwIoBase + MAC_REG_CAMADDR, (BYTE)(CAMADDR_CAMEN | byAddress));
/* issue read command */
MACvRegBitsOn(dwIoBase, MAC_REG_CAMCR, CAMCR_CAMRD);
/* Wait for CAMRD self clear */
while (TRUE) {
if (GMACbIsRegBitsOff(dwIoBase, MAC_REG_CAMCR, CAMCR_CAMRD))
break;
}
VNSvInPortD(dwIoBase + MAC_REG_CAM, (PDWORD)pbyData);
VNSvInPortW(dwIoBase + MAC_REG_CAM + 4, (PWORD)(pbyData + 4));
/* disable CAMEN */
VNSvOutPortB(dwIoBase + MAC_REG_CAMADDR, 0);
/* restore to original CAMCR */
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byOrgCAMCR);
}
/*
* Description:
* Turn Off MAC Rx
*
* Parameters:
* In:
* dwIoBase - Base Address for MAC
* Out:
* none
*
* Return Value: true if success; otherwise false
*
*/
bool MACbSafeRxOff(void __iomem *dwIoBase)
{
unsigned short ww;
unsigned long dwData;
unsigned char byData;
// turn off wow temp for turn off Rx safely
// Clear RX DMA0,1
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_CLRRUN);
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_CLRRUN);
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData);
if (!(dwData & DMACTL_RUN))
break;
}
if (ww == W_MAX_TIMEOUT) {
DBG_PORT80(0x10);
pr_debug(" DBG_PORT80(0x10)\n");
return false;
}
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData);
if (!(dwData & DMACTL_RUN))
break;
}
if (ww == W_MAX_TIMEOUT) {
DBG_PORT80(0x11);
pr_debug(" DBG_PORT80(0x11)\n");
return false;
}
// try to safe shutdown RX
MACvRegBitsOff(dwIoBase, MAC_REG_HOSTCR, HOSTCR_RXON);
// W_MAX_TIMEOUT is the timeout period
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
VNSvInPortB(dwIoBase + MAC_REG_HOSTCR, &byData);
if (!(byData & HOSTCR_RXONST))
break;
}
if (ww == W_MAX_TIMEOUT) {
DBG_PORT80(0x12);
pr_debug(" DBG_PORT80(0x12)\n");
return false;
}
return true;
}
VOID GMACvGetVCAMMask(DWORD dwIoBase, PBYTE pbyMask)
{
BYTE byOrgCAMCR, byData;
/* modify CAMCR to select CAM MASK regs */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byOrgCAMCR);
byData = (BYTE)((byOrgCAMCR & ~CAMCR_PS1) | CAMCR_PS0);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byData);
/* select VCAM Mask */
VNSvOutPortB(dwIoBase + MAC_REG_CAMADDR, CAMADDR_VCAMSL);
VNSvInPortD(dwIoBase + MAC_REG_CAM, (PDWORD)pbyMask);
VNSvInPortD(dwIoBase + MAC_REG_CAM + 4, (PDWORD)(pbyMask + 4));
/* restore to original CAMCR */
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byOrgCAMCR);
}
/*
* Description:
* Test if MAC interrupt disable
*
* Parameters:
* In:
* dwIoBase - Base Address for MAC
* Out:
* none
*
* Return Value: true if interrupt is disable; otherwise false
*
*/
bool MACbIsIntDisable(void __iomem *dwIoBase)
{
unsigned long dwData;
VNSvInPortD(dwIoBase + MAC_REG_IMR, &dwData);
if (dwData != 0)
return false;
return true;
}
BOOL GMACbIsIntDisable(DWORD dwIoBase, BYTE byRevId)
{
DWORD dwData;
VNSvInPortD(dwIoBase + MAC_REG_IMR, &dwData);
if (dwData != 0x00000000UL)
return FALSE;
return TRUE;
}
void dumpmac(int iobase)
{
int i = 0;
DWORD data;
for (i = 0; i < 0x80; i += 4) {
VNSvInPortD(iobase+i, &data);
printf("mac %8x:%8x\n", i, data);
}
return;
}
VOID GMACvGetMCAMMask(DWORD dwIoBase, PBYTE pbyMask)
{
BYTE byOrgCAMCR, byData;
/* modify CAMCR to select CAM MASK regs */
VNSvInPortB(dwIoBase + MAC_REG_CAMCR, &byOrgCAMCR);
byData = (BYTE)((byOrgCAMCR & ~CAMCR_PS1) | CAMCR_PS0);
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byData);
/* Select MCAM Mask */
VNSvOutPortB(dwIoBase + MAC_REG_CAMADDR, 0);
/* select CAM and read CAM mask data (don't need to set CAMEN) */
VNSvOutPortB(dwIoBase + MAC_REG_CAMADDR, 0);
VNSvInPortD(dwIoBase + MAC_REG_CAM, (PDWORD)pbyMask);
VNSvInPortD(dwIoBase + MAC_REG_CAM + 4, (PDWORD)(pbyMask + 4));
/* restore to original CAMCR */
VNSvOutPortB(dwIoBase + MAC_REG_CAMCR, byOrgCAMCR);
}
static void register_dump(void)
{
int i;
DWORD state;
printf("resister dump-------------------------------------------\n");
for (i = 0; i < 32; i++) {
VNSvInPortD(sg_aAdapter->dwIoBase+4*i, &state);
printf("%08X\n", state);
}
printf("--------------------------------------------------------\n");
return;
}
/*
* Description: Write to IF/RF, by embeded programming
*
* Parameters:
* In:
* dwIoBase - I/O base address
* dwData - data to write
* Out:
* none
*
* Return Value: TRUE if succeeded; FALSE if failed.
*
*/
BOOL IFRFbWriteEmbeded (DWORD_PTR dwIoBase, DWORD dwData)
{
WORD ww;
DWORD dwValue;
VNSvOutPortD(dwIoBase + MAC_REG_IFREGCTL, dwData);
// W_MAX_TIMEOUT is the timeout period
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
VNSvInPortD(dwIoBase + MAC_REG_IFREGCTL, &dwValue);
if (dwValue & IFREGCTL_DONE)
break;
}
if (ww == W_MAX_TIMEOUT) {
// DBG_PORT80_ALWAYS(0x32);
return FALSE;
}
return TRUE;
}
/*
* Description: Write to IF/RF, by embeded programming
*
* Parameters:
* In:
* dwIoBase - I/O base address
* dwData - data to write
* Out:
* none
*
* Return Value: true if succeeded; false if failed.
*
*/
bool IFRFbWriteEmbeded (unsigned long dwIoBase, unsigned long dwData)
{
unsigned short ww;
unsigned long dwValue;
VNSvOutPortD(dwIoBase + MAC_REG_IFREGCTL, dwData);
// W_MAX_TIMEOUT is the timeout period
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
VNSvInPortD(dwIoBase + MAC_REG_IFREGCTL, &dwValue);
if (dwValue & IFREGCTL_DONE)
break;
}
if (ww == W_MAX_TIMEOUT) {
// DBG_PORT80_ALWAYS(0x32);
return false;
}
return true;
}
/*
* Description: Write to IF/RF, by embedded programming
*
* Parameters:
* In:
* iobase - I/O base address
* dwData - data to write
* Out:
* none
*
* Return Value: true if succeeded; false if failed.
*
*/
bool IFRFbWriteEmbedded(struct vnt_private *priv, unsigned long dwData)
{
void __iomem *iobase = priv->PortOffset;
unsigned short ww;
unsigned long dwValue;
VNSvOutPortD(iobase + MAC_REG_IFREGCTL, dwData);
/* W_MAX_TIMEOUT is the timeout period */
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
VNSvInPortD(iobase + MAC_REG_IFREGCTL, &dwValue);
if (dwValue & IFREGCTL_DONE)
break;
}
if (ww == W_MAX_TIMEOUT)
return false;
return true;
}