pr_debug("stm pm mpe42: ClockGens A: restored\n"); } #define MPE42_DDR_PLL_CFG MPE42_DDR_SYSCFG(7502) #define MPE42_DDR_PLL_STATUS MPE42_DDR_SYSCFG(7569) #define SELF_REFRESH_ON_PCTL 1 static const long stx_mpe42_ddr0_enter[] = { #ifdef SELF_REFRESH_ON_PCTL synopsys_ddr32_in_self_refresh(MPE42_DDR_PCTL_BASE(0)), #else UPDATE32(MPE42_DDR_PWR_DWN(0), ~MPE42_DDR_PWR_DWN_REQ, 0), WHILE_NE32(MPE42_DDR_PWR_STATUS(0), MPE42_DDR_PWR_STATUS_ACK, 0), #endif synopsys_ddr32_phy_standby_enter(MPE42_DDR_PCTL_BASE(0)), }; static const long stx_mpe42_ddr1_enter[] = { #ifdef SELF_REFRESH_ON_PCTL synopsys_ddr32_in_self_refresh(MPE42_DDR_PCTL_BASE(1)), #else UPDATE32(MPE42_DDR_PWR_DWN(1), ~MPE42_DDR_PWR_DWN_REQ, 0), WHILE_NE32(MPE42_DDR_PWR_STATUS(1), MPE42_DDR_PWR_STATUS_ACK, 0), #endif synopsys_ddr32_phy_standby_enter(MPE42_DDR_PCTL_BASE(1)),
synopsys_ddr32_phy_standby_enter(STIG125_DDR_PCTL_BASE), POKE32(CLK_A1_BASE + SASC_SWITCH_CFG(0), 0), POKE32(CLK_A1_BASE + SASC_POWER_CFG, 0x3), /* bypass and disable the A9.PLL */ OR32(SYSCONF_CPU_722, 1 << 2), OR32(SYSCONF_CPU_722, 1), END_MARKER, }; static long stig125_ddr0_exit[] = { /* enable, wait and don't bypass the A9.PLL */ UPDATE32(SYSCONF_CPU_722, ~1, 0), WHILE_NE32(SYSCONF_CPU_760, 1, 1), UPDATE32(SYSCONF_CPU_722, ~(1 << 2), 0), /* turn-on A1.PLLs */ POKE32(CLK_A1_BASE + SASC_POWER_CFG, 0x0), /* Wait A1.PLLs are locked */ WHILE_NE32(CLK_A1_BASE + SASC_PLL_LOCK_REG(0), SASC_PLL_LOCK_STATUS, SASC_PLL_LOCK_STATUS), WHILE_NE32(CLK_A1_BASE + SASC_PLL_LOCK_REG(1), SASC_PLL_LOCK_STATUS, SASC_PLL_LOCK_STATUS), OR32(CLK_A1_BASE + SASC_SWITCH_CFG(0), 0x1 << DDR_CLK_SHIFT), synopsys_ddr32_phy_standby_exit(STIG125_DDR_PCTL_BASE), synopsys_ddr32_out_of_self_refresh(STIG125_DDR_PCTL_BASE),
synopsys_ddr32_phy_standby_enter(DDR3SS_REG), OR32(CLK_A1_BASE + CKGA_POWER_CFG, 3), /* END. */ END_MARKER, /* * Turn-on DDR clock: * The DDR subsystem uses the channel coming from A1.HS_0 * this means there is _no_ ClockGen_D... * * - turn on the A1.PLLs * - wait both the PLLs are locked */ UPDATE32(CLK_A1_BASE + CKGA_POWER_CFG, 0, ~0x3), WHILE_NE32(SYSTEM_STATUS_160, 3, 3), synopsys_ddr32_phy_standby_exit(DDR3SS_REG), synopsys_ddr32_out_of_self_refresh(DDR3SS_REG), END_MARKER }; static int stxh205_suspend_begin(suspend_state_t state) { pr_info("[STM][PM] Analyzing the wakeup devices\n"); stm_check_wakeup_devices(&stxh205_wkd); return 0; }
*/ static unsigned long fli7510_standby_table[] __cacheline_aligned = { END_MARKER, END_MARKER }; /* ********************* * MEM INSTRUCTION TABLE * ********************* */ static unsigned long fli7510_mem_table[] __cacheline_aligned = { /* 1. Enables the DDR self refresh mode based on paraghaph. 7.1.4 * -> from ACCESS to LowPower */ POKE32(DDR0_BASE_REG + DDR_SCTL, DDR_SCTL_SLEEP), WHILE_NE32(DDR0_BASE_REG + DDR_STAT, DDR_STAT_LOW_POWER, DDR_STAT_LOW_POWER), #if 0 OR32(DDR0_BASE_REG + DDR_PHY_IOCRV1, 1), OR32(DDR0_BASE_REG + DDR_PHY_DXCCR, 1), #endif POKE32(DDR1_BASE_REG + DDR_SCTL, DDR_SCTL_SLEEP), WHILE_NE32(DDR1_BASE_REG + DDR_STAT, DDR_STAT_LOW_POWER, DDR_STAT_LOW_POWER), #if 0 OR32(DDR1_BASE_REG + DDR_PHY_IOCRV1, 1), OR32(DDR1_BASE_REG + DDR_PHY_DXCCR, 1), OR32(DDR0_BASE_REG + DDR_PHY_PIR, 1 << 7), OR32(DDR1_BASE_REG + DDR_PHY_PIR, 1 << 7), #endif
/* reduces OSC_st40 */ POKE32(CGA + CKGA_OSC_DIV_CFG(17), 0), /* ic_if_200 */ END_MARKER }; /* ********************* * MEM INSTRUCTION TABLE * ********************* */ static unsigned long stx7111_mem_table[] __cacheline_aligned = { /* 1. Enables the DDR self refresh mode */ OR32(_SYS_CFG(38), (1 << 20)), /* waits until the ack bit is zero */ WHILE_NE32(_SYS_STA(4), 1, 1), /* Disable the analogue input buffers of the pads */ OR32(_SYS_CFG(12), (1 << 10)), /* Disable the clock output */ UPDATE32(_SYS_CFG(4), ~(1 << 2), 0), /* 1.1 Turn-off the ClockGenD */ OR32(_SYS_CFG(11), (1 << 12)), /* wait clock gen lock */ WHILE_NE32(_SYS_STA(3), 1, 1), POKE32(CGA + CKGA_OSC_DIV_CFG(17), 31), /* ic_if_200 */ END_MARKER, /*
END_MARKER, END_MARKER }; /* ********************* * MEM INSTRUCTION TABLE * ********************* */ static unsigned long stx5206_mem_table[] __cacheline_aligned = { /* 1. Enables the DDR self refresh mode */ OR32(SYSCONF(38), (1 << 20)), /* waits until the ack bit is zero */ WHILE_NE32(SYSSTA(4), 1, 1), /* Disable the clock output */ UPDATE32(SYSCONF(4), ~(1 << 2), 0), /* Disable the analogue input buffers of the pads */ OR32(SYSCONF(12), (1 << 10)), /* 1.1 Turn-off the ClockGenD */ OR32(SYSCONF(11), (1 << 12)), /* wait clock gen lock */ WHILE_NE32(SYSSTA(3), 1, 1), END_MARKER, UPDATE32(SYSCONF(12), ~(1 << 10), 0), /* Reset LMI Pad logic */ OR32(SYSCONF(11), (1 << 27)),