static void xycom566isr(void *arg) { xy566 *card=arg; epicsUInt16 csr; csr=READ16(card->base, XY566_CSR); if(!(csr&XY566_CSR_PND)) return; /* not ours */ if(card->use_seq_clk) WRITE8(card->base, XY566_STC, 0xC2); /* Disarm Seq. trig clock */ /* Disable sequence controller, acknowledge * interrupts, and schedule further processing * out of interrupt context */ csr&=~XY566_CSR_SEQ; /* disable seq. cont. */ /* writing back what was read will clear any pending * interrupts */ WRITE16(card->base, XY566_CSR, csr); callbackRequest(&card->cb_irq); return; }
void i386_device::i486_cmpxchg_rm8_r8() // Opcode 0x0f b0 { UINT8 modrm = FETCH(); if( modrm >= 0xc0 ) { UINT8 dst = LOAD_RM8(modrm); UINT8 src = LOAD_REG8(modrm); if( REG8(AL) == dst ) { STORE_RM8(modrm, src); m_ZF = 1; CYCLES(CYCLES_CMPXCHG_REG_REG_T); } else { REG8(AL) = dst; m_ZF = 0; CYCLES(CYCLES_CMPXCHG_REG_REG_F); } } else { // TODO: Check write if needed UINT32 ea = GetEA(modrm,0); UINT8 dst = READ8(ea); UINT8 src = LOAD_REG8(modrm); if( REG8(AL) == dst ) { WRITE8(ea, src); m_ZF = 1; CYCLES(CYCLES_CMPXCHG_REG_MEM_T); } else { REG8(AL) = dst; m_ZF = 0; CYCLES(CYCLES_CMPXCHG_REG_MEM_F); } } }
static void I486OP(cmpxchg_rm8_r8)(i386_state *cpustate) // Opcode 0x0f b0 { UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT8 dst = LOAD_RM8(modrm); UINT8 src = LOAD_REG8(modrm); if( REG8(AL) == dst ) { STORE_RM8(modrm, src); cpustate->ZF = 1; CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_T); } else { REG8(AL) = dst; cpustate->ZF = 0; CYCLES(cpustate,CYCLES_CMPXCHG_REG_REG_F); } } else { UINT32 ea = GetEA(cpustate,modrm); UINT8 dst = READ8(cpustate,ea); UINT8 src = LOAD_REG8(modrm); if( REG8(AL) == dst ) { WRITE8(cpustate,modrm, src); cpustate->ZF = 1; CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_T); } else { REG8(AL) = dst; cpustate->ZF = 0; CYCLES(cpustate,CYCLES_CMPXCHG_REG_MEM_F); } } }
static void Mcu_ConfigureFlash(void) { /* These flash settings increases the CPU performance of 7 times compared to reset default settings!! */ #if defined(CFG_MPC5516) /* Have 2 ports, p0 and p1 * - All Z1 instructions go to port 0 * - All Z1 data go to port 1 * * --> Flash port 0 is ONLY used by Z1 instructions. */ /* Disable pipelined reads when flash options are changed. */ FLASH.MCR.B.PRD = 1; /* Errata e1178 (note that Errata A is the same as Errata B) * - Disable all prefetch for all masters * - Fixed Arb mode+ Port 0 highest prio * - PFCRPn[RWSC] = 0b010; PFCRPn[WWSC] = 0b01 for 80Mhz (MPC5516 data sheeet) * - APC = RWSC, The settings for APC and RWSC should be the same. ( MPC5516 ref. manual) */ FLASH.PFCRP0.R = PFCR_LBCFG(0) + PFCR_ARB + PFCR_APC(2) + PFCR_RWSC(2) + PFCR_WWSC(1) + PFCR_BFEN; FLASH.PFCRP1.R = PFCR_LBCFG(3) + PFCR_APC(2) + PFCR_RWSC(2) + PFCR_WWSC(1) + PFCR_BFEN; /* Enable pipelined reads again. */ FLASH.MCR.B.PRD = 0; #elif defined(CFG_MPC5668) /* Check values from cookbook and MPC5668x Microcontroller Data Sheet */ /* Should probably trim this values */ const typeof(FLASH.PFCRP0.B) val = {.M0PFE = 1, .M2PFE=1, .APC=3, .RWSC=3, .WWSC =1, .DPFEN = 0, .IPFEN = 1, .PFLIM =2, .BFEN = 1 }; FLASH.PFCRP0.B = val; /* Enable pipelined reads again. */ #elif defined(CFG_MPC5554) || defined(CFG_MPC5567) FLASH.BIUCR.R = 0x00104B3D; /* value for up to 128 MHz */ #elif defined(CFG_MPC5606S) CFLASH0.PFCR0.R = 0x10840B6F; /* Instruction prefetch enabled and other according to cookbook */ #elif defined(CFG_MPC563XM) CFLASH0.BIUCR.R = 0x00006b57; /* Prefetch disabled due to flash driver limitations */ #elif defined(CFG_MPC560X) CFLASH.PFCR0.R = 0x10840B6F; /* Instruction prefetch enabled and other according to cookbook */ #endif /* Enable error reporting on Flash (FEAR, etc will be updated) */ WRITE8(ECSM_BASE+ECSM_ECR,ESR_F1BC+ESR_FNCE); } uint32 EccErrReg = 0; void McuE_GetECCError( uint32 *err ) { *err = EccErrReg; /* Clear stored */ EccErrReg = 0; }
void evgEvtClk::setSource (epicsUInt16 source) { epicsUInt8 clkReg, regMap = 0; epicsUInt32 version; version = READ32(m_pReg, FWVersion); version &= FWVersion_ver_mask; if ((RFClockReference) source >= RFClockReference_PXIe100 && version < EVG_FCT_MIN_FIRMWARE ) { throw std::out_of_range("RF clock source you selected does not exist in this firmware version."); } else if ((RFClockReference) source >= RFClockReference_ExtDownrate && version < EVG_MIN_FIRMWARE_REDUCECLK ) { throw std::out_of_range("RF clock source you selected does not exist in this firmware version."); } switch ((RFClockReference) source) { case RFClockReference_Internal: regMap = EVG_CLK_SRC_INTERNAL; break; case RFClockReference_External: regMap = EVG_CLK_SRC_EXTERNAL; break; case RFClockReference_PXIe100: regMap = EVG_CLK_SRC_PXIE100; break; case RFClockReference_PXIe10: regMap = EVG_CLK_SRC_PXIE10; break; case RFClockReference_Recovered: regMap = EVG_CLK_SRC_RECOVERED; break; case RFClockReference_ExtDownrate: regMap = EVG_CLK_SRC_EXTDOWNRATE; break; case RFClockReference_RecoverHalved: regMap = EVG_CLK_SRC_RECOVERHALVED; break; default: throw std::out_of_range("RF clock source you selected does not exist."); break; } clkReg = READ8(m_pReg, ClockSource); // read register content clkReg &= ~EVG_CLK_SRC_SEL; // clear old clock source clkReg |= regMap; // set new clock source WRITE8(m_pReg, ClockSource, clkReg); // write the new value to the register }
void evgEvtClk::setRFDiv(epicsUInt32 rfDiv) { if(rfDiv < 1 || rfDiv > 32) { char err[80]; sprintf(err, "Invalid RF Divider %d. Valid range is 1 - 32", rfDiv); std::string strErr(err); throw std::runtime_error(strErr); } WRITE8(m_pReg, RfDiv, rfDiv-1); }
static void xycom566isrcb(CALLBACK *cb) { xy566 *card; epicsUInt16 csr; epicsUInt16 datacnt[32]; epicsUInt16 dcnt; size_t i, ch; callbackGetUser(card,cb); epicsMutexMustLock(card->guard); /* clear number of data points */ memset(datacnt,0,sizeof(datacnt)); /* number of samples taken */ dcnt=READ16(card->base, XY566_RAM); if(dcnt>256){ /* Somehow the sequence was restart w/o resetting * the pointer, or changed by an outside program */ dcnt=256; printf("Data longer then expected\n"); } for(i=0;i<dcnt;i++){ ch=card->seq[i]&0x1f; card->data[ch][datacnt[ch]]=READ16(card->data_base, XY566_DOFF(i)); datacnt[ch]++; if( card->seq[i]&SEQ_END ) break; } /* reset pointers */ WRITE16(card->base, XY566_RAM, 0); WRITE8(card->base, XY566_SEQ, 0); csr=READ16(card->base, XY566_CSR); /* enable sequence controller */ csr|=XY566_CSR_SEQ; WRITE16(card->base, XY566_CSR, csr); scanIoRequest(card->seq_irq); epicsMutexUnlock(card->guard); }
uint32_t SIZE_OPTIMIZATION WaitEEWriteToFinish(PFLASH_SSD_CONFIG pSSDConfig, uint32_t* dest,\ uint32_t* size, uint8_t** pData, uint8_t step) { uint32_t ret; /* return code variable */ uint32_t temp; /* temporary variable */ if (0x01U == step) { WRITE8(*dest, READ8(*pData)); } if (0x02U == step) { #if(BIG_ENDIAN == ENDIANNESS) temp = (uint32_t)READ8(*pData) << 8; temp |= (uint32_t)(READ8(*pData + 1)); #else temp = (uint32_t)READ8(*pData + 1) << 8; temp |= (uint32_t)(READ8(*pData)); #endif WRITE16(BYTE2WORD(*dest), (uint16_t)temp); } if (0x04U == step) { #if(BIG_ENDIAN == ENDIANNESS) temp = (uint32_t)READ8(*pData) << 24; temp |= (uint32_t)(READ8(*pData + 1)) << 16; temp |= (uint32_t)(READ8(*pData + 2)) << 8; temp |= (uint32_t)(READ8(*pData + 3)); #else temp = (uint32_t)READ8(*pData + 3) << 24; temp |= (uint32_t)(READ8(*pData + 2)) << 16; temp |= (uint32_t)(READ8(*pData + 1)) << 8; temp |= (uint32_t)READ8(*pData); #endif WRITE32(BYTE2WORD(*dest), (uint32_t)temp); } temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCNFG_OFFSET; while(0x0U == REG_BIT_GET(temp, FTFx_SSD_FCNFG_EEERDY)) { /* wait till EEERDY bit is set */ } /* Check for protection violation error */ temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET; ret = (uint32_t)REG_READ(temp) & FTFx_SSD_FSTAT_FPVIOL; *dest += step; *size -= step; *pData += step; return ret; }
void evgSeqRam::setTrigSrc(SeqTrigSrc trigSrc) { if(trigSrc == Software){ if(!m_id) trigSrc = SoftRam0; else trigSrc = SoftRam1; } /*Here we allow only one external input at a time to act as a trigger source *for the Sequencer. In theory mutliple external input can act as a trigger *source simultaneously */ if(trigSrc > External) { /* *When we set the trigger source to a new external input we should disable *the previous external input trigger. Since we dont keep track of the *previous trigger source we disable the trigger from all the *external inputs. */ for(int i = 0; i < evgNumFrontInp; i++) disableSeqExtTrig(m_owner->getInput(i, FrontInp)); for(int i = 0; i < evgNumUnivInp; i++) disableSeqExtTrig(m_owner->getInput(i, UnivInp)); for(int i = 0; i < evgNumRearInp; i++) disableSeqExtTrig(m_owner->getInput(i, RearInp)); /* *Now enable the triggering only on the appropraite external input of EVG. *Each external input is identified by its number and its type. The *SeqTrigSrc value for each input is chosen in such a way that when you *divide it by 4 the quotient will give you the input number and *remainder will give you the input type. */ div_t divResult = div((epicsUInt32)trigSrc-40, 4); evgInput* inp = m_owner->getInput(divResult.quot, (InputType)divResult.rem); epicsUInt32 map = inp->getSeqTrigMap(); map = map | (m_id+1); inp->setSeqTrigMap(map); if(!m_id) trigSrc = ExtRam0; else trigSrc = ExtRam1; } WRITE8(m_pReg, SeqTrigSrc(m_id), trigSrc); }
static long write_gain(mbboRecord* prec) { xy566 *card=prec->dpvt; short chan=prec->out.value.vmeio.signal; if(chan < 0 || chan > card->nchan) return 1; WRITE8(card->base, XY566_GAIN(chan), prec->rval); prec->rbv=READ8(card->base, XY566_GAIN(chan)); return 0; }
void xycom566finish(void) { ELLNODE *node; xy566* card; epicsUInt16 csr; for(node=ellFirst(&xy566s); node; node=ellNext(node)) { card=node2priv(node); if(!card->fail){ if(!!finish566seq(card)){ printf("Board #%d failed to generate samping sequence and will not be used\n",card->id); card->fail=1; } } if(!card->clk_div){ printf("Board #%d STC not initialized and will not be used\n",card->id); card->fail=1; } if(!!card->fail){ printf("Board #%d failed to initialize and will not be used\n",card->id); /* Reset the board again and * turn off the LEDS to indicate failure */ WRITE16(card->base, XY566_CSR, XY566_CSR_RST); WRITE16(card->base, XY566_CSR, XY566_CSR_RED); return; } WRITE16(card->base, XY566_RAM, 0); WRITE8(card->base, XY566_SEQ, 0); csr=READ16(card->base, XY566_CSR); csr|=XY566_CSR_SEQ|XY566_CSR_INA|XY566_CSR_SIE; csr|=XY566_CSR_RED|XY566_CSR_GRN; WRITE16(card->base, XY566_CSR, csr); } return; }
void evgEvtClk::setPLLBandwidth(PLLBandwidth pllBandwidth) { epicsUInt8 clkCtrl; epicsUInt8 bw; if(pllBandwidth > PLLBandwidth_MAX){ throw std::out_of_range("PLL bandwith you selected is not available."); } bw = (epicsUInt8)pllBandwidth; bw = bw << EVG_CLK_BW_shift; // shift appropriately clkCtrl = READ8(m_pReg, ClockSource); // read register content clkCtrl &= ~EVG_CLK_BW; // clear bw_sel clkCtrl |= bw; // OR bw sel value WRITE8(m_pReg, ClockSource, clkCtrl); // write the new value to the register }
void i386_device::i486_xadd_rm8_r8() // Opcode 0x0f c0 { UINT8 modrm = FETCH(); if( modrm >= 0xc0 ) { UINT8 dst = LOAD_RM8(modrm); UINT8 src = LOAD_REG8(modrm); STORE_REG8(modrm, dst); STORE_RM8(modrm, dst + src); CYCLES(CYCLES_XADD_REG_REG); } else { UINT32 ea = GetEA(modrm,1); UINT8 dst = READ8(ea); UINT8 src = LOAD_REG8(modrm); WRITE8(ea, dst + src); STORE_REG8(modrm, dst); CYCLES(CYCLES_XADD_REG_MEM); } }
static void I486OP(xadd_rm8_r8)(i386_state *cpustate) // Opcode 0x0f c0 { UINT8 modrm = FETCH(cpustate); if( modrm >= 0xc0 ) { UINT8 dst = LOAD_RM8(modrm); UINT8 src = LOAD_REG8(modrm); STORE_RM16(modrm, dst + src); STORE_REG16(modrm, dst); CYCLES(cpustate,CYCLES_XADD_REG_REG); } else { UINT32 ea = GetEA(cpustate,modrm); UINT8 dst = READ8(cpustate,ea); UINT8 src = LOAD_REG8(modrm); WRITE8(cpustate,ea, dst + src); STORE_REG8(modrm, dst); CYCLES(cpustate,CYCLES_XADD_REG_MEM); } }
void nsZipHeader::Init(const nsACString & aPath, PRTime aDate, PRUint32 aAttr, PRUint32 aOffset) { NS_ASSERTION(!mInited, "Already initalised"); PRExplodedTime time; PR_ExplodeTime(aDate, PR_LocalTimeParameters, &time); mTime = time.tm_sec / 2 + (time.tm_min << 5) + (time.tm_hour << 11); mDate = time.tm_mday + ((time.tm_month + 1) << 5) + ((time.tm_year - 1980) << 9); // Store modification timestamp as extra field // First fill CDS extra field mFieldLength = 9; mExtraField = new PRUint8[mFieldLength]; if (!mExtraField) { mFieldLength = 0; } else { PRUint32 pos = 0; WRITE16(mExtraField.get(), &pos, ZIP_EXTENDED_TIMESTAMP_FIELD); WRITE16(mExtraField.get(), &pos, 5); WRITE8(mExtraField.get(), &pos, ZIP_EXTENDED_TIMESTAMP_MODTIME); WRITE32(mExtraField.get(), &pos, aDate / PR_USEC_PER_SEC); // Fill local extra field mLocalExtraField = new PRUint8[mFieldLength]; if (mLocalExtraField) { mLocalFieldLength = mFieldLength; memcpy(mLocalExtraField.get(), mExtraField.get(), mLocalFieldLength); } } mEAttr = aAttr; mOffset = aOffset; mName = aPath; mComment = NS_LITERAL_CSTRING(""); // Claim a UTF-8 path in case it needs it. mFlags |= FLAGS_IS_UTF8; mInited = PR_TRUE; }
static long write_output(boRecord* prec) { xy220 *priv=prec->dpvt; short line=prec->out.value.vmeio.signal; int port=line/8; int bit=line%8; epicsUInt8 mask=1<<bit; epicsUInt8 val; if(line<0 || port>XY220_NPORTS){ errMessage(errlogMajor,"I/O bit number out of range"); return 1; } epicsMutexMustLock(priv->guard); val=READ8(priv->base, XY220_PORT(port)); if(dbg220>0) printf("%lx read %02x ",(unsigned long)prec,val); if(prec->rval) val|=mask; else val&=~mask; if(dbg220>0) printf("write %02x\n",val); WRITE8(priv->base, XY220_PORT(port), val); epicsMutexUnlock(priv->guard); return 0; }
static ADDRESS_MAP_START( ms7004_map, AS_IO, 8, ms7004_device ) AM_RANGE(MCS48_PORT_P1, MCS48_PORT_P1) AM_WRITE(p1_w) AM_RANGE(MCS48_PORT_P2, MCS48_PORT_P2) AM_WRITE(p2_w) AM_RANGE(MCS48_PORT_T1, MCS48_PORT_T1) AM_READ(t1_r) AM_RANGE(MCS48_PORT_PROG, MCS48_PORT_PROG) AM_DEVWRITE("i8243", i8243_device, i8243_prog_w) ADDRESS_MAP_END //------------------------------------------------- // MACHINE_CONFIG //------------------------------------------------- static MACHINE_CONFIG_FRAGMENT( ms7004 ) MCFG_CPU_ADD(MS7004_CPU_TAG, I8048, XTAL_4_608MHz) MCFG_CPU_IO_MAP(ms7004_map) MCFG_I8243_ADD("i8243", NOOP, WRITE8(ms7004_device, i8243_port_w)) MCFG_SPEAKER_STANDARD_MONO("mono") MCFG_SOUND_ADD(MS7004_SPK_TAG, BEEP, 0) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50) MACHINE_CONFIG_END //------------------------------------------------- // machine_config_additions - device-specific // machine configurations //------------------------------------------------- machine_config_constructor ms7004_device::device_mconfig_additions() const { return MACHINE_CONFIG_NAME( ms7004 );
void fbGlyph24(FbBits * dstBits, FbStride dstStride, int dstBpp, FbStip * stipple, FbBits fg, int x, int height) { int lshift; FbStip bits; CARD8 *dstLine; CARD8 *dst; FbStip f0, f1, f2; int n; int shift; f0 = fg; f1 = FbRot24(f0, 16); f2 = FbRot24(f0, 8); dstLine = (CARD8 *) dstBits; dstLine += (x & ~3) * 3; dstStride *= (sizeof(FbBits) / sizeof(CARD8)); shift = x & 3; lshift = 4 - shift; while (height--) { bits = *stipple++; n = lshift; dst = dstLine; while (bits) { switch (FbStipMoveLsb(FbLeftStipBits(bits, n), 4, n)) { case CASE(0, 0, 0, 0): break; case CASE(1, 0, 0, 0): WRITE2(dst, 0, _AB); WRITE1(dst, 2, _C); break; case CASE(0, 1, 0, 0): WRITE1(dst, 3, _A); WRITE2(dst, 4, _BC); break; case CASE(1, 1, 0, 0): WRITE4(dst, 0, _ABCA); WRITE2(dst, 4, _BC); break; case CASE(0, 0, 1, 0): WRITE2(dst, 6, _AB); WRITE1(dst, 8, _C); break; case CASE(1, 0, 1, 0): WRITE2(dst, 0, _AB); WRITE1(dst, 2, _C); WRITE2(dst, 6, _AB); WRITE1(dst, 8, _C); break; case CASE(0, 1, 1, 0): WRITE1(dst, 3, _A); WRITE4(dst, 4, _BCAB); WRITE1(dst, 8, _C); break; case CASE(1, 1, 1, 0): WRITE8(dst); WRITE1(dst, 8, _C); break; case CASE(0, 0, 0, 1): WRITE1(dst, 9, _A); WRITE2(dst, 10, _BC); break; case CASE(1, 0, 0, 1): WRITE2(dst, 0, _AB); WRITE1(dst, 2, _C); WRITE1(dst, 9, _A); WRITE2(dst, 10, _BC); break; case CASE(0, 1, 0, 1): WRITE1(dst, 3, _A); WRITE2(dst, 4, _BC); WRITE1(dst, 9, _A); WRITE2(dst, 10, _BC); break; case CASE(1, 1, 0, 1): WRITE4(dst, 0, _ABCA); WRITE2(dst, 4, _BC); WRITE1(dst, 9, _A); WRITE2(dst, 10, _BC); break; case CASE(0, 0, 1, 1): WRITE2(dst, 6, _AB); WRITE4(dst, 8, _CABC); break; case CASE(1, 0, 1, 1): WRITE2(dst, 0, _AB); WRITE1(dst, 2, _C); WRITE2(dst, 6, _AB); WRITE4(dst, 8, _CABC); break; case CASE(0, 1, 1, 1): WRITE1(dst, 3, _A); WRITE4(dst, 4, _BCAB); WRITE4(dst, 8, _CABC); break; case CASE(1, 1, 1, 1): WRITE8(dst); WRITE4(dst, 8, _CABC); break; } bits = FbStipLeft(bits, n); n = 4; dst += 12; } dstLine += dstStride; } }
MCFG_PIA_WRITEPB_HANDLER(WRITE8(bitgraph_state, pia_pb_w)) MCFG_ER2055_ADD(EAROM_TAG) MCFG_SPEAKER_STANDARD_MONO("mono") MCFG_SOUND_ADD(PSG_TAG, AY8912, XTAL_1_2944MHz) MCFG_AY8910_PORT_A_WRITE_CB(WRITE8(bitgraph_state, earom_write)) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.00) MACHINE_CONFIG_END #ifdef UNUSED_FUNCTION static MACHINE_CONFIG_FRAGMENT( bg_ppu ) MCFG_CPU_ADD(PPU_TAG, I8035, XTAL_6_9MHz) MCFG_CPU_IO_MAP(ppu_io) MCFG_I8243_ADD("i8243", NOOP, WRITE8(bitgraph_state, ppu_i8243_w)) MCFG_CENTRONICS_ADD("centronics", centronics_devices, "printer") MCFG_CENTRONICS_ACK_HANDLER(DEVWRITELINE("cent_status_in", input_buffer_device, write_bit6)) MCFG_CENTRONICS_BUSY_HANDLER(DEVWRITELINE("cent_status_in", input_buffer_device, write_bit7)) MCFG_CENTRONICS_FAULT_HANDLER(DEVWRITELINE("cent_status_in", input_buffer_device, write_bit4)) MCFG_CENTRONICS_PERROR_HANDLER(DEVWRITELINE("cent_status_in", input_buffer_device, write_bit5)) MCFG_DEVICE_ADD("cent_status_in", INPUT_BUFFER, 0) MCFG_CENTRONICS_OUTPUT_LATCH_ADD("cent_data_out", "centronics") MACHINE_CONFIG_END #endif static MACHINE_CONFIG_START( bitgrpha, bitgraph_state ) MCFG_CPU_ADD(M68K_TAG, M68000, XTAL_6_9MHz)
void abc99_device::abc99_z5_mem(address_map &map) { map(0x0000, 0x07ff).rom().region(I8035_Z5_TAG, 0); } //------------------------------------------------- // device_add_mconfig - add device configuration //------------------------------------------------- MACHINE_CONFIG_START(abc99_device::device_add_mconfig) // keyboard CPU MCFG_DEVICE_ADD(I8035_Z2_TAG, I8035, XTAL(6'000'000)/3) // from Z5 T0 output MCFG_DEVICE_PROGRAM_MAP(abc99_z2_mem) MCFG_DEVICE_IO_MAP(abc99_z2_io) MCFG_MCS48_PORT_P1_OUT_CB(WRITE8(*this, abc99_device, z2_p1_w)) MCFG_MCS48_PORT_P2_IN_CB(READ8(*this, abc99_device, z2_p2_r)) MCFG_MCS48_PORT_T0_IN_CB(READLINE(*this, abc99_device, z2_t0_r)) MCFG_MCS48_PORT_T1_IN_CB(READLINE(*this, abc99_device, z2_t1_r)) // mouse CPU MCFG_DEVICE_ADD(I8035_Z5_TAG, I8035, XTAL(6'000'000)) MCFG_DEVICE_PROGRAM_MAP(abc99_z5_mem) //MCFG_MCS48_PORT_P1_IN_CB(READ8(*this, abc99_device, z5_p1_r)) //MCFG_MCS48_PORT_P2_OUT_CB(WRITE8(*this, abc99_device, z5_p2_w)) //MCFG_MCS48_PORT_T0_CLK_CUSTOM() // Z2 CLK //MCFG_MCS48_PORT_T1_IN_CB(READ8(*this, abc99_device, z5_t1_r)) MCFG_DEVICE_DISABLE() // HACK fix for broken serial I/O // sound hardware SPEAKER(config, "mono").front_center();
/* sound hardware */ SPEAKER(config, "mono").front_center(); MCFG_DEVICE_ADD("speaker", SPEAKER_SOUND) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50) /* Devices */ MCFG_DEVICE_ADD("rtc", MM58274C, 0) // this is all a guess MCFG_MM58274C_MODE24(0) // 12 hour MCFG_MM58274C_DAY1(1) // monday MCFG_NSC810_ADD("iotimer",XTAL(4'000'000),XTAL(4'000'000)) MCFG_NSC810_PORTA_READ(READ8(*this, hunter2_state,keyboard_r)) MCFG_NSC810_PORTB_READ(READ8(*this, hunter2_state,serial_dsr_r)) MCFG_NSC810_PORTB_WRITE(WRITE8(*this, hunter2_state,keyboard_w)) MCFG_NSC810_PORTC_READ(READ8(*this, hunter2_state,serial_rx_r)) MCFG_NSC810_TIMER0_OUT(WRITELINE(*this, hunter2_state,timer0_out)) MCFG_NSC810_TIMER1_OUT(WRITELINE(*this, hunter2_state,timer1_out)) RS232_PORT(config, m_rs232, default_rs232_devices, nullptr); m_rs232->cts_handler().set(FUNC(hunter2_state::cts_w)); m_rs232->rxd_handler().set(FUNC(hunter2_state::rxd_w)); NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0); ADDRESS_MAP_BANK(config, "bank1").set_map(&hunter2_state::hunter2_banked_mem).set_endianness(ENDIANNESS_LITTLE).set_data_width(8).set_stride(0x4000); ADDRESS_MAP_BANK(config, "bank2").set_map(&hunter2_state::hunter2_banked_mem).set_endianness(ENDIANNESS_LITTLE).set_data_width(8).set_stride(0x4000); ADDRESS_MAP_BANK(config, "bank3").set_map(&hunter2_state::hunter2_banked_mem).set_endianness(ENDIANNESS_LITTLE).set_data_width(8).set_stride(0x4000); ADDRESS_MAP_BANK(config, "bank4").set_map(&hunter2_state::hunter2_banked_mem).set_endianness(ENDIANNESS_LITTLE).set_data_width(8).set_stride(0x4000); MACHINE_CONFIG_END
break; } } void de_3b_state::machine_reset() { } void de_3b_state::init_de_3b() { } MACHINE_CONFIG_START(de_3b_state::de_3b) /* basic machine hardware */ MCFG_DECOCPU_TYPE3B_ADD("decocpu",XTAL(8'000'000) / 2, ":maincpu") MCFG_DECOCPU_DISPLAY(READ8(*this, de_3b_state,display_r),WRITE8(*this, de_3b_state,display_w)) MCFG_DECOCPU_SOUNDLATCH(WRITE8(*this, de_3b_state,sound_w)) MCFG_DECOCPU_SWITCH(READ8(*this, de_3b_state,switch_r),WRITE8(*this, de_3b_state,switch_w)) MCFG_DECOCPU_LAMP(WRITE8(*this, de_3b_state,lamps_w)) MCFG_DECOCPU_DMDSTATUS(READ8(*this, de_3b_state,dmd_status_r)) genpin_audio(config); /* sound hardware */ MCFG_DECOBSMT_ADD(DECOBSMT_TAG) MCFG_DECODMD_TYPE3_ADD("decodmd",":cpu3") MACHINE_CONFIG_END MACHINE_CONFIG_START(de_3b_state::detest)
{ } MACHINE_CONFIG_START(ron_state::ron) /* basic machine hardware */ MCFG_DEVICE_ADD("maincpu", Z80, MAIN_CLOCK) MCFG_DEVICE_PROGRAM_MAP(ron_map) MCFG_DEVICE_IO_MAP(ron_io) MCFG_DEVICE_ADD("audiocpu", I8035, SOUND_CLOCK) MCFG_DEVICE_PROGRAM_MAP(ron_audio_map) MCFG_DEVICE_IO_MAP(ron_audio_io) MCFG_MCS48_PORT_T0_CLK_DEVICE("aysnd") MCFG_MCS48_PORT_P2_IN_CB(READ8(*this, ron_state, audio_cmd_r)) MCFG_MCS48_PORT_P1_OUT_CB(WRITE8(*this, ron_state, audio_p1_w)) MCFG_MCS48_PORT_P2_OUT_CB(WRITE8(*this, ron_state, audio_p2_w)) MCFG_MCS48_PORT_T1_IN_CB(READLINE(*this, ron_state, audio_T1_r)) /* video hardware */ MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_UPDATE_DRIVER(ron_state, screen_update) MCFG_SCREEN_RAW_PARAMS(VIDEO_CLOCK, 320, 0, 256, 264, 0, 240) MCFG_SCREEN_PALETTE("palette") MCFG_SCREEN_VBLANK_CALLBACK(WRITELINE(*this, ron_state, vblank_irq)) MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_ron) MCFG_PALETTE_ADD("palette", 8) //MCFG_PALETTE_ADD("palette", 512) //MCFG_PALETTE_INDIRECT_ENTRIES(32)
, m_rxd_cb(*this) , m_txd(1U) , m_bus(0U) { } tiny_rom_entry const *kaypro_10_keyboard_device::device_rom_region() const { return ROM_NAME(kaypro_10_keyboard); } MACHINE_CONFIG_START(kaypro_10_keyboard_device::device_add_mconfig) MCFG_DEVICE_ADD("mcu", I8049, 6_MHz_XTAL) MCFG_MCS48_PORT_P1_IN_CB(READ8(*this, kaypro_10_keyboard_device, p1_r)) MCFG_MCS48_PORT_P2_IN_CB(READ8(*this, kaypro_10_keyboard_device, p2_r)) MCFG_MCS48_PORT_P2_OUT_CB(WRITE8(*this, kaypro_10_keyboard_device, p2_w)) MCFG_MCS48_PORT_T1_IN_CB(READLINE(*this, kaypro_10_keyboard_device, t1_r)) MCFG_MCS48_PORT_BUS_IN_CB(READ8(*this, kaypro_10_keyboard_device, bus_r)) MCFG_MCS48_PORT_BUS_OUT_CB(WRITE8(*this, kaypro_10_keyboard_device, bus_w)) SPEAKER(config, "keyboard").front_center(); MCFG_DEVICE_ADD("bell", SPEAKER_SOUND) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "keyboard", 0.25) MACHINE_CONFIG_END ioport_constructor kaypro_10_keyboard_device::device_input_ports() const { (void)&INPUT_PORTS_NAME(kaypro_keyboard_bitshift); return INPUT_PORTS_NAME(kaypro_keyboard_typewriter); }
MCFG_HUC6260_TIME_TIL_NEXT_EVENT_CB(READ16("huc6202", huc6202_device, time_until_next_event)) MCFG_HUC6260_VSYNC_CHANGED_CB(WRITELINE("huc6202", huc6202_device, vsync_changed)) MCFG_HUC6260_HSYNC_CHANGED_CB(WRITELINE("huc6202", huc6202_device, hsync_changed)) MCFG_DEVICE_ADD( "huc6270_0", HUC6270, 0 ) MCFG_HUC6270_VRAM_SIZE(0x10000) MCFG_HUC6270_IRQ_CHANGED_CB(INPUTLINE("maincpu", 0)) MCFG_DEVICE_ADD( "huc6270_1", HUC6270, 0 ) MCFG_HUC6270_VRAM_SIZE(0x10000) MCFG_HUC6270_IRQ_CHANGED_CB(INPUTLINE("maincpu", 0)) MCFG_DEVICE_ADD( "huc6202", HUC6202, 0 ) MCFG_HUC6202_NEXT_PIXEL_0_CB(READ16("huc6270_0", huc6270_device, next_pixel)) MCFG_HUC6202_TIME_TIL_NEXT_EVENT_0_CB(READ16("huc6270_0", huc6270_device, time_until_next_event)) MCFG_HUC6202_VSYNC_CHANGED_0_CB(WRITELINE("huc6270_0", huc6270_device, vsync_changed)) MCFG_HUC6202_HSYNC_CHANGED_0_CB(WRITELINE("huc6270_0", huc6270_device, hsync_changed)) MCFG_HUC6202_READ_0_CB(READ8("huc6270_0", huc6270_device, read)) MCFG_HUC6202_WRITE_0_CB(WRITE8("huc6270_0", huc6270_device, write)) MCFG_HUC6202_NEXT_PIXEL_1_CB(READ16("huc6270_1", huc6270_device, next_pixel)) MCFG_HUC6202_TIME_TIL_NEXT_EVENT_1_CB(READ16("huc6270_1", huc6270_device, time_until_next_event)) MCFG_HUC6202_VSYNC_CHANGED_1_CB(WRITELINE("huc6270_1", huc6270_device, vsync_changed)) MCFG_HUC6202_HSYNC_CHANGED_1_CB(WRITELINE("huc6270_1", huc6270_device, hsync_changed)) MCFG_HUC6202_READ_1_CB(READ8("huc6270_1", huc6270_device, read)) MCFG_HUC6202_WRITE_1_CB(WRITE8("huc6270_1", huc6270_device, write)) MCFG_DEVICE_ADD("rtc", MSM6242, XTAL(32'768)) SPEAKER(config, "lspeaker").front_left(); SPEAKER(config, "rspeaker").front_right(); MCFG_DEVICE_ADD("oki", OKIM6295, PCE_MAIN_CLOCK/12, okim6295_device::PIN7_HIGH) /* unknown clock / pin 7 */ MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.00) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.00)
//------------------------------------------------- const tiny_rom_entry *abc800_keyboard_device::device_rom_region() const { return ROM_NAME( abc800_keyboard ); } //------------------------------------------------- // device_add_mconfig - add device configuration //------------------------------------------------- MACHINE_CONFIG_START(abc800_keyboard_device::device_add_mconfig) MCFG_DEVICE_ADD(I8048_TAG, I8048, XTAL(5'990'400)) MCFG_MCS48_PORT_P1_IN_CB(READ8(*this, abc800_keyboard_device, kb_p1_r)) MCFG_MCS48_PORT_P1_OUT_CB(WRITE8(*this, abc800_keyboard_device, kb_p1_w)) MCFG_MCS48_PORT_P2_OUT_CB(WRITE8(*this, abc800_keyboard_device, kb_p2_w)) MCFG_MCS48_PORT_T1_IN_CB(READLINE(*this, abc800_keyboard_device, kb_t1_r)) MACHINE_CONFIG_END //------------------------------------------------- // INPUT_PORTS( abc800_keyboard ) //------------------------------------------------- INPUT_PORTS_START( abc800_keyboard ) PORT_START("X0") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!') PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("CAPS LOCK") PORT_CODE(KEYCODE_CAPSLOCK) PORT_CHAR(UCHAR_MAMEKEY(CAPSLOCK)) PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("CTRL") PORT_CODE(KEYCODE_LCONTROL) PORT_CHAR(UCHAR_MAMEKEY(LCONTROL)) PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Left SHIFT") PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
MACHINE_CONFIG_START(votrpss_state::votrpss) /* basic machine hardware */ MCFG_DEVICE_ADD("maincpu", Z80, XTAL(8'000'000)/2) /* 4.000 MHz, verified */ MCFG_DEVICE_PROGRAM_MAP(votrpss_mem) MCFG_DEVICE_IO_MAP(votrpss_io) MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(votrpss_state,irq_ack) /* video hardware */ //config.set_default_layout(layout_votrpss); /* sound hardware */ SPEAKER(config, "mono").front_center(); MCFG_DEVICE_ADD("ay", AY8910, XTAL(8'000'000)/4) /* 2.000 MHz, verified */ MCFG_AY8910_PORT_B_READ_CB(IOPORT("DSW1")) // port B read MCFG_AY8910_PORT_A_WRITE_CB(WRITE8("votrax", votrax_sc01_device, write)) // port A write MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25) MCFG_DEVICE_ADD("votrax", VOTRAX_SC01, 720000) /* 720 kHz? needs verify */ MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.00) /* Devices */ MCFG_DEVICE_ADD(m_terminal, GENERIC_TERMINAL, 0) MCFG_GENERIC_TERMINAL_KEYBOARD_CB(PUT(votrpss_state, kbd_put)) i8251_device &uart(I8251(config, "uart", 0)); uart.txd_handler().set("rs232", FUNC(rs232_port_device::write_txd)); uart.dtr_handler().set("rs232", FUNC(rs232_port_device::write_dtr)); uart.rts_handler().set("rs232", FUNC(rs232_port_device::write_rts)); // when serial is chosen, and you select terminal, nothing shows (by design). You can only type commands in. rs232_port_device &rs232(RS232_PORT(config, "rs232", default_rs232_devices, nullptr));
m_T1_line = 0; m_nmi_enable = 0; m_irq_enable = 0; } MACHINE_CONFIG_START(finalizr_state::finalizr) /* basic machine hardware */ MCFG_DEVICE_ADD("maincpu", KONAMI1, XTAL(18'432'000)/6) /* ??? */ MCFG_DEVICE_PROGRAM_MAP(main_map) MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", finalizr_state, finalizr_scanline, "screen", 0, 1) MCFG_DEVICE_ADD("audiocpu", I8039,XTAL(18'432'000)/2) /* 9.216MHz clkin ?? */ MCFG_DEVICE_PROGRAM_MAP(sound_map) MCFG_DEVICE_IO_MAP(sound_io_map) MCFG_MCS48_PORT_P1_OUT_CB(WRITE8("dac", dac_byte_interface, data_w)) MCFG_MCS48_PORT_P2_OUT_CB(WRITE8(*this, finalizr_state, i8039_irqen_w)) //MCFG_MCS48_PORT_T0_CLK_CUSTOM(finalizr_state, i8039_T0_w) MCFG_MCS48_PORT_T1_IN_CB(READLINE(*this, finalizr_state, i8039_T1_r)) WATCHDOG_TIMER(config, "watchdog"); /* video hardware */ MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_REFRESH_RATE(60) MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */) MCFG_SCREEN_SIZE(36*8, 32*8) MCFG_SCREEN_VISIBLE_AREA(1*8, 35*8-1, 2*8, 30*8-1) MCFG_SCREEN_UPDATE_DRIVER(finalizr_state, screen_update_finalizr) MCFG_SCREEN_PALETTE("palette")
static void HandleMemSingle( data32_t insn ) { data32_t rn, rnv, off, rd; /* Fetch the offset */ if (insn & INSN_I) { off = decodeShift(insn, NULL); } else { off = insn & INSN_SDT_IMM; } /* Calculate Rn, accounting for PC */ rn = (insn & INSN_RN) >> INSN_RN_SHIFT; // if (rn==0xf) logerror("%08x: Source R15\n",R15); if (insn & INSN_SDT_P) { /* Pre-indexed addressing */ if (insn & INSN_SDT_U) { rnv = (GetRegister(rn) + off); } else { rnv = (GetRegister(rn) - off); } if (insn & INSN_SDT_W) { SetRegister(rn,rnv); //check writeback??? } else if (rn == eR15) { rnv = (rnv & ADDRESS_MASK) + 8; } } else { /* Post-indexed addressing */ if (rn == eR15) { rnv = (R15 & ADDRESS_MASK) + 8; } else { rnv = GetRegister(rn); } } /* Do the transfer */ rd = (insn & INSN_RD) >> INSN_RD_SHIFT; if (insn & INSN_SDT_L) { /* Load */ if (insn & INSN_SDT_B) { SetRegister(rd,(data32_t) READ8(rnv)); } else { if (rd == eR15) { if (ARM_DEBUG_CORE) logerror("%08x: LDR to R15\n",R15); R15 = (READ32(rnv) & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & MODE_MASK); R15 -= 4; } else { SetRegister(rd,READ32(rnv)); } } } else { /* Store */ if (insn & INSN_SDT_B) { if (ARM_DEBUG_CORE && rd==eR15) logerror("Wrote R15 in byte mode\n"); WRITE8(rnv, (data8_t) GetRegister(rd) & 0xffu); } else { if (ARM_DEBUG_CORE && rd==eR15) logerror("Wrote R15 in 32bit mode\n"); WRITE32(rnv, rd == eR15 ? R15 + 8 : GetRegister(rd)); } } /* Do post-indexing writeback */ if (!(insn & INSN_SDT_P)/* && (insn&INSN_SDT_W)*/) { if (insn & INSN_SDT_U) { /* Writeback is applied in pipeline, before value is read from mem, so writeback is effectively ignored */ if (rd==rn) { SetRegister(rn,GetRegister(rd)); //todo: check for offs... ? } else { if ((insn&INSN_SDT_W)!=0) logerror("%08x: RegisterWritebackIncrement %d %d %d\n",R15,(insn & INSN_SDT_P)!=0,(insn&INSN_SDT_W)!=0,(insn & INSN_SDT_U)!=0); SetRegister(rn,(rnv + off)); } } else { /* Writeback is applied in pipeline, before value is read from mem, so writeback is effectively ignored */ if (rd==rn) { SetRegister(rn,GetRegister(rd)); // logerror("Arm %08x: LDR style with rn==rn\n",R15); } else { SetRegister(rn,(rnv - off)); if ((insn&INSN_SDT_W)!=0) logerror("%08x: RegisterWritebackDecrement %d %d %d\n",R15,(insn & INSN_SDT_P)!=0,(insn&INSN_SDT_W)!=0,(insn & INSN_SDT_U)!=0); } } } // arm_check_irq_state() } /* HandleMemSingle */
m_bus->srq_w(BIT(data, 1)); m_exrom = !BIT(data, 3); m_roml_sel = BIT(data, 4); } //------------------------------------------------- // device_add_mconfig - add device configuration //------------------------------------------------- MACHINE_CONFIG_START(c64_ieee488_device::device_add_mconfig) MCFG_DEVICE_ADD(MOS6525_TAG, TPI6525, 0) MCFG_TPI6525_IN_PA_CB(READ8(*this, c64_ieee488_device, tpi_pa_r)) MCFG_TPI6525_OUT_PA_CB(WRITE8(*this, c64_ieee488_device, tpi_pa_w)) MCFG_TPI6525_IN_PB_CB(READ8(IEEE488_TAG, ieee488_device, dio_r)) MCFG_TPI6525_OUT_PB_CB(WRITE8(IEEE488_TAG, ieee488_device, dio_w)) MCFG_TPI6525_IN_PC_CB(READ8(*this, c64_ieee488_device, tpi_pc_r)) MCFG_TPI6525_OUT_PC_CB(WRITE8(*this, c64_ieee488_device, tpi_pc_w)) MCFG_CBM_IEEE488_ADD(nullptr) MCFG_C64_PASSTHRU_EXPANSION_SLOT_ADD() MACHINE_CONFIG_END //************************************************************************** // LIVE DEVICE //**************************************************************************