VOID __SoraHwTxUnsafeNoWait ( PSORA_RADIO pRadio, PTX_DESC pTxDesc) #endif { __REG32_TX_CTRL TXControl; #ifdef DEBUG_CHECKSUM WRITE_REGISTER_ULONG( (PULONG)&pRadio->__ctrl_reg.pRadioRegs->TXChecksum, Checksum); #endif WRITE_REGISTER_ULONG( (PULONG)&pRadio->__ctrl_reg.pRadioRegs->TXAddr, pTxDesc->__RCBDestAddr); WRITE_REGISTER_ULONG( (PULONG)&pRadio->__ctrl_reg.pRadioRegs->TXSize, pTxDesc->Size); TXControl.Value = 0; TXControl.Bits.TXInit = 1; WRITE_REGISTER_ULONG( (PULONG)&pRadio->__ctrl_reg.pRadioRegs->TXControl, TXControl.Value); }
VOID __SoraHwTransferUnsafeNoWait( IN PTRANSFER_OBJ pTransferObj, IN PTX_DESC pTxDesc) #endif { HRESULT hr = S_OK; __REG32_TRANS_CTRL TransCtrl; __PSORA_RADIO_REGS pRegs = pTransferObj->TransferReg; pTxDesc->__FrameCtrlOwn = 1; //software own the buffer // make sure modulation buffer is flushed into memory. _mm_mfence(); TransCtrl.Value = 0; TransCtrl.Bits.TransferInit = 1; #ifdef DEBUG_CHECKSUM WRITE_REGISTER_ULONG( (PULONG)&pRegs->TransferChecksum, Checksum); #endif WRITE_REGISTER_ULONG( (PULONG)&pRegs->TransferSrcAddrL, pTxDesc->ThisPa.u.LowPart); WRITE_REGISTER_ULONG( (PULONG)&pRegs->TransferSrcAddrH, pTxDesc->ThisPa.u.HighPart); WRITE_REGISTER_ULONG( (PULONG)&pRegs->TransferControl, TransCtrl.Value); }
VOID HalpInitializeClock(VOID) { PKIPCR Pcr = (PKIPCR)KeGetPcr(); ULONG ClockInterval; SP804_CONTROL_REGISTER ControlRegister; /* Setup the clock and profile interrupt */ Pcr->InterruptRoutine[CLOCK2_LEVEL] = HalpStallInterrupt; /* * Configure the interval to 10ms * (INTERVAL (10ms) * TIMCLKfreq (1MHz)) * --------------------------------------- == 10^4 * (TIMCLKENXdiv (1) * PRESCALEdiv (1)) */ ClockInterval = 0x2710; /* Configure the timer */ ControlRegister.AsUlong = 0; ControlRegister.Wide = TRUE; ControlRegister.Periodic = TRUE; ControlRegister.Interrupt = TRUE; ControlRegister.Enabled = TRUE; /* Enable the timer */ WRITE_REGISTER_ULONG(TIMER0_LOAD, ClockInterval); WRITE_REGISTER_ULONG(TIMER0_CONTROL, ControlRegister.AsUlong); }
VOID NTAPI LlbHwVersaUartInitialize(VOID) { ULONG Divider, Remainder, Fraction, ClockRate, Baudrate; /* Query peripheral rate, hardcore baudrate */ ClockRate = LlbHwGetPClk(); Baudrate = 115200; /* Calculate baudrate clock divider and remainder */ Divider = ClockRate / (16 * Baudrate); Remainder = ClockRate % (16 * Baudrate); /* Calculate the fractional part */ Fraction = (8 * Remainder / Baudrate) >> 1; Fraction += (8 * Remainder / Baudrate) & 1; /* Disable interrupts */ WRITE_REGISTER_ULONG(UART_PL011_CR, 0); /* Set the baud rate to 115200 bps */ WRITE_REGISTER_ULONG(UART_PL011_IBRD, Divider); WRITE_REGISTER_ULONG(UART_PL011_FBRD, Fraction); /* Set 8 bits for data, 1 stop bit, no parity, FIFO enabled */ WRITE_REGISTER_ULONG(UART_PL011_LCRH, UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN); /* Clear and enable FIFO */ WRITE_REGISTER_ULONG(UART_PL011_CR, UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE); }
VOID XenGfxChangeXgfxMode(PXENGFX_DEVICE_EXTENSION pXenGfxExtension, BOOLEAN Enable) { ULONG ControlReg; if ((Enable)&&(!pXenGfxExtension->XgfxMode)) { ControlReg = READ_REGISTER_ULONG((PULONG)(pXenGfxExtension->pGlobalRegs + XGFX_CONTROL)); // Enable XGFX hires mode and endable interrupts. ControlReg |= XGFX_CONTROL_INT_EN|XGFX_CONTROL_HIRES_EN; WRITE_REGISTER_ULONG((PULONG)(pXenGfxExtension->pGlobalRegs + XGFX_CONTROL), ControlReg); pXenGfxExtension->XgfxMode = TRUE; } else if ((!Enable)&&(pXenGfxExtension->XgfxMode)) { ControlReg = READ_REGISTER_ULONG((PULONG)(pXenGfxExtension->pGlobalRegs + XGFX_CONTROL)); // Disable XGFX mode ControlReg &= ~(XGFX_CONTROL_INT_EN|XGFX_CONTROL_HIRES_EN); WRITE_REGISTER_ULONG((PULONG)(pXenGfxExtension->pGlobalRegs + XGFX_CONTROL), ControlReg); pXenGfxExtension->XgfxMode = FALSE; } }
USHORT CHalWaveDevice::TransferAudio( PVOID pvLeft, PVOID pvRight, ULONG ulSamplesToTransfer, LONG lPCIndex ) // ASIO Version, Sample Format will always be 32-bit Stereo ///////////////////////////////////////////////////////////////////////////// { PULONG pHWBuffer = (PULONG)m_pAudioBuffer; LONG lLSample = 0, lRSample = 0; // are we overriding the PCIndex if( lPCIndex != -1 ) m_lPCIndex = lPCIndex; m_ulBytesTransferred += (ulSamplesToTransfer * sizeof( DWORD ) * 2); m_ulSamplesTransferred += ulSamplesToTransfer; if( m_bIsRecord ) { register PLONG pLDst = (PLONG)pvLeft; register PLONG pRDst = (PLONG)pvRight; //DC('r'); DX16( (USHORT)ulSamplesToTransfer, COLOR_NORMAL ); DC(' '); while( ulSamplesToTransfer-- ) { lLSample = READ_REGISTER_ULONG( &pHWBuffer[ m_lPCIndex++ ] ); lRSample = READ_REGISTER_ULONG( &pHWBuffer[ m_lPCIndex++ ] ); if( m_lPCIndex >= WAVE_CIRCULAR_BUFFER_SIZE ) m_lPCIndex = 0; if( pLDst ) *pLDst++ = lLSample; if( pRDst ) *pRDst++ = lRSample; } // while } else { register PLONG pLSrc = (PLONG)pvLeft; register PLONG pRSrc = (PLONG)pvRight; //DC('p'); DX16( (USHORT)ulSamplesToTransfer, COLOR_NORMAL ); DC(' '); while( ulSamplesToTransfer-- ) { if( pLSrc ) lLSample = *pLSrc++; if( pRSrc ) lRSample = *pRSrc++; WRITE_REGISTER_ULONG( &pHWBuffer[ m_lPCIndex++ ], lLSample ); // Left Channel WRITE_REGISTER_ULONG( &pHWBuffer[ m_lPCIndex++ ], lRSample ); // Right Channel if( m_lPCIndex >= WAVE_CIRCULAR_BUFFER_SIZE ) m_lPCIndex = 0; } // while } if( m_lPCIndex >= WAVE_CIRCULAR_BUFFER_SIZE ) m_lPCIndex -= WAVE_CIRCULAR_BUFFER_SIZE; // Write the PCIndex to the hardware //DC('{'); DX16( (USHORT)m_lPCIndex, COLOR_BOLD ); DC('}'); m_RegStreamControl.Write( (REG_STREAMCTL_XFERDONE | m_lPCIndex), (REG_STREAMCTL_XFERDONE | REG_STREAMCTL_PCPTR_MASK) ); //DPF(("h%ld p%ld ", m_RegStreamStatus.Read() & REG_STREAMSTAT_L2PTR_MASK, m_lPCIndex )); return( HSTATUS_OK ); }
void SoraHwSetTxBufferRegs(PSORA_RADIO pRadio, PPACKET_BASE pPacket) { WRITE_REGISTER_ULONG( (PULONG)&pRadio->__ctrl_reg.pRadioRegs->TXAddr, pPacket->pTxDesc->__RCBDestAddr); WRITE_REGISTER_ULONG( (PULONG)&pRadio->__ctrl_reg.pRadioRegs->TXSize, pPacket->pTxDesc->Size); }
VOID PLxHardwareReset( IN PDEVICE_EXTENSION DevExt ) /*++ Routine Description: Called by D0Exit when the device is being disabled or when the system is shutdown to put the device in a known initial state. Arguments: DevExt Pointer to Device Extension Return Value: --*/ { LARGE_INTEGER delay; union { EEPROM_CSR bits; ULONG ulong; } eeCSR; TraceEvents(TRACE_LEVEL_INFORMATION, DBG_PNP, "--> PLxIssueFullReset"); // // Drive the 9656 into soft reset. // eeCSR.ulong = READ_REGISTER_ULONG( (PULONG) &DevExt->Regs->EEPROM_Ctrl_Stat ); eeCSR.bits.SoftwareReset = TRUE; WRITE_REGISTER_ULONG( (PULONG) &DevExt->Regs->EEPROM_Ctrl_Stat, eeCSR.ulong ); // // Wait 100 msec. // delay.QuadPart = WDF_REL_TIMEOUT_IN_MS(100); KeDelayExecutionThread( KernelMode, TRUE, &delay ); // // Finally pull the 9656 out of reset. // eeCSR.bits.SoftwareReset = FALSE; WRITE_REGISTER_ULONG( (PULONG) &DevExt->Regs->EEPROM_Ctrl_Stat, eeCSR.ulong ); TraceEvents(TRACE_LEVEL_INFORMATION, DBG_PNP, "<-- PLxIssueFullReset"); }
BOOLEAN NTAPI KdPortInitializeEx(IN PCPPORT PortInformation, IN ULONG ComPortNumber) { ULONG Divider, Remainder, Fraction; ULONG Baudrate = PortInformation->BaudRate; // // Calculate baudrate clock divider and remainder // Divider = HACK / (16 * Baudrate); Remainder = HACK % (16 * Baudrate); // // Calculate the fractional part // Fraction = (8 * Remainder / Baudrate) >> 1; Fraction += (8 * Remainder / Baudrate) & 1; // // Disable interrupts // WRITE_REGISTER_ULONG((PULONG)UART_PL011_CR, 0); // // Set the baud rate // WRITE_REGISTER_ULONG((PULONG)UART_PL011_IBRD, Divider); WRITE_REGISTER_ULONG((PULONG)UART_PL011_FBRD, Fraction); // // Set 8 bits for data, 1 stop bit, no parity, FIFO enabled // WRITE_REGISTER_ULONG((PULONG)UART_PL011_LCRH, UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN); // // Clear and enable FIFO // WRITE_REGISTER_ULONG((PULONG)UART_PL011_CR, UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE); // // Done // return TRUE; }
/*++ __SORA_HW_ENROLL_RX_BUFFER_UNSAFE notify hardware the physical address and size of RX DMA buffer. --*/ void __SORA_HW_ENROLL_RX_BUFFER_UNSAFE(PSORA_RADIO pRadio) { ASSERT(SORA_RADIO_WELL_CONFIGED2(pRadio)); WRITE_REGISTER_ULONG( (PULONG)&pRadio->__ctrl_reg.pRadioRegs->RXBufAddrL, SORA_GET_RX_DMA_BUFFER_PADDRESSLO(SORA_GET_RX_QUEUE(pRadio))); WRITE_REGISTER_ULONG( (PULONG)&pRadio->__ctrl_reg.pRadioRegs->RXBufAddrH, SORA_GET_RX_DMA_BUFFER_PADDRESSHI(SORA_GET_RX_QUEUE(pRadio))); WRITE_REGISTER_ULONG( (PULONG)&pRadio->__ctrl_reg.pRadioRegs->RXBufSize, SORA_GET_RX_DMA_BUFFER_SIZE(SORA_GET_RX_QUEUE(pRadio))); }
NTSTATUS PLxInitRead( IN PDEVICE_EXTENSION DevExt ) /*++ Routine Description: Initialize read data structures Arguments: DevExt Pointer to Device Extension Return Value: --*/ { TraceEvents(TRACE_LEVEL_INFORMATION, DBG_PNP, "--> PLxInitRead"); // // Make sure the DMA Chan 1 DAC (Dual Address Cycle) is set to 0. // WRITE_REGISTER_ULONG( (PULONG) &DevExt->Regs->Dma1_PCI_DAC, 0 ); // // Clear the saved copy of the DMA Channel 1's CSR // DevExt->Dma1Csr.uchar = 0; TraceEvents(TRACE_LEVEL_INFORMATION, DBG_PNP, "<-- PLxInitRead"); return STATUS_SUCCESS; }
VOID NTAPI LlbHwUartSendChar(IN CHAR Char) { /* Send the character */ WRITE_REGISTER_ULONG(UART_PL01x_DR, Char); }
VOID ScsiPortWriteRegisterUlong( IN PULONG Register, IN ULONG Value ) /*++ Routine Description: Write to the specificed register address. Arguments: Register - Supplies a pointer to the register address. Value - Supplies the value to be written. Return Value: None --*/ { WRITE_REGISTER_ULONG(Register, Value); }
VOID NTAPI VideoPortWriteRegisterUlong( PULONG Register, ULONG Value) { WRITE_REGISTER_ULONG(Register, Value); }
void CHalRegister::Write( ULONG ulValue ) ///////////////////////////////////////////////////////////////////////////// { m_ulValue = ulValue; if( m_ulType != REG_READONLY ) WRITE_REGISTER_ULONG( m_pAddress, m_ulValue ); }
HRESULT MixedRxTf(PSORA_RADIO pRadio) { __REG32_TRANS_CTRL TransCtrl; __PSORA_RADIO_REGS pRegs = pRadio->__ctrl_reg.pRadioRegs; ULONG uTemp = 100000; pPhyFrameDesc->__FrameCtrlOwn = 1; //software own the phy frame TransCtrl.Value = 0; TransCtrl.Bits.TransferInit = 1; WRITE_REGISTER_ULONG( (PULONG)&pRegs->TransferSrcAddrL, pPhyFrameDesc->ThisPa.u.LowPart); WRITE_REGISTER_ULONG( (PULONG)&pRegs->TransferSrcAddrH, pPhyFrameDesc->ThisPa.u.HighPart); WRITE_REGISTER_ULONG( (PULONG)&pRegs->TransferControl, TransCtrl.Value); while(pPhyFrameDesc->__FrameCtrlOwn == 1) //wait until hw owns the phy frame //hw will set it if TXDone. PHY frame desc is in MmWriteCombined mem, so not cached. { { __REG32_RX_CTRL RXControl; RXControl.Value = 0; RXControl.Bits.RXEnable = 1; WRITE_REGISTER_ULONG( (PULONG)&pRadio->__phy_reg_manager.pRadioRegs->RXControl, RXControl.Value); pRadio->__fRxEnabled = TRUE; } uTemp--; if(uTemp < 1) { KdPrint(("Wait Own Timeout!")); hr = E_TX_TRANSFER_FAIL; break; } _mm_pause(); } TransCtrl.Value = 0; WRITE_REGISTER_ULONG((PULONG)&pRegs->TransferControl, TransCtrl.Value); //clear init bit return hr; }
void io_write(struct fscc_card *card, unsigned bar, PULONG Address, ULONG Value) { if (card->bar[bar].memory_mapped) WRITE_REGISTER_ULONG(Address, Value); else WRITE_PORT_ULONG(Address, Value); }
VOID NTAPI ScsiPortWriteRegisterUlong( IN PULONG Register, IN ULONG Value) { WRITE_REGISTER_ULONG(Register, Value); }
VOID __SoraHwStop(PSORA_RADIO pRadio) { KIRQL OldIrql; KeAcquireSpinLock(&pRadio->__HWOpLock, &OldIrql); WRITE_REGISTER_ULONG( (PULONG)(&((__PSORA_REGISTERS)pRadio->__ctrl_reg.pSoraSysRegs)->HWControl), 0x01); KeReleaseSpinLock(&pRadio->__HWOpLock, OldIrql); }
ULONG HWREG<ULONG>::Write( _In_ ULONG Value ) { volatile ULONG *addr = &m_Value; WRITE_REGISTER_ULONG((PULONG)addr, Value); return Value; }
/* * @implemented */ VOID NTAPI KeStallExecutionProcessor(IN ULONG Microseconds) { SP804_CONTROL_REGISTER ControlRegister; /* Enable the timer */ WRITE_REGISTER_ULONG(TIMER1_LOAD, Microseconds); /* Configure the timer */ ControlRegister.AsUlong = 0; ControlRegister.OneShot = TRUE; ControlRegister.Wide = TRUE; ControlRegister.Periodic = TRUE; ControlRegister.Enabled = TRUE; WRITE_REGISTER_ULONG(TIMER1_CONTROL, ControlRegister.AsUlong); /* Now we will loop until the timer reached 0 */ while (READ_REGISTER_ULONG(TIMER1_VALUE)); }
HRESULT SoraHwSyncTx(PSORA_RADIO pRadio, ULONG mask) { __REG32_TX_CTRL TXControl; HRESULT hr; TXControl.Value = 0; TXControl.Bits.TXInit = 1; TXControl.Bits.TXMask = mask; WRITE_REGISTER_ULONG( (PULONG)&pRadio->__ctrl_reg.pRadioRegs->TXControl, TXControl.Value); hr = __SoraHwWaitTxDone(pRadio); TXControl.Value = 0; TXControl.Bits.TXInit = 0; WRITE_REGISTER_ULONG( (PULONG)&pRadio->__ctrl_reg.pRadioRegs->TXControl, TXControl.Value); return hr; }
VOID vWriteFifoD( VOID* p, ULONG v) { gcFifo--; if (gcFifo < 0) { gcFifo = 0; RIP("Incorrect FIFO wait count"); } WRITE_REGISTER_ULONG(p, v); }
VOID NTAPI KdPortPutByteEx(IN PCPPORT PortInformation, IN UCHAR ByteToSend) { // // Wait for ready // while ((READ_REGISTER_ULONG((PULONG)UART_PL01x_FR) & UART_PL01x_FR_TXFF) != 0); // // Send the character // WRITE_REGISTER_ULONG((PULONG)UART_PL01x_DR, ByteToSend); }
VOID HalpClockInterrupt(VOID) { /* Clear the interrupt */ ASSERT(KeGetCurrentIrql() == CLOCK2_LEVEL); WRITE_REGISTER_ULONG(TIMER0_INT_CLEAR, 1); /* FIXME: Update HAL Perf counters */ /* FIXME: Check if someone changed the clockrate */ /* Call the kernel */ KeUpdateSystemTime(KeGetCurrentThread()->TrapFrame, HalpCurrentTimeIncrement, CLOCK2_LEVEL); }
/*++ SORA_HW_ENABLE_RX enable radio to start RX and write samples into RX buffer from previous write point. --*/ VOID SORAAPI SORA_HW_ENABLE_RX(PSORA_RADIO pRadio) { __REG32_RX_CTRL RXControl; KIRQL OldIrql; RXControl.Value = 0; RXControl.Bits.RXEnable = 1; KeAcquireSpinLock(&pRadio->__HWOpLock, &OldIrql); WRITE_REGISTER_ULONG( (PULONG)&pRadio->__ctrl_reg.pRadioRegs->RXControl, RXControl.Value); KeReleaseSpinLock(&pRadio->__HWOpLock, OldIrql); pRadio->__fRxEnabled = TRUE; }
VOID HalpUnmapNvram ( IN PENTRYLO SavedPte, IN KIRQL OldIrql ) /*++ Routine Description: This function is called to unmap the NVRAM from the address space of the current process. Arguments: SavedPte - Supplies a pointer to an array which contains the old NVRAM PTE values. OldIrql - Supplies the previous IRQL value. Return Value: None. --*/ { #if 0 // N.B For Driver. // // // Set nvram write protect // WRITE_REGISTER_ULONG( (PULONG)&(COLUMNBS_LCNTL)->STSR ,STSR_NVWINH|STSR_WNVWINH); #endif // // Unmap the NVRAM from the address space of the current process. // KeLowerIrql(OldIrql); return; }
VOID HalRequestIpi ( IN ULONG Mask ) /*++ Routine Description: This routine requests an interprocessor interrupt on a set of processors. N.B. This routine must ensure that the interrupt is posted at the target processor(s) before returning. Arguments: Mask - Supplies the set of processors that are sent an interprocessor interrupt. Return Value: None. --*/ { /* Start M001 */ ULONG buffer; /* End M001 */ // // Request an interprocessor interrupt on each of the specified target // processors. // /* Start M001 */ buffer = HalpIpiIntRequestMask[(Mask & 0xf)] | // S004 ( (((PCR->Prcb)->Number) & 0x3) << IntIR_CODE_BIT ); WRITE_REGISTER_ULONG( &( PMC_CONTROL1 )->IntIR.Long, buffer); // S007 /* End M001 */ return; }
HRESULT __SORA_HW_TX_TRANSFER_UNSAFE( IN HANDLE TransferObj, IN PTX_DESC pTxDesc) #endif { PTRANSFER_OBJ pTransferObj = (PTRANSFER_OBJ)TransferObj; HRESULT hr = S_OK; __REG32_TRANS_CTRL TransCtrl; __PSORA_RADIO_REGS pRegs = pTransferObj->TransferReg; #ifdef DEBUG_CHECKSUM ULONG TransferErrorCount; TransferErrorCount = READ_REGISTER_ULONG((PULONG)&((pRegs->TransferErrorCount))); #endif #ifdef DEBUG_CHECKSUM __SoraHwTransferUnsafeNoWait(pTransferObj, pTxDesc, Checksum); #else __SoraHwTransferUnsafeNoWait(pTransferObj, pTxDesc); #endif hr = __SoraHwWaitTransferDone(pTxDesc); TransCtrl.Value = 0; WRITE_REGISTER_ULONG((PULONG)&pRegs->TransferControl, TransCtrl.Value); //clear init bit #ifdef DEBUG_CHECKSUM if (SUCCEEDED(hr)) { if (TransferErrorCount != READ_REGISTER_ULONG((PULONG)&((pRegs->TransferErrorCount)))) hr = E_TX_TRANSFER_CHECKSUM_FAIL; } else __SoraHwPrintDbgRegsUnsafe(pTransferObj); #else if (FAILED(hr)) __SoraHwPrintDbgRegsUnsafe(pTransferObj); #endif return hr; }
KIRQL HalpMapNvram ( IN PENTRYLO SavedPte ) /*++ Routine Description: This function is called to map the NVRAM into the address space of the current process. Arguments: SavedPte - Supplies a pointer to an array which receives the old NVRAM PTE values. Return Value: The previous IRQL is returned as the function value. --*/ { KIRQL OldIrql; // // disable nvram Write protection. Set Write Enable // #if 0 // // No Gard. for Driver. Fix. // WRITE_REGISTER_ULONG( (PULONG)&(COLUMNBS_LCNTL)->STSR ,STSR_WNVWINH); #endif KeRaiseIrql(HIGH_LEVEL, &OldIrql); return OldIrql; }