bool Savage_GetEdidInfo(edid1_info& edidInfo) { // Get the EDID info and return true if successful. SharedInfo& si = *gInfo.sharedInfo; uint32 DDCPort = 0; switch (si.chipType) { case S3_SAVAGE_3D: case S3_SAVAGE_MX: case S3_SUPERSAVAGE: case S3_SAVAGE2000: DDCPort = 0xAA; break; case S3_SAVAGE4: case S3_PROSAVAGE: case S3_TWISTER: case S3_PROSAVAGE_DDR: DDCPort = 0xB1; break; } i2c_bus bus; bus.cookie = (void*)DDCPort; bus.set_signals = &SetI2CSignals; bus.get_signals = &GetI2CSignals; ddc2_init_timing(&bus); uint8 tmp = ReadCrtcReg(DDCPort); WriteCrtcReg(DDCPort, tmp | 0x13); bool bResult = (ddc2_read_edid1(&bus, &edidInfo, NULL, NULL) == B_OK); WriteCrtcReg(DDCPort, tmp); return bResult; }
static status_t SetI2CSignals(void* cookie, int _clock, int data) { uint32 index = (uint32)cookie; uint8 value = 0x10; if (_clock) value |= 0x1; if (data) value |= 0x2; WriteCrtcReg(index, value); return B_OK; }
static void Virge_GEReset(const DisplayModeEx& mode) { SharedInfo& si = *gInfo.sharedInfo; if (si.chipType == S3_TRIO_3D) Virge_NopAllCmdSets(); gInfo.WaitIdleEmpty(); if (si.chipType == S3_TRIO_3D) { bool ge_was_on = false; snooze(10000); for (int r = 1; r < 10; r++) { uint8 resetidx = 0x66; VerticalRetraceWait(); uint8 tmp = ReadCrtcReg(resetidx); VerticalRetraceWait(); IN_SUBSYS_STAT(); // turn off the GE if (tmp & 0x01) { WriteCrtcReg(resetidx, tmp); ge_was_on = true; snooze(10000); } IN_SUBSYS_STAT(); WriteCrtcReg(resetidx, tmp | 0x02); snooze(10000); VerticalRetraceWait(); WriteCrtcReg(resetidx, tmp & ~0x02); snooze(10000); if (ge_was_on) { tmp |= 0x01; WriteCrtcReg(resetidx, tmp); snooze(10000); } VerticalRetraceWait(); Virge_NopAllCmdSets(); gInfo.WaitIdleEmpty(); WriteReg32(DEST_SRC_STR, mode.bytesPerRow << 16 | mode.bytesPerRow); snooze(10000); if ((IN_SUBSYS_STAT() & 0x3f802000 & 0x20002000) != 0x20002000) { TRACE("Restarting S3 graphics engine reset %2d ...%lx\n", r, IN_SUBSYS_STAT() ); } else break; } } else { uint8 regIndex = (si.chipType == S3_VIRGE_VX ? 0x63 : 0x66); uint8 tmp = ReadCrtcReg(regIndex); snooze(10000); // try multiple times to avoid lockup of VIRGE/MX for (int r = 1; r < 10; r++) { WriteCrtcReg(regIndex, tmp | 0x02); snooze(10000); WriteCrtcReg(regIndex, tmp & ~0x02); snooze(10000); gInfo.WaitIdleEmpty(); WriteReg32(DEST_SRC_STR, mode.bytesPerRow << 16 | mode.bytesPerRow); snooze(10000); if (((IN_SUBSYS_STAT() & 0x3f00) != 0x3000)) { TRACE("Restarting S3 graphics engine reset %2d ...\n", r); } else break; } } gInfo.WaitQueue(2); WriteReg32(SRC_BASE, 0); WriteReg32(DEST_BASE, 0); gInfo.WaitQueue(4); WriteReg32(CLIP_L_R, ((0) << 16) | mode.timing.h_display); WriteReg32(CLIP_T_B, ((0) << 16) | mode.timing.v_display); WriteReg32(MONO_PAT_0, ~0); WriteReg32(MONO_PAT_1, ~0); if (si.chipType == S3_TRIO_3D) Virge_NopAllCmdSets(); }
static void Virge_WriteMode(const DisplayModeEx& mode, VirgeRegRec& regRec) { // This function writes out all of the standard VGA and extended S3 registers // needed to setup a video mode. TRACE("Virge_WriteMode()\n"); SharedInfo& si = *gInfo.sharedInfo; // First reset GE to make sure nothing is going on. if (ReadCrtcReg(si.chipType == S3_VIRGE_VX ? 0x63 : 0x66) & 0x01) Virge_GEReset(mode); // As per databook, always disable STREAMS before changing modes. if ((ReadCrtcReg(0x67) & 0x0c) == 0x0c) { // STREAMS running, disable it VerticalRetraceWait(); WriteReg32(FIFO_CONTROL_REG, 0xC000); WriteCrtcReg(0x67, 0x00, 0x0c); // disable STREAMS processor } // Restore S3 extended regs. WriteCrtcReg(0x63, regRec.CR63); WriteCrtcReg(0x66, regRec.CR66); WriteCrtcReg(0x3a, regRec.CR3A); WriteCrtcReg(0x31, regRec.CR31); WriteCrtcReg(0x58, regRec.CR58); // Extended mode timings registers. WriteCrtcReg(0x53, regRec.CR53); WriteCrtcReg(0x5d, regRec.CR5D); WriteCrtcReg(0x5e, regRec.CR5E); WriteCrtcReg(0x3b, regRec.CR3B); WriteCrtcReg(0x3c, regRec.CR3C); WriteCrtcReg(0x43, regRec.CR43); WriteCrtcReg(0x65, regRec.CR65); WriteCrtcReg(0x6d, regRec.CR6D); // Restore the desired video mode with CR67. WriteCrtcReg(0x67, 0x50, 0xf0); // possible hardware bug on VX? snooze(10000); WriteCrtcReg(0x67, regRec.CR67 & ~0x0c); // Don't enable STREAMS // Other mode timing and extended regs. WriteCrtcReg(0x34, regRec.CR34); if (si.chipType != S3_TRIO_3D && si.chipType != S3_VIRGE_MX) { WriteCrtcReg(0x40, regRec.CR40); } if (S3_VIRGE_MX_SERIES(si.chipType)) { WriteCrtcReg(0x41, regRec.CR41); } WriteCrtcReg(0x42, regRec.CR42); WriteCrtcReg(0x45, regRec.CR45); WriteCrtcReg(0x51, regRec.CR51); WriteCrtcReg(0x54, regRec.CR54); // Memory timings. WriteCrtcReg(0x68, regRec.CR68); WriteCrtcReg(0x69, regRec.CR69); WriteCrtcReg(0x33, regRec.CR33); if (si.chipType == S3_TRIO_3D_2X || S3_VIRGE_GX2_SERIES(si.chipType) /* MXTESTME */ || S3_VIRGE_MX_SERIES(si.chipType) ) { WriteCrtcReg(0x85, regRec.CR85); } if (si.chipType == S3_VIRGE_DXGX) { WriteCrtcReg(0x86, regRec.CR86); } if ( (si.chipType == S3_VIRGE_GX2) || S3_VIRGE_MX_SERIES(si.chipType) ) { WriteCrtcReg(0x7b, regRec.CR7B); WriteCrtcReg(0x7d, regRec.CR7D); WriteCrtcReg(0x87, regRec.CR87); WriteCrtcReg(0x92, regRec.CR92); WriteCrtcReg(0x93, regRec.CR93); } if (si.chipType == S3_VIRGE_DXGX || S3_VIRGE_GX2_SERIES(si.chipType) || S3_VIRGE_MX_SERIES(si.chipType) || si.chipType == S3_TRIO_3D) { WriteCrtcReg(0x90, regRec.CR90); WriteCrtcReg(0x91, regRec.CR91); } WriteSeqReg(0x08, 0x06); // unlock extended sequencer regs // Restore extended sequencer regs for DCLK. WriteSeqReg(0x12, regRec.SR12); WriteSeqReg(0x13, regRec.SR13); if (S3_VIRGE_GX2_SERIES(si.chipType) || S3_VIRGE_MX_SERIES(si.chipType)) { WriteSeqReg(0x29, regRec.SR29); } if (S3_VIRGE_MX_SERIES(si.chipType)) { WriteSeqReg(0x54, regRec.SR54); WriteSeqReg(0x55, regRec.SR55); WriteSeqReg(0x56, regRec.SR56); WriteSeqReg(0x57, regRec.SR57); } WriteSeqReg(0x18, regRec.SR18); // Load new m,n PLL values for DCLK & MCLK. uint8 tmp = ReadSeqReg(0x15) & ~0x21; WriteSeqReg(0x15, tmp | 0x03); WriteSeqReg(0x15, tmp | 0x23); WriteSeqReg(0x15, tmp | 0x03); WriteSeqReg(0x15, regRec.SR15); if (si.chipType == S3_TRIO_3D) { WriteSeqReg(0x0a, regRec.SR0A); WriteSeqReg(0x0f, regRec.SR0F); } // Now write out CR67 in full, possibly starting STREAMS. VerticalRetraceWait(); WriteCrtcReg(0x67, 0x50); // For possible bug on VX?! snooze(10000); WriteCrtcReg(0x67, regRec.CR67); uint8 cr66 = ReadCrtcReg(0x66); WriteCrtcReg(0x66, cr66 | 0x80); WriteCrtcReg(0x3a, regRec.CR3A | 0x80); // Now, before we continue, check if this mode has the graphic engine ON. // If yes, then we reset it. if (si.chipType == S3_VIRGE_VX) { if (regRec.CR63 & 0x01) Virge_GEReset(mode); } else { if (regRec.CR66 & 0x01) Virge_GEReset(mode); } VerticalRetraceWait(); if (S3_VIRGE_GX2_SERIES(si.chipType) || S3_VIRGE_MX_SERIES(si.chipType) ) { WriteCrtcReg(0x85, 0x1f); // primary stream threshold } // Set the standard CRTC vga regs. WriteCrtcReg(0x11, 0x00, 0x80); // unlock CRTC reg's 0-7 by clearing bit 7 of cr11 for (int j = 0; j < NUM_ELEMENTS(regRec.CRTC); j++) { WriteCrtcReg(j, regRec.CRTC[j]); } // Setup HSYNC & VSYNC polarity and select clock source 2 (0x0c) for // programmable PLL. uint8 miscOutReg = 0x23 | 0x0c; if (!(mode.timing.flags & B_POSITIVE_HSYNC)) miscOutReg |= 0x40; if (!(mode.timing.flags & B_POSITIVE_VSYNC)) miscOutReg |= 0x80; WriteMiscOutReg(miscOutReg); WriteCrtcReg(0x66, cr66); WriteCrtcReg(0x3a, regRec.CR3A); return ; }
status_t Virge_Init(void) { TRACE("Virge_Init()\n"); SharedInfo& si = *gInfo.sharedInfo; // Use PIO for following operations since MMIO may not be currently enabled. WritePIO_8(VGA_ENABLE, ReadPIO_8(VGA_ENABLE) | 0x01); // enable VGA WritePIO_8(MISC_OUT_W, ReadPIO_8(MISC_OUT_R) | 0x01); // enable color // Set linear base register to the PCI register value; // some DX chipsets don't seem to do it automatically. WritePIO_8(CRTC_INDEX, 0x59); WritePIO_8(CRTC_DATA, (uint32)(si.videoMemPCI) >> 24); WritePIO_8(CRTC_INDEX, 0x5A); WritePIO_8(CRTC_DATA, (uint32)(si.videoMemPCI) >> 16); // Enable MMIO. WritePIO_8(CRTC_INDEX, 0x53); WritePIO_8(CRTC_DATA, ReadPIO_8(CRTC_DATA) | 0x8); if (si.chipType == S3_TRIO_3D) WriteCrtcReg(0x40, 0x01, 0x01); // Detect amount of installed ram. uint8 config1 = ReadCrtcReg(0x36); // get amount of vram installed uint8 config2 = ReadCrtcReg(0x37); // get amount of off-screen ram // Compute the amount of video memory and offscreen memory. int ramOffScreenMB = 0; // off screen memory size in megabytes int ramSizeMB = 0; // memory size in megabytes if (si.chipType == S3_VIRGE_VX) { switch ((config2 & 0x60) >> 5) { case 1: ramOffScreenMB = 4; break; case 2: ramOffScreenMB = 2; break; } switch ((config1 & 0x60) >> 5) { case 0: ramSizeMB = 2; break; case 1: ramSizeMB = 4; break; case 2: ramSizeMB = 6; break; case 3: ramSizeMB = 8; break; } ramSizeMB -= ramOffScreenMB; } else if (si.chipType == S3_TRIO_3D_2X) {