int main()
{
/*
* L'adresse de démarrage décodée depuis le fichier S-record n'est pas
* prise en compte, puisque le processeur PowerPC ne peut démarrer qu'à
* l'adresse 0xFFFFFFFC. Une fois le fichier S-record chargé en mémoire,
* on demande au processeur de se reseter pour booter le nouveau programme.
*/
Xuint32 start_address;
XStatus status;
XCache_DisableDCache();
XCache_DisableICache();
print("Starting bootloader.\r\n");
status = load_srec("a:\\boot.me", &start_address);
if (status == XST_SUCCESS)
{
// branchement
print("All right ! Let's go, girls !\r\n\r\n");
usleep(100000);
asm("lis 0,0x3000");
asm("mtdbcr0 0"); // soft reset powaaa !!
}
print("Boot failed.\r\n");
return 0;
}
void
disable_caches()
{
#ifdef __PPC__
XCache_DisableDCache();
XCache_DisableICache();
#elif __MICROBLAZE__
#ifdef XPAR_MICROBLAZE_USE_DCACHE
#if !XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
microblaze_invalidate_dcache();
#endif
microblaze_disable_dcache();
#endif
#ifdef XPAR_MICROBLAZE_USE_ICACHE
microblaze_invalidate_icache();
microblaze_disable_icache();
#endif
#endif
}
int main (void) {
XCache_EnableICache(0x80000001);
XCache_EnableDCache(0x80000000);
/* Initialize RS232 - Set baudrate and number of stop bits */
XUartNs550_SetBaud(XPAR_RS232_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, 9600);
XUartNs550_mSetLineControlReg(XPAR_RS232_BASEADDR, XUN_LCR_8_DATA_BITS);
print("-- Entering main() --\r\n");
/*
* MemoryTest routine will not be run for the memory at
* 0x81000000 (FLASH_8Mx16)
* because it is a read-only memory
*/
/*
* MemoryTest routine will not be run for the memory at
* 0x00000000 (DDR_SDRAM_1)
* because it is being used to hold a part of this application program
*/
/*
* MemoryTest routine will not be run for the memory at
* 0xfffff000 (plb_bram_if_cntlr_1)
* because it is being used to hold a part of this application program
*/
print("-- Exiting main() --\r\n");
XCache_DisableDCache();
XCache_DisableICache();
return 0;
}
int main (void) {
XCache_EnableICache(0x00000001);
XCache_EnableDCache(0x00000001);
XCache_DisableDCache();
XCache_DisableICache();
xil_printf("\r\n-- Entering main() --\r\n");
/************************ SDRAM SelfTest **************************/
xil_printf("Performing SelfTest of SDRAM controller...\r\n");
int iteration = 0;
while(1)
{
xil_printf("*Iteration %d\r\n", iteration++);
int Status;
int i;
volatile a;
volatile b;
int TotalErrors;
Xuint8 dcm_psen, dcm_psincdec, dcm_done;
mySDRAMConfig = XMpmc_LookupConfig(XPAR_MPMC_0_DEVICE_ID);
if(mySDRAMConfig == NULL)
{
xil_printf("Could not find SDRAM based on dev id\r\n");
return XST_FAILURE;
}
else {
xil_printf("Got SDRAM config\r\n");
}
Status = XMpmc_CfgInitialize(&mySDRAM,mySDRAMConfig, XPAR_MPMC_0_MPMC_BASEADDR);
if(Status != XST_SUCCESS) {
xil_printf("Initialization Failed!\r\n");
return XST_FAILURE;
}
else {
xil_printf("Initialization Complete!\r\n");
}
Status = XMpmc_SelfTest(&mySDRAM);
if(Status != XST_SUCCESS) {
xil_printf("SelfTest Failed!\r\n");
return XST_FAILURE;
}
else {
xil_printf("SelfTest Complete!\r\n");
}
/***************** START CALIBRATION ***************/
Status = MpmcCalibrationExample(XPAR_MPMC_0_DEVICE_ID);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/***************** END CALIBRATION *****************/
TotalErrors = MpmcMemTestExample(XPAR_MPMC_0_DEVICE_ID);
if (TotalErrors) {
xil_printf("\r\n### Program finished with errors ###\r\n");
} else {
xil_printf("\r\n### Program finished successfully ###\r\n");
}
ENABLE_ICACHE();
ENABLE_DCACHE();
Xuint32 memSize = XPAR_MPMC_0_MPMC_HIGHADDR - XPAR_MPMC_0_MPMC_BASEADDR + 1; //get correct SDRAM size
Xuint32* myAddress = (Xuint32*)XPAR_MPMC_0_MPMC_BASEADDR;
xil_printf("\r\nStarting Wade's special Test...\r\n");
char wadeSuccess = RunAllMemoryTests(myAddress, memSize);
if (wadeSuccess){
xil_printf("Wade's test PASSED!");
}
else{
xil_printf("Wade's test FAILED!");
}
xil_printf("Total Errors: %d\r\n", TotalErrors);
}
}
void disable_caches()
{
XCache_DisableDCache();
XCache_DisableICache();
}
/******************************************************************************
* Name: main
* Description: Program entry point
*
* Returns: int - returns 0 if no errors
******************************************************************************/
int main() {
/* declare a network interface and network addresses */
struct netif *netif, server_netif;
struct ip_addr ipaddr, netmask, gw;
/* specify a unique MAC address for the board */
#ifdef XPAR_CPU_PPC440_CORE_CLOCK_FREQ_HZ /* set MAC on ML507 board */
unsigned char mac_ethernet_address[] = {0x00, 0x0a, 0x35, 0x01, 0xC9, 0x76};
#else /* set MAC on ML410 board */
unsigned char mac_ethernet_address[] = {0x00, 0x0a, 0x35, 0x01, 0x9A, 0xFE};
#endif
/* set the network interface pointer */
netif = &server_netif;
/* enable caches */
XCache_EnableICache( INSTR_CACHE );
XCache_EnableDCache( DATA_CACHE );
/* setup interrupts */
setup_interrupts();
/* initliaze network addresses to be used */
IP4_ADDR( &ipaddr, 192, 168, 1, 15 );
IP4_ADDR( &netmask, 255, 255, 255, 0 );
IP4_ADDR( &gw, 192, 168, 1, 1 );
/* print the application header and IP settings */
print_app_header();
print_ip_settings(&ipaddr, &netmask, &gw);
/* initialize lwip */
lwip_init();
/* add network interface to the netif_list, and set it as default */
if( !xemac_add( netif, &ipaddr, &netmask, &gw,
mac_ethernet_address, EMAC_BASEADDR ) ) {
xil_printf( "Error adding N/W interface\n\r" );
return -1;
}
netif_set_default( netif );
/* now enable interrupts */
enable_interrupts();
/* specify that the network if is up */
netif_set_up( netif );
/* start the application */
start_application();
/* print debug header if debug mode set */
#ifdef QMFIR_DEBUG
debug_menu();
while( 1) {
qmfir_debug();
}
#endif
/* receive and process packets */
while( 1 ) {
xemacif_input( netif );
}
/* disable caches */
XCache_DisableDCache();
XCache_DisableICache();
return 0;
} /* main */
int main (void) {
XCache_EnableICache(0x80000001);
XCache_EnableDCache(0x80000001);
/* Initialize RS232 - Set baudrate and number of stop bits */
XUartNs550_SetBaud(XPAR_RS232_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, 9600);
XUartNs550_mSetLineControlReg(XPAR_RS232_BASEADDR, XUN_LCR_8_DATA_BITS);
print("-- Entering main() --\r\n");
/*
* MemoryTest routine will not be run for the memory at
* 0xffff0000 (xps_bram_if_cntlr_1)
* because it is being used to hold a part of this application program
*/
/*
* MemoryTest routine will not be run for the memory at
* 0x86000000 (FLASH_8Mx16)
* because it is a read-only memory
*/
/* Testing Memory (DDR2_SDRAM_16Mx32)*/
{
XStatus status;
print("Starting MemoryTest for DDR2_SDRAM_16Mx32:\r\n");
print(" Running 32-bit test...");
status = XUtil_MemoryTest32((Xuint32*)XPAR_DDR2_SDRAM_16MX32_MEM_BASEADDR, 1024, 0xAAAA5555, XUT_ALLMEMTESTS);
if (status == XST_SUCCESS) {
print("PASSED!\r\n");
}
else {
print("FAILED!\r\n");
}
print(" Running 16-bit test...");
status = XUtil_MemoryTest16((Xuint16*)XPAR_DDR2_SDRAM_16MX32_MEM_BASEADDR, 2048, 0xAA55, XUT_ALLMEMTESTS);
if (status == XST_SUCCESS) {
print("PASSED!\r\n");
}
else {
print("FAILED!\r\n");
}
print(" Running 8-bit test...");
status = XUtil_MemoryTest8((Xuint8*)XPAR_DDR2_SDRAM_16MX32_MEM_BASEADDR, 4096, 0xA5, XUT_ALLMEMTESTS);
if (status == XST_SUCCESS) {
print("PASSED!\r\n");
}
else {
print("FAILED!\r\n");
}
}
print("-- Exiting main() --\r\n");
XCache_DisableDCache();
XCache_DisableICache();
return 0;
}
