static void SetupInterruptSystem(XScuGic *GicInstancePtr, u32 *FPGAPtr, u16 FPGAIntrId,
XGpioPs *Gpio, u16 GpioIntrId)
{
XScuGic_Config *IntcConfig; //GIC config
Xil_ExceptionInit();
//initialise the GIC
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
XScuGic_CfgInitialize(GicInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
//connect to the hardware
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
GicInstancePtr);
//set up the timer interrupt
XScuGic_Connect(GicInstancePtr, FPGAIntrId,
(Xil_ExceptionHandler)FPGAIntrHandler,
(void *)FPGAPtr);
//set up the GPIO interrupt
XScuGic_Connect(GicInstancePtr, GpioIntrId,
(Xil_ExceptionHandler)XGpioPs_IntrHandler,
(void *)Gpio);
//Enable interrupts for all the pins in bank 0.
XGpioPs_SetIntrTypePin(Gpio, pbsw, XGPIOPS_IRQ_TYPE_EDGE_RISING);
//Set the handler for gpio interrupts.
XGpioPs_SetCallbackHandler(Gpio, (void *)Gpio, GPIOIntrHandler);
//Enable the GPIO interrupts of Bank 0.
XGpioPs_IntrEnablePin(Gpio, pbsw);
//Enable the interrupt for the GPIO device.
XScuGic_Enable(GicInstancePtr, GpioIntrId);
//enable the interrupt for the Timer at GIC
XScuGic_Enable(GicInstancePtr, FPGAIntrId);
// Enable interrupts in the Processor.
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
printf("Interrupt Set Up\n\r");
}
/*
* Set Up Interrupt for IMU
*/
int setupDMPInt() {
//Variables
int status;
XScuGic_Config* IntcConfig;
XGpioPs_Config* GpioConfig;
unsigned char data;
//MPU and DMP
//Configure MPU Interrupt Pin
status = imuReadIntConfig(&data); //Read Register
if (status != XST_SUCCESS) {
return status;
}
//Modify Bits
data &= (~INT_LEVEL_BIT); //Clear bit --> active high
data &= (~INT_OPEN_BIT); //Clear bit --> push-pull
data &= (~INT_RD_CLEAR_BIT); //Clear bit --> interrupt status bits are cleared only by reading INT_STATUS (Register 58)
data |= LATCH_INT_EN_BIT; //Set bit --> INT pin is held high until the interrupt is cleared
//Configure Int Pin
status = imuConfigureInt(&data);
if (status != XST_SUCCESS) {
return status;
}
//Set Interrupt level
status = mpu_set_int_level(0); //Set Interrupt for "active high" (0)
if (status != XST_SUCCESS) {
myprintf("mpu_int.c: Could not set interrupt level.\r\n");
return status;
}
//Enable Latched Interrupt
status = imuSetIntLatched(1);
if (status != XST_SUCCESS) {
myprintf("mpu_int.c: Could not set latched interrupt.\r\n");
return status;
}
//Set DMP Interrupt Mode
status = imuSetDmpIntMode(DMP_INT_CONTINUOUS); //Interrupt when one FIFO period has elapsed
if (status != XST_SUCCESS) {
myprintf("mpu_int.c: Could not set interrupt mode.\r\n");
return status;
}
//Initialize Xil Exceptions
Xil_ExceptionInit();
//Initialize GPIO
GpioConfig = XGpioPs_LookupConfig(GPIO_DEVICE_ID);
status = XGpioPs_CfgInitialize(&Gpio, GpioConfig, GpioConfig->BaseAddr);
if (status != XST_SUCCESS) {
myprintf("mpu_utils.c: Error initializing GPIO Config.\r\n");
return status;
}
//Initialize GIC
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
status = XScuGic_CfgInitialize(&Intc, IntcConfig,
IntcConfig->CpuBaseAddress);
if (status != XST_SUCCESS) {
myprintf("mpu_utils.c: Error initializing SCU GIC Config.\r\n");
return status;
}
//Connect interrupt controller interrupt handler to HW interrupt handling logic in PS
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler) XScuGic_InterruptHandler, &Intc);
//Connect driver handler (GIC) called when interrupt occurs to HW defined above
XScuGic_Connect(&Intc, GPIO_INT_ID,
(Xil_ExceptionHandler) myXGpioPs_IntrHandler, (void*) &Gpio); //Use my own Intr Handler
//Enable Interrupt for Pin
XGpioPs_SetIntrTypePin(&Gpio, GPIO_INT_PIN, XGPIOPS_IRQ_TYPE_EDGE_RISING);
//Set Callback Handler for GPIO Interrupts
XGpioPs_SetCallbackHandler(&Gpio, (void *) &Gpio,
(XGpioPs_Handler) ImuIntrHandler);
//Enable GPIO Interrupt for Pin
XGpioPs_IntrEnablePin(&Gpio, GPIO_INT_PIN);
if (!XGpioPs_IntrGetEnabledPin(&Gpio, GPIO_INT_PIN)) {
myprintf("mpu_int.c: Interrupt not enabled.\r\n");
}
//Enable Interrupts for GPIO
XScuGic_Enable(&Intc, GPIO_INT_ID);
//Enable Interrupts in Processor
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
//Free memory
return XST_SUCCESS;
}
