/*
*
* Handle an interrupt from the Ethernet MAC when configured with scatter-gather
* DMA. The only interrupts handled in this case are errors.
*
* @param InstancePtr is a pointer to the XEmac instance to be worked on.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
static void HandleEmacDmaIntr(XEmac * InstancePtr)
{
u32 IntrStatus;
/*
* When configured with DMA, the EMAC generates interrupts only when errors
* occur. We clear the interrupts immediately so that any latched status
* interrupt bits will reflect the true status of the device, and so any
* pulsed interrupts (non-status) generated during the Isr will not be lost.
*/
IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, IntrStatus);
/*
* Check the MAC for errors
*/
XEmac_CheckEmacError(InstancePtr, IntrStatus);
}
/******************************************************************************
*
* FUNCTION:
*
* IpIntrSelfTest
*
* DESCRIPTION:
*
* Perform a self test on the IP interrupt registers of the IPIF. This
* function modifies registers of the IPIF such that they are not guaranteed
* to be in the same state when it returns. Any bits in the IP interrupt
* status register which are set are assumed to be set by default after a reset
* and are not tested in the test.
*
* ARGUMENTS:
*
* InstancePtr points to the XIpIf to operate on.
*
* IpRegistersWidth contains the number of bits in the IP interrupt registers
* of the device. The hardware is parameterizable such that only the number of
* bits necessary to support a device are implemented. This value must be
* between 0 and 32 with 0 indicating there are no IP interrupt registers used.
*
* RETURN VALUE:
*
* A status indicating XST_SUCCESS if the test was successful. Otherwise, one
* of the following values is returned.
*
* XST_IPIF_RESET_REGISTER_ERROR The value of a register at reset was
* not valid
* XST_IPIF_IP_STATUS_ERROR A write to the IP interrupt status
* register did not read back correctly
* XST_IPIF_IP_ACK_ERROR One or more bits in the IP status
* register did not reset when acked
* XST_IPIF_IP_ENABLE_ERROR The IP interrupt enable register
* did not read back correctly based upon
* what was written to it
* NOTES:
*
* None.
*
******************************************************************************/
static XStatus
IpIntrSelfTest(u32 RegBaseAddress, u32 IpRegistersWidth)
{
/* ensure that the IP interrupt interrupt enable register is zero
* as it should be at reset, the interrupt status is dependent upon the
* IP such that it's reset value is not known
*/
if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) {
return XST_IPIF_RESET_REGISTER_ERROR;
}
/* if there are any used IP interrupts, then test all of the interrupt
* bits in all testable registers
*/
if (IpRegistersWidth > 0) {
u32 BitCount;
u32 IpInterruptMask = XIIF_V123B_FIRST_BIT_MASK;
u32 Mask = XIIF_V123B_FIRST_BIT_MASK; /* bits assigned MSB to LSB */
u32 InterruptStatus;
/* generate the register masks to be used for IP register tests, the
* number of bits supported by the hardware is parameterizable such
* that only that number of bits are implemented in the registers, the
* bits are allocated starting at the MSB of the registers
*/
for (BitCount = 1; BitCount < IpRegistersWidth; BitCount++) {
Mask = Mask << 1;
IpInterruptMask |= Mask;
}
/* get the current IP interrupt status register contents, any bits
* already set must default to 1 at reset in the device and these
* bits can't be tested in the following test, remove these bits from
* the mask that was generated for the test
*/
InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
IpInterruptMask &= ~InterruptStatus;
/* set the bits in the device status register and verify them by reading
* the register again, all bits of the register are latched
*/
XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask);
InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
if ((InterruptStatus & IpInterruptMask) != IpInterruptMask)
{
return XST_IPIF_IP_STATUS_ERROR;
}
/* test to ensure that the bits set in the IP interrupt status register
* can be cleared by acknowledging them in the IP interrupt status
* register then read it again and verify it was cleared
*/
XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask);
InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
if ((InterruptStatus & IpInterruptMask) != 0) {
return XST_IPIF_IP_ACK_ERROR;
}
/* set the IP interrupt enable set register and then read the IP
* interrupt enable register and verify the interrupts were enabled
*/
XIIF_V123B_WRITE_IIER(RegBaseAddress, IpInterruptMask);
if (XIIF_V123B_READ_IIER(RegBaseAddress) != IpInterruptMask) {
return XST_IPIF_IP_ENABLE_ERROR;
}
/* clear the IP interrupt enable register and then read the
* IP interrupt enable register and verify the interrupts were disabled
*/
XIIF_V123B_WRITE_IIER(RegBaseAddress, 0);
if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) {
return XST_IPIF_IP_ENABLE_ERROR;
}
}
return XST_SUCCESS;
}
/**
*
* Receive an Ethernet frame into the buffer passed as an argument. This
* function is called in response to the callback function for received frames
* being called by the driver. The callback function is set up using
* SetFifoRecvHandler, and is invoked when the driver receives an interrupt
* indicating a received frame. The driver expects the upper layer software to
* call this function, FifoRecv, to receive the frame. The buffer supplied
* should be large enough to hold a maximum-size Ethernet frame.
*
* The buffer into which the frame will be received must be 32-bit aligned. If
* using simple DMA and the PLB 10/100 Ethernet core, the buffer must be 64-bit
* aligned.
*
* If the device is configured with DMA, simple DMA will be used to transfer
* the buffer from the Emac to memory. This means that this buffer should not
* be cached. See the comment section "Simple DMA" in xemac.h for more
* information.
*
* @param InstancePtr is a pointer to the XEmac instance to be worked on.
* @param BufPtr is a pointer to a aligned buffer into which the received
* Ethernet frame will be copied.
* @param ByteCountPtr is both an input and an output parameter. It is a pointer
* to a 32-bit word that contains the size of the buffer on entry into
* the function and the size the received frame on return from the
* function.
*
* @return
*
* - XST_SUCCESS if the frame was sent successfully
* - XST_DEVICE_IS_STOPPED if the device has not yet been started
* - XST_NOT_INTERRUPT if the device is not in interrupt mode
* - XST_NO_DATA if there is no frame to be received from the FIFO
* - XST_BUFFER_TOO_SMALL if the buffer to receive the frame is too small for
* the frame waiting in the FIFO.
* - XST_DEVICE_BUSY if configured for simple DMA and the DMA engine is busy
* - XST_DMA_ERROR if an error occurred during the DMA transfer (simple DMA).
* The user should treat this as a fatal error that requires a reset of the
* EMAC device.
*
* @note
*
* The input buffer must be big enough to hold the largest Ethernet frame.
*
* @internal
*
* The Ethernet MAC uses FIFOs behind its length and status registers. For this
* reason, it is important to keep the length, status, and data FIFOs in sync
* when reading or writing to them.
*
******************************************************************************/
XStatus
XEmac_FifoRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr)
{
XStatus Result;
u32 PktLength;
u32 StatusReg;
XASSERT_NONVOID(InstancePtr != NULL);
XASSERT_NONVOID(BufPtr != NULL);
XASSERT_NONVOID(ByteCountPtr != NULL);
XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
/*
* Be sure the device is not configured for polled mode and it is started
*/
if (InstancePtr->IsPolled) {
return XST_NOT_INTERRUPT;
}
if (InstancePtr->IsStarted != XCOMPONENT_IS_STARTED) {
return XST_DEVICE_IS_STOPPED;
}
/*
* Make sure the buffer is big enough to hold the maximum frame size.
* We need to do this because as soon as we read the MAC's packet length
* register, which is actually a FIFO, we remove that length from the
* FIFO. We do not want to read the length FIFO without also reading the
* data FIFO since this would get the FIFOs out of sync. So we have to
* make this restriction.
*/
if (*ByteCountPtr < XEM_MAX_FRAME_SIZE) {
return XST_BUFFER_TOO_SMALL;
}
/*
* Before reading from the length FIFO, make sure the length FIFO is not
* empty. We could cause an underrun error if we try to read from an
* empty FIFO.
*/
StatusReg = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
if (StatusReg & XEM_EIR_RECV_LFIFO_EMPTY_MASK) {
/*
* Clear the empty status so the next time through the current status
* of the hardware is reflected (we have to do this because the status
* is level in the device but latched in the interrupt status register).
*/
XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress,
XEM_EIR_RECV_LFIFO_EMPTY_MASK);
return XST_NO_DATA;
}
/*
* If configured with DMA, make sure the DMA engine is not busy
*/
if (XEmac_mIsDma(InstancePtr)) {
if (XDmaChannel_GetStatus(&InstancePtr->RecvChannel) &
XDC_DMASR_BUSY_MASK) {
return XST_DEVICE_BUSY;
}
}
/*
* Determine, from the MAC, the length of the next packet available
* in the data FIFO (there should be a non-zero length here)
*/
PktLength = XIo_In32(InstancePtr->BaseAddress + XEM_RPLR_OFFSET);
if (PktLength == 0) {
return XST_NO_DATA;
}
/*
* We assume that the MAC never has a length bigger than the largest
* Ethernet frame, so no need to make another check here.
*
* Receive either by directly reading the FIFO or using the DMA engine
*/
if (!XEmac_mIsDma(InstancePtr)) {
/*
* This is a non-blocking read. The FIFO returns an error if there is
* not at least the requested amount of data in the FIFO.
*/
Result =
XPacketFifoV200a_Read(&InstancePtr->RecvFifo, BufPtr,
PktLength);
if (Result != XST_SUCCESS) {
return Result;
}
} else {
/*
* Call on DMA to transfer from the FIFO to the buffer. First set up
* the DMA control register.
*/
XDmaChannel_SetControl(&InstancePtr->RecvChannel,
XDC_DMACR_DEST_INCR_MASK |
XDC_DMACR_SOURCE_LOCAL_MASK |
XDC_DMACR_SG_DISABLE_MASK);
/*
* Now transfer the data
*/
XDmaChannel_Transfer(&InstancePtr->RecvChannel,
(u32 *) (InstancePtr->BaseAddress +
XEM_PFIFO_RXDATA_OFFSET),
(u32 *) BufPtr, PktLength);
/*
* Poll here waiting for DMA to be not busy. We think this will
* typically be a single read since DMA should be ahead of the SW.
*/
do {
StatusReg =
XDmaChannel_GetStatus(&InstancePtr->RecvChannel);
}
while (StatusReg & XDC_DMASR_BUSY_MASK);
/* Return an error if there was a problem with DMA */
if ((StatusReg & XDC_DMASR_BUS_ERROR_MASK) ||
(StatusReg & XDC_DMASR_BUS_TIMEOUT_MASK)) {
InstancePtr->Stats.DmaErrors++;
return XST_DMA_ERROR;
}
}
*ByteCountPtr = PktLength;
InstancePtr->Stats.RecvFrames++;
InstancePtr->Stats.RecvBytes += PktLength;
return XST_SUCCESS;
}
/******************************************************************************
*
* Handle an interrupt from the Ethernet MAC when configured for direct FIFO
* communication. The interrupts handled are:
* - Transmit done (transmit status FIFO is non-empty). Used to determine when
* a transmission has been completed.
* - Receive done (receive length FIFO is non-empty). Used to determine when a
* valid frame has been received.
*
* In addition, the interrupt status is checked for errors.
*
* @param InstancePtr is a pointer to the XEmac instance to be worked on.
*
* @return
*
* None.
*
* @note
*
* None.
*
******************************************************************************/
static void
HandleEmacFifoIntr(XEmac * InstancePtr)
{
u32 IntrStatus;
/*
* The EMAC generates interrupts for errors and generates the transmit
* and receive done interrupts for data. We clear the interrupts
* immediately so that any latched status interrupt bits will reflect the
* true status of the device, and so any pulsed interrupts (non-status)
* generated during the Isr will not be lost.
*/
IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, IntrStatus);
if (IntrStatus & XEM_EIR_RECV_DONE_MASK) {
/*
* Configured for direct memory-mapped I/O using FIFO with interrupts.
* This interrupt means the RPLR is non-empty, indicating a frame has
* arrived.
*/
InstancePtr->Stats.RecvInterrupts++;
InstancePtr->FifoRecvHandler(InstancePtr->FifoRecvRef);
/*
* The upper layer has removed as many frames as it wants to, so we
* need to clear the RECV_DONE bit before leaving the ISR so that it
* reflects the current state of the hardware (because it's a level
* interrupt that is latched in the IPIF interrupt status register).
* Note that if we've reached this point the bit is guaranteed to be
* set because it was cleared at the top of this ISR before any frames
* were serviced, so the bit was set again immediately by hardware
* because the RPLR was not yet emptied by software.
*/
XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress,
XEM_EIR_RECV_DONE_MASK);
}
/*
* If configured for direct memory-mapped I/O using FIFO, the xmit status
* FIFO must be read and the callback invoked regardless of success or not.
*/
if (IntrStatus & XEM_EIR_XMIT_DONE_MASK) {
u32 XmitStatus;
InstancePtr->Stats.XmitInterrupts++;
XmitStatus =
XIo_In32(InstancePtr->BaseAddress + XEM_TSR_OFFSET);
/*
* Collision errors are stored in the transmit status register
* instead of the interrupt status register
*/
if (XmitStatus & XEM_TSR_EXCESS_DEFERRAL_MASK) {
InstancePtr->Stats.XmitExcessDeferral++;
}
if (XmitStatus & XEM_TSR_LATE_COLLISION_MASK) {
InstancePtr->Stats.XmitLateCollisionErrors++;
}
InstancePtr->FifoSendHandler(InstancePtr->FifoSendRef);
/*
* Only one status is retrieved per interrupt. We need to clear the
* XMIT_DONE bit before leaving the ISR so that it reflects the current
* state of the hardware (because it's a level interrupt that is latched
* in the IPIF interrupt status register). Note that if we've reached
* this point the bit is guaranteed to be set because it was cleared at
* the top of this ISR before any statuses were serviced, so the bit was
* set again immediately by hardware because the TSR was not yet emptied
* by software.
*/
XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress,
XEM_EIR_XMIT_DONE_MASK);
}
/*
* Check the MAC for errors
*/
XEmac_CheckEmacError(InstancePtr, IntrStatus);
}
/**
*
* This function is the interrupt handler for the XIic driver. This function
* should be connected to the interrupt system.
*
* Only one interrupt source is handled for each interrupt allowing
* higher priority system interrupts quicker response time.
*
* @param InstancePtr is a pointer to the XIic instance to be worked on.
*
* @return
*
* None.
*
* @internal
*
* The XIIC_INTR_ARB_LOST_MASK and XIIC_INTR_TX_ERROR_MASK interrupts must have
* higher priority than the other device interrupts so that the IIC device does
* not get into a potentially confused state. The remaining interrupts may be
* rearranged with no harm.
*
* All XIic device interrupts are ORed into one device interrupt. This routine
* reads the pending interrupts via the IpIf interface and masks that with the
* interrupt mask to evaluate only the interrupts enabled.
*
******************************************************************************/
void XIic_InterruptHandler(void *InstancePtr)
{
u8 Status;
u32 IntrStatus;
u32 IntrPending;
u32 IntrEnable;
XIic *IicPtr = NULL;
u32 Clear = 0;
/*
* Verify that each of the inputs are valid.
*/
XASSERT_VOID(InstancePtr != NULL);
/*
* Convert the non-typed pointer to an IIC instance pointer
*/
IicPtr = (XIic *) InstancePtr;
/* Get the interrupt Status from the IPIF. There is no clearing of
* interrupts in the IPIF. Interrupts must be cleared at the source.
* To find which interrupts are pending; AND interrupts pending with
* interrupts masked.
*/
IntrPending = XIIF_V123B_READ_IISR(IicPtr->BaseAddress);
IntrEnable = XIIF_V123B_READ_IIER(IicPtr->BaseAddress);
IntrStatus = IntrPending & IntrEnable;
/* Do not processes a devices interrupts if the device has no
* interrupts pending or the global interrupts have been disabled
*/
if ((IntrStatus == 0) |
(XIIF_V123B_IS_GINTR_ENABLED(IicPtr->BaseAddress) == FALSE)) {
return;
}
/* Update interrupt stats and get the contents of the status register
*/
IicPtr->Stats.IicInterrupts++;
Status = XIo_In8(IicPtr->BaseAddress + XIIC_SR_REG_OFFSET);
/* Service requesting interrupt
*/
if (IntrStatus & XIIC_INTR_ARB_LOST_MASK) {
/* Bus Arbritration Lost */
IicPtr->Stats.ArbitrationLost++;
XIic_ArbLostFuncPtr(IicPtr);
Clear = XIIC_INTR_ARB_LOST_MASK;
}
else if (IntrStatus & XIIC_INTR_TX_ERROR_MASK) {
/* Transmit errors (no acknowledge) received */
IicPtr->Stats.TxErrors++;
TxErrorHandler(IicPtr);
Clear = XIIC_INTR_TX_ERROR_MASK;
}
else if (IntrStatus & XIIC_INTR_NAAS_MASK) {
/* Not Addressed As Slave */
XIic_NotAddrAsSlaveFuncPtr(IicPtr);
Clear = XIIC_INTR_NAAS_MASK;
}
else if (IntrStatus & XIIC_INTR_RX_FULL_MASK) {
/* Receive register/FIFO is full */
IicPtr->Stats.RecvInterrupts++;
if (Status & XIIC_SR_ADDR_AS_SLAVE_MASK) {
XIic_RecvSlaveFuncPtr(IicPtr);
} else {
XIic_RecvMasterFuncPtr(IicPtr);
}
Clear = XIIC_INTR_RX_FULL_MASK;
}
else if (IntrStatus & XIIC_INTR_AAS_MASK) {
/* Addressed As Slave */
XIic_AddrAsSlaveFuncPtr(IicPtr);
Clear = XIIC_INTR_AAS_MASK;
}
else if (IntrStatus & XIIC_INTR_BNB_MASK) {
/* IIC bus has transitioned to not busy */
/* check if send callback needs to run */
if (IicPtr->BNBOnly == TRUE) {
XIic_BusNotBusyFuncPtr(IicPtr);
IicPtr->BNBOnly = FALSE;
} else {
IicPtr->SendHandler(IicPtr->SendCallBackRef, 0);
}
Clear = XIIC_INTR_BNB_MASK;
/* The bus is not busy, disable BusNotBusy interrupt */
XIic_mDisableIntr(IicPtr->BaseAddress, XIIC_INTR_BNB_MASK);
}
else if ((IntrStatus & XIIC_INTR_TX_EMPTY_MASK) ||
(IntrStatus & XIIC_INTR_TX_HALF_MASK)) {
/* Transmit register/FIFO is empty or empty *
*/
IicPtr->Stats.SendInterrupts++;
if (Status & XIIC_SR_ADDR_AS_SLAVE_MASK) {
XIic_SendSlaveFuncPtr(IicPtr);
} else {
XIic_SendMasterFuncPtr(IicPtr);
}
/* Clear Interrupts
*/
IntrStatus = XIIF_V123B_READ_IISR(IicPtr->BaseAddress);
Clear = IntrStatus & (XIIC_INTR_TX_EMPTY_MASK |
XIIC_INTR_TX_HALF_MASK);
}
XIIF_V123B_WRITE_IISR(IicPtr->BaseAddress, Clear);
}
