static void xilinx_pcie_root_config_write(PCIDevice *d, uint32_t address,
uint32_t val, int len)
{
XilinxPCIEHost *s = XILINX_PCIE_HOST(OBJECT(d)->parent);
switch (address) {
case ROOTCFG_INTDEC:
xilinx_pcie_update_intr(s, 0, val);
break;
case ROOTCFG_INTMASK:
s->intr_mask = val;
xilinx_pcie_update_intr(s, 0, 0);
break;
case ROOTCFG_RPSCR:
s->rpscr &= ~ROOTCFG_RPSCR_BRIDGEEN;
s->rpscr |= val & ROOTCFG_RPSCR_BRIDGEEN;
memory_region_set_enabled(&s->mmio, val & ROOTCFG_RPSCR_BRIDGEEN);
if (val & ROOTCFG_INTMASK_INTX) {
s->rpscr &= ~ROOTCFG_INTMASK_INTX;
}
break;
case ROOTCFG_RPIFR1:
case ROOTCFG_RPIFR2:
if (s->intr_fifo_w == s->intr_fifo_r) {
/* FIFO empty */
return;
} else {
s->intr_fifo_r = (s->intr_fifo_r + 1) % ARRAY_SIZE(s->intr_fifo);
}
break;
default:
pci_default_write_config(d, address, val, len);
break;
}
}
static inline XilinxPCIEHost *
xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr,
hwaddr cfg_base, uint64_t cfg_size,
hwaddr mmio_base, uint64_t mmio_size,
qemu_irq irq, bool link_up)
{
DeviceState *dev;
MemoryRegion *cfg, *mmio;
dev = qdev_create(NULL, TYPE_XILINX_PCIE_HOST);
qdev_prop_set_uint32(dev, "bus_nr", bus_nr);
qdev_prop_set_uint64(dev, "cfg_base", cfg_base);
qdev_prop_set_uint64(dev, "cfg_size", cfg_size);
qdev_prop_set_uint64(dev, "mmio_base", mmio_base);
qdev_prop_set_uint64(dev, "mmio_size", mmio_size);
qdev_prop_set_bit(dev, "link_up", link_up);
qdev_init_nofail(dev);
cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0);
mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0);
qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq);
return XILINX_PCIE_HOST(dev);
}
static void xilinx_pcie_host_realize(DeviceState *dev, Error **errp)
{
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
XilinxPCIEHost *s = XILINX_PCIE_HOST(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev);
snprintf(s->name, sizeof(s->name), "pcie%u", s->bus_nr);
/* PCI configuration space */
pcie_host_mmcfg_init(pex, s->cfg_size);
/* MMIO region */
memory_region_init(&s->mmio, OBJECT(s), "mmio", UINT64_MAX);
memory_region_set_enabled(&s->mmio, false);
/* dummy PCI I/O region (not visible to the CPU) */
memory_region_init(&s->io, OBJECT(s), "io", 16);
/* interrupt out */
qdev_init_gpio_out_named(dev, &s->irq, "interrupt_out", 1);
sysbus_init_mmio(sbd, &pex->mmio);
sysbus_init_mmio(sbd, &s->mmio);
pci->bus = pci_register_root_bus(dev, s->name, xilinx_pcie_set_irq,
pci_swizzle_map_irq_fn, s, &s->mmio,
&s->io, 0, 4, TYPE_PCIE_BUS);
qdev_set_parent_bus(DEVICE(&s->root), BUS(pci->bus));
qdev_init_nofail(DEVICE(&s->root));
}
static void xilinx_pcie_set_irq(void *opaque, int irq_num, int level)
{
XilinxPCIEHost *s = XILINX_PCIE_HOST(opaque);
xilinx_pcie_queue_intr(s,
(irq_num << ROOTCFG_RPIFR1_INT_LANE_SHIFT) |
(level << ROOTCFG_RPIFR1_INT_ASSERT_SHIFT) |
(1 << ROOTCFG_RPIFR1_INT_VALID_SHIFT),
0);
}
static void xilinx_pcie_host_init(Object *obj)
{
XilinxPCIEHost *s = XILINX_PCIE_HOST(obj);
XilinxPCIERoot *root = &s->root;
object_initialize(root, sizeof(*root), TYPE_XILINX_PCIE_ROOT);
object_property_add_child(obj, "root", OBJECT(root), NULL);
qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
qdev_prop_set_bit(DEVICE(root), "multifunction", false);
}
static void xilinx_pcie_root_realize(PCIDevice *pci_dev, Error **errp)
{
BusState *bus = qdev_get_parent_bus(DEVICE(pci_dev));
XilinxPCIEHost *s = XILINX_PCIE_HOST(bus->parent);
pci_set_word(pci_dev->config + PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
pci_set_word(pci_dev->config + PCI_MEMORY_BASE, s->mmio_base >> 16);
pci_set_word(pci_dev->config + PCI_MEMORY_LIMIT,
((s->mmio_base + s->mmio_size - 1) >> 16) & 0xfff0);
pci_bridge_initfn(pci_dev, TYPE_PCI_BUS);
if (pcie_endpoint_cap_v1_init(pci_dev, 0x80) < 0) {
error_setg(errp, "Failed to initialize PCIe capability");
}
}
static uint32_t xilinx_pcie_root_config_read(PCIDevice *d,
uint32_t address, int len)
{
XilinxPCIEHost *s = XILINX_PCIE_HOST(OBJECT(d)->parent);
uint32_t val;
switch (address) {
case ROOTCFG_INTDEC:
val = s->intr;
break;
case ROOTCFG_INTMASK:
val = s->intr_mask;
break;
case ROOTCFG_PSCR:
val = s->link_up ? ROOTCFG_PSCR_LINK_UP : 0;
break;
case ROOTCFG_RPSCR:
if (s->intr_fifo_r != s->intr_fifo_w) {
s->rpscr &= ~ROOTCFG_RPSCR_INTNEMPTY;
} else {
s->rpscr |= ROOTCFG_RPSCR_INTNEMPTY;
}
val = s->rpscr;
break;
case ROOTCFG_RPIFR1:
if (s->intr_fifo_w == s->intr_fifo_r) {
/* FIFO empty */
val = 0;
} else {
val = s->intr_fifo[s->intr_fifo_r].fifo_reg1;
}
break;
case ROOTCFG_RPIFR2:
if (s->intr_fifo_w == s->intr_fifo_r) {
/* FIFO empty */
val = 0;
} else {
val = s->intr_fifo[s->intr_fifo_r].fifo_reg2;
}
break;
default:
val = pci_default_read_config(d, address, len);
break;
}
return val;
}
