XStatus
init_ll_fifo(struct xemac_s *xemac)
{
xlltemacif_s *xlltemacif = (xlltemacif_s *)(xemac->state);
#if NO_SYS
struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
#endif
/* initialize ll fifo */
XLlFifo_Initialize(&xlltemacif->llfifo,
XLlTemac_LlDevBaseAddress(&xlltemacif->lltemac));
/* Clear any pending FIFO interrupts */
XLlFifo_IntClear(&xlltemacif->llfifo, XLLF_INT_ALL_MASK);
/* enable fifo interrupts */
XLlFifo_IntEnable(&xlltemacif->llfifo, XLLF_INT_ALL_MASK);
#if NO_SYS
/* Register temac interrupt with interrupt controller */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xlltemacif->lltemac.Config.TemacIntr,
(XInterruptHandler)xlltemac_error_handler,
&xlltemacif->lltemac);
/* connect & enable FIFO interrupt */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xlltemacif->lltemac.Config.LLFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
/* Enable EMAC interrupts in the interrupt controller */
do {
/* read current interrupt enable mask */
unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr + XIN_IER_OFFSET);
/* form new mask enabling SDMA & ll_temac interrupts */
cur_mask = cur_mask
| (1 << xlltemacif->lltemac.Config.LLFifoIntr)
| (1 << xlltemacif->lltemac.Config.TemacIntr);
/* set new mask */
XIntc_mEnableIntr(xtopologyp->intc_baseaddr, cur_mask);
} while (0);
#else
/* connect & enable TEMAC interrupts */
register_int_handler(xlltemacif->lltemac.Config.TemacIntr,
(XInterruptHandler)xlltemac_error_handler,
&xlltemacif->lltemac);
enable_interrupt(xlltemacif->lltemac.Config.TemacIntr);
/* connect & enable FIFO interrupts */
register_int_handler(xlltemacif->lltemac.Config.LLFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
enable_interrupt(xlltemacif->lltemac.Config.LLFifoIntr);
#endif
return 0;
}
void
platform_setup_timer()
{
/* set the number of cycles the timer counts before interrupting */
/* 100 Mhz clock => .01us for 1 clk tick. For 100ms, 10000000 clk ticks need to elapse */
XTmrCtr_SetLoadReg(PLATFORM_TIMER_BASEADDR, 0, TIMER_TLR);
/* reset the timers, and clear interrupts */
XTmrCtr_SetControlStatusReg(PLATFORM_TIMER_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );
/* start the timers */
XTmrCtr_SetControlStatusReg(PLATFORM_TIMER_BASEADDR, 0,
XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK
| XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK);
#if XPAR_INTC_0_HAS_FAST == 1
XIntc_RegisterFastHandler(XPAR_INTC_0_BASEADDR,
PLATFORM_TIMER_INTERRUPT_INTR,
(XFastInterruptHandler)xadapter_fasttimer_handler);
#else
/* Register Timer handler */
XIntc_RegisterHandler(XPAR_INTC_0_BASEADDR,
PLATFORM_TIMER_INTERRUPT_INTR,
(XInterruptHandler)xadapter_timer_handler,
0);
#endif
XIntc_EnableIntr(XPAR_INTC_0_BASEADDR, PLATFORM_TIMER_INTERRUPT_MASK);
}
tEplKernel PUBLIC EplTimerSynckDelInstance (void)
{
tEplKernel Ret = kEplSuccessful;
EplTimerSynckDrvCompareInterruptDisable();
EplTimerSynckDrvSetCompareValue( 0 );
#ifdef EPL_TIMER_USE_COMPARE_PDI_INT
EplTimerSynckDrvCompareTogPdiInterruptDisable();
EplTimerSynckDrvSetCompareTogPdiValue( 0 );
#endif //EPL_TIMER_USE_COMPARE_PDI_INT
#ifdef __NIOS2__
alt_ic_isr_register(EPL_TIMER_SYNC_IRQ_IC_ID, EPL_TIMER_SYNC_IRQ,
NULL, NULL, NULL);
#elif defined(__MICROBLAZE__)
XIntc_RegisterHandler(EPL_TIMER_INTC_BASE, EPL_TIMER_SYNC_IRQ,
(XInterruptHandler)NULL, (void*)NULL);
#else
#error "Configuration unknown!"
#endif
EPL_MEMSET(&EplTimerSynckInstance_l, 0, sizeof (EplTimerSynckInstance_l));
return Ret;
}
void init_sound_int()
{
XIntc_RegisterHandler(XPAR_INTC_0_BASEADDR,
XPAR_XPS_INTC_0_PLB_AC97_0_INTERRUPT_INTR,
(XInterruptHandler)sound_int_handler,
0);
}
void init_all(void) {
XIntc_Initialize(&intc, XPAR_XPS_INTC_0_DEVICE_ID);
microblaze_enable_interrupts();
XIntc_mMasterEnable(XPAR_INTC_0_BASEADDR);
XUartLite_mEnableIntr(XPAR_UARTLITE_0_BASEADDR);
//// пецхярпюжхъ напюанрвхйнб ////////////////////////////////////////////
XIntc_RegisterHandler(XPAR_XPS_INTC_0_BASEADDR,
XPAR_INTC_0_UARTLITE_0_VEC_ID,
(XInterruptHandler)handler_RS232,
(void *)0);
XIntc_RegisterHandler(XPAR_XPS_INTC_0_BASEADDR,
XPAR_INTC_0_TMRCTR_0_VEC_ID,
(XInterruptHandler)handler_Timer,
(void *)0);
///////////////////////////////////////////////////////////////////////////////
//// мюярпнийю рюилепю //////////////////////////////////////////////////////
XTmrCtr_mSetLoadReg(XPAR_XPS_TIMER_0_BASEADDR,
0,
0x61a8 //(25 MHz / 25000 = 1mS
//0x124F8//(75 MHz : 75.000 = 1 mS
);
XIntc_mEnableIntr(XPAR_INTC_0_BASEADDR,
// XPAR_XPS_TIMER_0_INTERRUPT_MASK |
XPAR_XPS_UARTLITE_0_INTERRUPT_MASK);
XTmrCtr_mSetControlStatusReg(XPAR_XPS_TIMER_0_BASEADDR,
0,
XTC_CSR_ENABLE_TMR_MASK |
XTC_CSR_ENABLE_INT_MASK |
XTC_CSR_AUTO_RELOAD_MASK |
XTC_CSR_DOWN_COUNT_MASK);
/////////////////////////////////////////////////////////////////////////////////
///////// мюярпнийю сярпниярб ббндю-бшбндю ////////////////////////////////////
XGpio_Initialize(&photo, XPAR_XPS_GPIO_0_DEVICE_ID);
XGpio_Initialize(&ircom, XPAR_XPS_GPIO_1_DEVICE_ID);
XGpio_Initialize(&kt, XPAR_XPS_GPIO_2_DEVICE_ID);
XGpio_SetDataDirection(&photo, 1, 0xffffffff); // ББНД
XGpio_SetDataDirection(&photo, 2, 0x00); // БШБНД
XGpio_SetDataDirection(&ircom, 1, 0x00); // БШБНД
XGpio_SetDataDirection(&ircom, 2, 0x00); // БШБНД
XGpio_SetDataDirection(&kt, 1, 0x00); // БШБНД
};
//------------------------------------------------------------------------------
void timer_init(void)
{
//register fit interrupt handler
XIntc_RegisterHandler(TGT_INTC_BASE,
TGT_TIMER_INTR,
(XInterruptHandler)irqHandler,
0);
//enable the fit interrupt
XIntc_EnableIntr(TGT_INTC_BASE, TGT_TIMER_INTR_MASK);
}
//---------------------------------------------------------------------------
//
// Function: initInterrupts
//
// Description: inits the global interrupt and registers the fit timer handler
//
// Parameters: void
//
// Returns: void
//
// State:
//
//---------------------------------------------------------------------------
void initInterrupts(void)
{
//note: master enable is asserted, otherwise sharedBuff would enter deadlock
enableInterruptMaster();
//register fit irq handler
XIntc_RegisterHandler(XPAR_PCP_INTC_BASEADDR, XPAR_PCP_INTC_FIT_TIMER_0_INTERRUPT_INTR,
(XInterruptHandler)FitTimerIrqHandler, 0);
//enable the fit interrupt
XIntc_EnableIntr(XPAR_PCP_INTC_BASEADDR, XPAR_FIT_TIMER_0_INTERRUPT_MASK);
}
void init_ps2_int()
{
// Enregistrement des interrupt du core dans le controlleur d'interrupt
XIntc_RegisterHandler(XPAR_INTC_0_BASEADDR,
XPAR_XPS_INTC_0_PS2CORE_0_PS2_INTERRUPT_INTR,
(XInterruptHandler)ps2_event_handler,
(void*)0);
// Initialisation des interrupt dans le core.
ps2_reset((void*)XPAR_PS2CORE_0_BASEADDR);
ps2_set_enable_interrupts((void*) XPAR_PS2CORE_0_BASEADDR, 1);
ps2_set_enable_rx_full_intr((void*) XPAR_PS2CORE_0_BASEADDR, 1);
}
void start_intc(void) {
// Setting Interupt controller
xil_printf("\r\nSetting up Interrupt Controller:\r\n");
//Initialize exception handling
xil_printf(" Initialize exception handling\r\n");
microblaze_enable_exceptions();
// Register external interrupt handler
xil_printf(" Register external interrupt handler\r\n");
microblaze_register_handler((XInterruptHandler)XIntc_DeviceInterruptHandler,
(void *)XPAR_XPS_INTC_0_DEVICE_ID);
// // Register UART interrupt handler
// // xil_printf(" Register UART interrupt handler\r\n");
// XIntc_RegisterHandler(XPAR_INTC_0_BASEADDR,XPAR_INTC_0_RS232_INTERRUPT_INTR,
// (XInterruptHandler)uart_int_handler,(void *)XPAR_RS232_BASEADDR);
// Register OPB_FX2 interrupt handler
xil_printf(" Register I2C_SLAVE interrupt handler\r\n");
XIntc_RegisterHandler(XPAR_INTC_0_BASEADDR,XPAR_XPS_INTC_0_XPS_I2C_SLAVE_0_IP2INTC_IRPT_INTR,
(XInterruptHandler)i2c_slave_int_handler,(void *)XPAR_XPS_I2C_SLAVE_0_BASEADDR);
// Enable timer interrupts
// // xil_printf(" Register OPB_TIMER interrupt handler\r\n");
// XIntc_mMasterEnable(XPAR_OPB_TIMER_0_BASEADDR); // Start the interrupt controller
// XIntc_SetIntrSvcOption( XPAR_INTC_0_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
// Enable uart interrupt in the interrupt controller
xil_printf(" Enable interrupts in the interrupt controller\r\n");
XIntc_EnableIntr(XPAR_INTC_0_BASEADDR,
// XPAR_RS232_INTERRUPT_MASK |
// XPAR_XPS_TIMER_0_INTERRUPT_MASK |
// XPAR_OPB_FX2_0_INTERRUPT_MASK |
XPAR_XPS_I2C_SLAVE_0_IP2INTC_IRPT_MASK);
xil_printf(" Start the interrupt controller\r\n");
XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);
// Enable uart interrupts
// // xil_printf(" Enable uart interrupt in Uartlite\r\n");
// XUartLite_mEnableIntr(XPAR_RS232_BASEADDR);
// xil_printf(" Enable all interrupts in XPS_FX2\r\n");
// Enable MB interrupts
// xil_printf(" Enable MB interrupts\r\n");
microblaze_enable_interrupts();
}
void init_network_timer_int()
{
/* set the number of cycles the timer counts before interrupting */
/* 100 Mhz clock => .01us for 1 clk tick. For 100ms, 10000000 clk ticks need to elapse */
XTmrCtr_SetLoadReg(XPAR_XPS_TIMER_0_BASEADDR, 0, TIMER_TLR);
/* reset the timers, and clear interrupts */
XTmrCtr_SetControlStatusReg(XPAR_XPS_TIMER_0_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );
/* start the timers */
XTmrCtr_SetControlStatusReg(XPAR_XPS_TIMER_0_BASEADDR, 0,
XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK
| XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK);
/* Register Timer handler */
XIntc_RegisterHandler(XPAR_INTC_0_BASEADDR,
XPAR_XPS_INTC_0_XPS_TIMER_0_INTERRUPT_INTR,
(XInterruptHandler)network_timer_handler,
0);
}
//--------------------------------------------------------------------
// PowerPC Timer Initialization functions.
// For PowerPC, DEC and opb_timer can be used for Profiling. This
// is selected by the user in standalone BSP
//
//--------------------------------------------------------------------
int powerpc405_init(void)
{
Xil_ExceptionInit();
Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
// Initialize the Timer.
// 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
// 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC
#ifdef PPC_PIT_INTERRUPT
ppc_dec_init();
#else
#ifdef TIMER_CONNECT_INTC
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,(void*)0);
#else
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
#endif
// Initialize the timer with Timer Ticks
opb_timer_init() ;
#endif
// Enable Interrupts in the System, if Profile Timer is the only Interrupt
// in the System.
#ifdef ENABLE_SYS_INTR
#ifdef PPC_PIT_INTERRUPT
XTime_DECEnableInterrupt() ;
#elif TIMER_CONNECT_INTC
XIntc_MasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
#endif
Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
#endif
return 0;
}
void init_display_timer_int()
{
// Set timer speed
XTmrCtr_SetLoadReg(XPAR_XPS_TIMER_1_BASEADDR, 0, TIMER_DISPLAY_TLR);
/* reset the timers, and clear interrupts */
XTmrCtr_SetControlStatusReg(XPAR_XPS_TIMER_1_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );
/* start the timers */
XTmrCtr_SetControlStatusReg(XPAR_XPS_TIMER_1_BASEADDR, 0,
XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK
| XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK);
/* Register Timer handler */
XIntc_RegisterHandler(XPAR_INTC_0_BASEADDR,
XPAR_XPS_INTC_0_XPS_TIMER_1_INTERRUPT_INTR,
(XInterruptHandler)display_timer_handler,
0);
timer_display_proc = 0;
}
//--------------------------------------------------------------------
// Initialize the Profile Timer for MicroBlaze Target.
// For MicroBlaze, opb_timer is used. The opb_timer can be directly
// connected to MicroBlaze or connected through Interrupt Controller.
//
//--------------------------------------------------------------------
int microblaze_init(void)
{
// Register profile_intr_handler
// 1. If timer is connected to Interrupt Controller, register the handler
// to Interrupt Controllers vector table.
// 2. If timer is directly connected to MicroBlaze, register the handler
// as Interrupt handler
Xil_ExceptionInit();
#ifdef TIMER_CONNECT_INTC
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,(void*)0);
#else
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)profile_intr_handler,
(void *)0) ;
#endif
// Initialize the timer with Timer Ticks
opb_timer_init() ;
// Enable Interrupts in the System, if Profile Timer is the only Interrupt
// in the System.
#ifdef ENABLE_SYS_INTR
#ifdef TIMER_CONNECT_INTC
XIntc_MasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
#endif
#endif
Xil_ExceptionEnable();
return 0;
}
void Foliage::SoundManager::init()
{
// hard reset & initialization
XAC97_HardReset(XPAR_AUDIO_CODEC_BASEADDR);
XAC97_InitAudio(XPAR_AUDIO_CODEC_BASEADDR, AC97_ANALOG_LOOPBACK);
XAC97_DisableInput(XPAR_AUDIO_CODEC_BASEADDR, AC97_MIC_INPUT);
XAC97_DisableInput(XPAR_AUDIO_CODEC_BASEADDR, AC97_LINE_INPUT);
XAC97_AwaitCodecReady(XPAR_AUDIO_CODEC_BASEADDR);
// volume settings
XAC97_WriteReg(XPAR_AUDIO_CODEC_BASEADDR, AC97_MasterVol, AC97_VOL_MAX);
XAC97_WriteReg(XPAR_AUDIO_CODEC_BASEADDR, AC97_AuxOutVol, AC97_VOL_MUTE);
XAC97_WriteReg(XPAR_AUDIO_CODEC_BASEADDR, AC97_MasterVolMono, AC97_VOL_MUTE);
XAC97_WriteReg(XPAR_AUDIO_CODEC_BASEADDR, AC97_PCBeepVol, AC97_VOL_MUTE);
XAC97_WriteReg(XPAR_AUDIO_CODEC_BASEADDR, AC97_PhoneInVol, AC97_VOL_MUTE);
XAC97_WriteReg(XPAR_AUDIO_CODEC_BASEADDR, AC97_MicVol, AC97_VOL_MUTE);
XAC97_WriteReg(XPAR_AUDIO_CODEC_BASEADDR, AC97_LineInVol, AC97_VOL_MUTE);
XAC97_WriteReg(XPAR_AUDIO_CODEC_BASEADDR, AC97_CDVol, AC97_VOL_MUTE);
XAC97_WriteReg(XPAR_AUDIO_CODEC_BASEADDR, AC97_VideoVol, AC97_VOL_MUTE);
XAC97_WriteReg(XPAR_AUDIO_CODEC_BASEADDR, AC97_AuxInVol, AC97_VOL_MUTE);
XAC97_WriteReg(XPAR_AUDIO_CODEC_BASEADDR, AC97_PCMOutVol, AC97_VOL_MAX);
XAC97_AwaitCodecReady(XPAR_AUDIO_CODEC_BASEADDR);
// VRA mode OFF
XAC97_WriteReg(XPAR_AUDIO_CODEC_BASEADDR, AC97_ExtendedAudioStat, 0);
// clear FIFOs
XAC97_ClearFifos(XPAR_AUDIO_CODEC_BASEADDR);
// interrupt
XIntc_RegisterHandler(XPAR_OPB_INTC_0_BASEADDR,
XPAR_OPB_INTC_0_AUDIO_CODEC_INTERRUPT_INTR,
(XInterruptHandler)Foliage::SoundManager::AC97_Callback,
NULL);
XAC97_mSetControl(XPAR_AUDIO_CODEC_BASEADDR, AC97_ENABLE_IN_FIFO_INTERRUPT);
std::cout << " * sound manager initialized" << std::endl;
}
static err_t low_level_init(struct netif *netif)
{
struct xemac_s *xemac;
XEmacLite_Config *config;
XEmacLite *xemaclitep;
struct xtopology_t *xtopologyp;
xemacliteif_s *xemacliteif;
unsigned link_speed = 1000;
xemaclitep = mem_malloc(sizeof *xemaclitep);
#ifndef XLWIP_CONFIG_INCLUDE_EMACLITE_ON_ZYNQ
#if XPAR_INTC_0_HAS_FAST == 1
xemaclitep_fast = xemaclitep;
#endif
#endif
if (xemaclitep == NULL) {
LWIP_DEBUGF(NETIF_DEBUG, ("xemacliteif_init: out of memory\r\n"));
return ERR_MEM;
}
xemac = mem_malloc(sizeof *xemac);
if (xemac == NULL) {
LWIP_DEBUGF(NETIF_DEBUG, ("xemacliteif_init: out of memory\r\n"));
return ERR_MEM;
}
xemacliteif = mem_malloc(sizeof *xemacliteif);
if (xemacliteif == NULL) {
LWIP_DEBUGF(NETIF_DEBUG, ("xemacliteif_init: out of memory\r\n"));
return ERR_MEM;
}
/* obtain pointer to topology structure for this emac */
xemac->topology_index = xtopology_find_index((unsigned)(netif->state));
xtopologyp = &xtopology[xemac->topology_index];
/* obtain config of this emaclite */
config = xemaclite_lookup_config((unsigned)(netif->state));
/* maximum transfer unit */
netif->mtu = XEL_MTU_SIZE;
/* broadcast capability */
netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
/* initialize the mac */
XEmacLite_Initialize(xemaclitep, config->DeviceId);
xemaclitep->NextRxBufferToUse = 0;
#if XLWIP_CONFIG_INCLUDE_EMACLITE_ON_ZYNQ == 1
XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
xtopologyp->intc_emac_intr,
(Xil_ExceptionHandler)XEmacLite_InterruptHandler,
xemaclitep);
XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
xtopologyp->intc_emac_intr,
EMACLITE_INTR_PRIORITY_SET_IN_GIC,
TRIG_TYPE_RISING_EDGE_SENSITIVE);
XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
xtopologyp->intc_emac_intr);
#else
#if NO_SYS
#if XPAR_INTC_0_HAS_FAST == 1
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xtopologyp->intc_emac_intr,
(XFastInterruptHandler)XEmacLite_FastInterruptHandler);
#else
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xtopologyp->intc_emac_intr,
(XInterruptHandler)XEmacLite_InterruptHandler,
xemaclitep);
#endif
#else
xPortInstallInterruptHandler( XPAR_INTC_0_EMACLITE_0_VEC_ID, ( XInterruptHandler ) XEmacLite_InterruptWrapper, xemaclitep );
vPortEnableInterrupt( XPAR_INTC_0_EMACLITE_0_VEC_ID );
#endif
#endif
/* set mac address */
XEmacLite_SetMacAddress(xemaclitep, (unsigned char*)(netif->hwaddr));
/* flush any frames already received */
XEmacLite_FlushReceive(xemaclitep);
/* set Rx, Tx interrupt handlers */
XEmacLite_SetRecvHandler(xemaclitep, (void *)(xemac), xemacif_recv_handler);
XEmacLite_SetSendHandler(xemaclitep, (void *)(xemac), xemacif_send_handler);
/* enable Rx, Tx interrupts */
XEmacLite_EnableInterrupts(xemaclitep);
#if !NO_SYS
sys_sem_new(&xemac->sem_rx_data_available, 0);
#endif
/* replace the state in netif (currently the base address of emaclite)
* with the xemacliteif instance pointer.
* this contains a pointer to the config table entry
*/
xemac->type = xemac_type_xps_emaclite;
xemac->state = (void *)xemacliteif;
netif->state = (void *)xemac;
xemacliteif->instance = xemaclitep;
xemacliteif->recv_q = pq_create_queue();
if (!xemacliteif->recv_q)
return ERR_MEM;
xemacliteif->send_q = pq_create_queue();
if (!xemacliteif->send_q)
return ERR_MEM;
/* Initialize PHY */
/* set PHY <--> MAC data clock */
#ifdef CONFIG_LINKSPEED_AUTODETECT
link_speed = get_IEEE_phy_speed_emaclite(xemaclitep);
xil_printf("auto-negotiated link speed: %d\r\n", link_speed);
#elif defined(CONFIG_LINKSPEED1000)
xil_printf("Link speed of 1000 Mbps not possible\r\n");
#elif defined(CONFIG_LINKSPEED100)
link_speed = 100;
configure_IEEE_phy_speed_emaclite(xemaclitep, link_speed);
xil_printf("link speed: %d\r\n", link_speed);
#elif defined(CONFIG_LINKSPEED10)
link_speed = 10;
configure_IEEE_phy_speed_emaclite(xemaclitep, link_speed);
xil_printf("link speed: %d\r\n", link_speed);
#endif
return ERR_OK;
}
XStatus init_axi_fifo(struct xemac_s *xemac)
{
xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
#if XPAR_INTC_0_HAS_FAST == 1
xaxiemacif_fast = xaxiemacif;
xemac_fast = xemac;
#endif
#if NO_SYS
struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
#endif
#ifdef OS_IS_FREERTOS
struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
#endif
/* initialize ll fifo */
XLlFifo_Initialize(&xaxiemacif->axififo,
XAxiEthernet_AxiDevBaseAddress(&xaxiemacif->axi_ethernet));
/* Clear any pending FIFO interrupts */
XLlFifo_IntClear(&xaxiemacif->axififo, XLLF_INT_ALL_MASK);
/* enable fifo interrupts */
XLlFifo_IntEnable(&xaxiemacif->axififo, XLLF_INT_ALL_MASK);
#if XLWIP_CONFIG_INCLUDE_AXIETH_ON_ZYNQ == 1
XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
xaxiemacif->axi_ethernet.Config.TemacIntr,
AXIETH_INTR_PRIORITY_SET_IN_GIC,
TRIG_TYPE_RISING_EDGE_SENSITIVE);
XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
AXIFIFO_INTR_PRIORITY_SET_IN_GIC,
TRIG_TYPE_RISING_EDGE_SENSITIVE);
XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
xaxiemacif->axi_ethernet.Config.TemacIntr);
XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr);
#else
#if NO_SYS
#if XPAR_INTC_0_HAS_FAST == 1
/* Register temac interrupt with interrupt controller */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XFastInterruptHandler)xaxiemac_fasterror_handler);
/* connect & enable FIFO interrupt */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XFastInterruptHandler)xllfifo_fastintr_handler);
#else
/* Register temac interrupt with interrupt controller */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
/* connect & enable FIFO interrupt */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
#endif
/* Enable EMAC interrupts in the interrupt controller */
do {
/* read current interrupt enable mask */
unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr + XIN_IER_OFFSET);
/* form new mask enabling SDMA & ll_temac interrupts */
cur_mask = cur_mask
| (1 << xaxiemacif->axi_ethernet.Config.AxiFifoIntr)
| (1 << xaxiemacif->axi_ethernet.Config.TemacIntr);
/* set new mask */
XIntc_EnableIntr(xtopologyp->intc_baseaddr, cur_mask);
} while (0);
#else
#ifdef OS_IS_XILKERNEL
/* connect & enable TEMAC interrupts */
register_int_handler(xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
enable_interrupt(xaxiemacif->axi_ethernet.Config.TemacIntr);
/* connect & enable FIFO interrupts */
register_int_handler(xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
enable_interrupt(xaxiemacif->axi_ethernet.Config.AxiFifoIntr);
#else
#if XPAR_INTC_0_HAS_FAST == 1
/* Register temac interrupt with interrupt controller */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XFastInterruptHandler)xaxiemac_fasterror_handler);
/* connect & enable FIFO interrupt */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XFastInterruptHandler)xllfifo_fastintr_handler);
#else
/* Register temac interrupt with interrupt controller */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
/* connect & enable FIFO interrupt */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
#endif
/* Enable EMAC interrupts in the interrupt controller */
do {
/* read current interrupt enable mask */
unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr + XIN_IER_OFFSET);
/* form new mask enabling SDMA & ll_temac interrupts */
cur_mask = cur_mask
| (1 << xaxiemacif->axi_ethernet.Config.AxiFifoIntr)
| (1 << xaxiemacif->axi_ethernet.Config.TemacIntr);
/* set new mask */
XIntc_EnableIntr(xtopologyp->intc_baseaddr, cur_mask);
} while (0);
#endif
#endif
#endif
return 0;
}
static err_t
low_level_init(struct netif *netif)
{
struct xemac_s *xemac;
XEmacLite_Config *config;
XEmacLite *xemaclitep;
struct xtopology_t *xtopologyp;
xemacliteif_s *xemacliteif;
xemaclitep = mem_malloc(sizeof *xemaclitep);
if (xemaclitep == NULL) {
LWIP_DEBUGF(NETIF_DEBUG, ("xemacliteif_init: out of memory\r\n"));
return ERR_MEM;
}
xemac = mem_malloc(sizeof *xemac);
if (xemac == NULL) {
LWIP_DEBUGF(NETIF_DEBUG, ("xemacliteif_init: out of memory\r\n"));
return ERR_MEM;
}
xemacliteif = mem_malloc(sizeof *xemacliteif);
if (xemac == NULL) {
LWIP_DEBUGF(NETIF_DEBUG, ("xemacliteif_init: out of memory\r\n"));
return ERR_MEM;
}
/* obtain pointer to topology structure for this emac */
xemac->topology_index = xtopology_find_index((unsigned)(netif->state));
xtopologyp = &xtopology[xemac->topology_index];
/* obtain config of this emaclite */
config = xemaclite_lookup_config((unsigned)(netif->state));
/* maximum transfer unit */
netif->mtu = XEL_MTU_SIZE;
/* broadcast capability */
netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
/* initialize the mac */
XEmacLite_Initialize(xemaclitep, config->DeviceId);
xemaclitep->NextRxBufferToUse = 0;
#if NO_SYS
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xtopologyp->intc_emac_intr,
(XInterruptHandler)XEmacLite_InterruptHandler,
xemaclitep);
#else
#include "xmk.h"
register_int_handler(xtopologyp->intc_emac_intr,
(XInterruptHandler)XEmacLite_InterruptHandler,
xemaclitep);
enable_interrupt(xtopologyp->intc_emac_intr);
#endif
/* set mac address */
XEmacLite_SetMacAddress(xemaclitep, (Xuint8*)(netif->hwaddr));
/* flush any frames already received */
XEmacLite_FlushReceive(xemaclitep);
/* set Rx, Tx interrupt handlers */
XEmacLite_SetRecvHandler(xemaclitep, (void *)(xemac), xemacif_recv_handler);
XEmacLite_SetSendHandler(xemaclitep, (void *)(xemac), xemacif_send_handler);
/* enable Rx, Tx interrupts */
XEmacLite_EnableInterrupts(xemaclitep);
#if !NO_SYS
xemac->sem_rx_data_available = sys_sem_new(0);
#endif
/* replace the state in netif (currently the base address of emaclite)
* with the xemacliteif instance pointer.
* this contains a pointer to the config table entry
*/
xemac->type = xemac_type_xps_emaclite;
xemac->state = (void *)xemacliteif;
netif->state = (void *)xemac;
xemacliteif->instance = xemaclitep;
xemacliteif->recv_q = pq_create_queue();
if (!xemacliteif->recv_q)
return ERR_MEM;
xemacliteif->send_q = pq_create_queue();
if (!xemacliteif->send_q)
return ERR_MEM;
return ERR_OK;
}
int main()
{
// Declare local variables and initialize global interrupt flag
Xuint32 i,j, numElements, numElementsParallel,temp1,temp2,slv_reg0;
Xuint32 DT_PeriphAddr, DT_InputRAM_AddrBase, DT_OutputRAM_AddrBase,DT_CoeffRAM_AddrBase;
DT_PeriphAddr = XPAR_DECISIONTREECLEAN_0_BASEADDR;
DT_InputRAM_AddrBase = XPAR_DECISIONTREECLEAN_0_MEM0_BASEADDR;
DT_OutputRAM_AddrBase = XPAR_DECISIONTREECLEAN_0_MEM1_BASEADDR;
DT_CoeffRAM_AddrBase = XPAR_DECISIONTREECLEAN_0_MEM2_BASEADDR;
volatile Xuint32 calcVal, temp, pseudo_intr;
interrupt_flag = 0;
////////////////////////////
// INTERRUPT INITIALIZATION
////////////////////////////
// // Initialize Interrupts on Microblaze
Xil_ExceptionInit();
// // Register the interrupt handler of the XPS Interrupt Controller with the Microblaze external interrupt
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (XExceptionHandler)XIntc_DeviceInterruptHandler,
(void *)XPAR_INTC_0_DEVICE_ID);
// // Register the DECISIONTREECLEAN interrupt handler in the vector table of the XPS Interrupt Controller
XIntc_RegisterHandler(XPAR_INTC_0_BASEADDR, XPAR_XPS_INTC_0_DECISIONTREECLEAN_0_IP2INTC_IRPT_INTR,
(XInterruptHandler)DECISIONTREECLEAN_Intr_DefaultHandler, (void *)XPAR_DECISIONTREECLEAN_0_BASEADDR);
// // Start the XPS Interrupt Controller
XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);
// // Enable DECISIONTREECLEAN interrupt requests in the XPS Interrupt Controller
XIntc_EnableIntr(XPAR_INTC_0_BASEADDR, XPAR_DECISIONTREECLEAN_0_IP2INTC_IRPT_MASK);
// // Local and global interrupt enable for the DECISIONTREECLEAN peripheral
DECISIONTREECLEAN_EnableInterrupt((Xuint32 *) XPAR_DECISIONTREECLEAN_0_BASEADDR);
// // Enable Microblaze non-critical (external) interrupts
Xil_ExceptionEnable();
////////////////////////////
// MAIN PROGRAM FUNCTIONS
////////////////////////////
// prepare the lookup table
DECISIONTREECLEAN_mWriteSlaveReg2(DT_PeriphAddr, 0, 0xffffffff); //for the RAM_ACCESS WE-- slv_reg2(31)
//Write the LUK UP tables
for (j=0; j< 8; j++)
{
DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4), 0x00010006 ); //00010000000000000110 );
DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(16*4),0x00000C06); //00000000110000000110 );
DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(16*4+4),0x00023411); //00100011010000010001 );
DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(32*4),0x00000C06); //00000000110000000110 );
DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(32*4+4), 0x00000C00); //00000000110000000000 );
DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(32*4+8),0x50004131); //01010100000100110001 );
DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(32*4+12),0x00033C11); //00110011110000010001 );
DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(48*4),0x00000C06); //00000000110000000110 );
DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(48*4+4),0x00020C00); //00100000110000000000 );
DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(48*4+8), 0x00000C00); //00000000110000000000 );
DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(48*4+12), 0x00033C11); //00110011110000010001 );
DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(48*4+16), 0x40004D31); //01000100110100110001 );
DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(48*4+20),0x000BA00F ); //10111010000000001111);
DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(48*4+24),0x00000000 ); //00000000000000000000 );
DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(48*4+28), 0x00000000); //00000000000000000000 );
}
// for ( i =0 ; i<19; i++)
// {
// temp1 =DECISIONTREECLEAN_mReadMemory(DT_CoeffRAM_AddrBase+i*4);
// printf("coeff_mem %lu\n", temp1);
// }
DECISIONTREECLEAN_mWriteSlaveReg2(DT_PeriphAddr, 0, 0x00000000); //for the RAM_ACCESS WE-- slv_reg2(31)
// Store the number of xyz samples we are going to process - do this for compatibility
scanf("%lu", &numElements);
// First loop stores all xyz samples into the source buffer
for (i=0; i < numElements; i++)
{
scanf("%x", &temp);
DECISIONTREECLEAN_mWriteMemory(DT_InputRAM_AddrBase + i*4, temp);// written to the memory controller
}
// temp2 =DECISIONTREECLEAN_mReadMemory(DT_InputRAM_AddrBase);
// printf("input_ram=%lu\n", temp2);
// Wait for a bit for LabView to catch up
//for (i=0; i < 10000; i++);
// Set up the DECISIONTREECLEAN module
numElementsParallel = ceil(numElements / 8) - 1;
DECISIONTREECLEAN_mWriteSlaveReg1(DT_PeriphAddr, 0, numElementsParallel);
// Start the DECISIONTREECLEAN module processing the samples
DECISIONTREECLEAN_mWriteSlaveReg0(DT_PeriphAddr, 0, 0x1); // go bit
// slv_reg0= DECISIONTREECLEAN_mReadSlaveReg0(DT_PeriphAddr, 0);
// printf("slv_reg0 %lu\n", slv_reg0);
//printf("we reached before interrupt");
// Wait for DECISIONTREECLEAN to finish
while (interrupt_flag == 0);
// pseudo_intr= DECISIONTREECLEAN_mReadSlaveReg5(DT_PeriphAddr, 0);
// printf("psi-%lu\n",pseudo_intr);
// After completion of operations, store the calculation time required and clear counter
//if (pseudo_intr == 1 )
//{
//printf("we reached after interrupt\n");
calcVal = DECISIONTREECLEAN_mReadSlaveReg7(DT_PeriphAddr, 0);
DECISIONTREECLEAN_mWriteSlaveReg6(DT_PeriphAddr, 0, 0xffffffff);
// Transmit results of calculation, plus the count value from the calculation timer
temp = numElements + 1;
printf("%u\n", temp);
for (i=0; i < (numElementsParallel+1); i++) {
temp = DECISIONTREECLEAN_mReadMemory(DT_OutputRAM_AddrBase + i*4);
printf("%u\n", temp);
}
printf("%u\n", calcVal);
//}
return 0;
}
int main (void)
{
XGpio dip;
int dip_check;
static XPs2 Ps2Inst;
XPs2_Config *ConfigPtr;
u32 StatusReg;
u32 BytesReceived;
u8 RxBuffer;
int key_count=0;
int i;
status=PVP;
int x_cur=7, y_cur=7, x_pos=0, y_pos=0;
XGpio_Initialize(&dip, XPAR_DIP_SWITCHES_8BITS_DEVICE_ID);
XGpio_SetDataDirection(&dip, 1, 0xffffffff);
ConfigPtr = XPs2_LookupConfig(XPAR_XPS_PS2_0_0_DEVICE_ID);
XPs2_CfgInitialize(&Ps2Inst, ConfigPtr, ConfigPtr->BaseAddress);
XIntc_RegisterHandler(XPAR_XPS_INTC_0_BASEADDR,
XPAR_XPS_INTC_0_XPS_TIMER_0_INTERRUPT_INTR,
(XInterruptHandler) timer_int_handler,
(void *)XPAR_XPS_TIMER_0_BASEADDR);
XIntc_MasterEnable(XPAR_XPS_INTC_0_BASEADDR);
XIntc_EnableIntr(XPAR_XPS_INTC_0_BASEADDR, 0x1);
XTmrCtr_SetLoadReg(XPAR_XPS_TIMER_0_BASEADDR, 0, 333333);
XTmrCtr_SetControlStatusReg(XPAR_XPS_TIMER_0_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );
XIntc_EnableIntr(XPAR_XPS_TIMER_0_BASEADDR, XPAR_XPS_TIMER_0_INTERRUPT_MASK);
XTmrCtr_SetControlStatusReg(XPAR_XPS_TIMER_0_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK |
XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK);
microblaze_enable_interrupts();
InitializeGame(x_cur, y_cur);status=PVP;
xil_printf("-- Game Starts! --\r\n");
xil_printf("\r\nHuman Player's turn!\r\n");
int vga_input;
vga_input=(0<<24)+(0<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(1<<24)+(0<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(2<<24)+(0<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(3<<24)+(0<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(4<<24)+(0<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(5<<24)+(0<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(6<<24)+(0<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(7<<24)+(0<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(8<<24)+(0<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(0<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(0<<24)+(17<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(1<<24)+(17<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(2<<24)+(17<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(3<<24)+(17<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(4<<24)+(17<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(5<<24)+(17<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(6<<24)+(17<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(7<<24)+(17<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(8<<24)+(17<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(17<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(0<<24)+(29<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(1<<24)+(29<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(2<<24)+(29<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(3<<24)+(29<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(4<<24)+(29<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(5<<24)+(29<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(6<<24)+(29<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(7<<24)+(29<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(8<<24)+(29<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(29<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(0<<24)+(8<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(1<<24)+(8<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(2<<24)+(8<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(3<<24)+(8<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(4<<24)+(8<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(5<<24)+(8<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(6<<24)+(8<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(7<<24)+(8<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(8<<24)+(8<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(8<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(1<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(2<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(3<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(4<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(5<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(6<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(7<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(8<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(9<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(10<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(11<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(12<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(13<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(14<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(15<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(16<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(17<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(18<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(19<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(20<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(21<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(22<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(23<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(24<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(25<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(26<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(27<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(28<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(29<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
vga_input=(9<<24)+(30<<16)+(1<<8)+3;
VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
while (1)
{
if (turn==HUMAN_PLAYER || (turn==COMPUTER_PLAYER && status==PVP)) {
do {
if (turn==COMPUTER_PLAYER && status==PVC)
break;
dip_check=XGpio_DiscreteRead(&dip, 1);
StatusReg = XPs2_GetStatus(&Ps2Inst);
}while((StatusReg & XPS2_STATUS_RX_FULL) == 0);
BytesReceived = XPs2_Recv(&Ps2Inst, &RxBuffer, 1);
key_count=(key_count+1)%3;
if (key_count==0) {
if (RxBuffer==0x21&& win_flag==0) {
DrawNumber(level,3,2,EMPTY);
if(level==1)
level=2;
else
level=1;
if(status==PVC )
DrawNumber(level,3,2,0);
else if(status==CVP)
DrawNumber(level,3,2,1);
else
DrawNumber(level,3,2,EMPTY);
}
if (RxBuffer==0x1D && win_flag==0) {
EraseCursor(x_cur, y_cur);
if (y_cur<=0)
y_cur=14;
else
y_cur--;
DrawChess(x_cur, y_cur, CURSOR);
}
if (RxBuffer==0x1B && win_flag==0) {
EraseCursor(x_cur, y_cur);
if (y_cur>=14)
y_cur=0;
else
y_cur++;
DrawChess(x_cur, y_cur, CURSOR);
}
if (RxBuffer==0x1C && win_flag==0) {
EraseCursor(x_cur, y_cur);
if (x_cur<=0)
x_cur=14;
else
x_cur--;
DrawChess(x_cur, y_cur, CURSOR);
}
if (RxBuffer==0x23 && win_flag==0) {
EraseCursor(x_cur, y_cur);
if (x_cur>=14)
x_cur=0;
else
x_cur++;
DrawChess(x_cur, y_cur, CURSOR);
}
if (RxBuffer==0x5A && win_flag==0) {
DrawBack(3,1119,EMPTY);
if (board_state[x_cur][y_cur]==EMPTY) {
if(status==CVP)
DrawChess(x_cur, y_cur, 1-turn);
else
DrawChess(x_cur, y_cur, turn);
board_state[x_cur][y_cur]=turn;
board_record[BackTimes].x=x_cur;
board_record[BackTimes].y=y_cur;
BackTimes++;
count=0;
time0=0;
if (turn==COMPUTER_PLAYER)
step_flag=1;
if (CheckWin(x_cur,y_cur,turn)==1) {
xil_printf("\r\nHuman Player wins!\r\n");
win_flag=1;
DrawWinning(0, 1, EMPTY);
if(status==CVP)
DrawWinning(0, 1, 1-turn);
else
DrawWinning(0, 1, turn);
}
if (CheckBan(x_cur,y_cur,turn)==1){
xil_printf("\r\nComputer Player wins!\r\n");
win_flag=1;
DrawWinning(0, 1, EMPTY);
if(status==CVP)
DrawWinning(0, 1, turn);
else
DrawWinning(0, 1, 1-turn);
}
else {
if (turn==HUMAN_PLAYER)
turn=COMPUTER_PLAYER;
else
turn=HUMAN_PLAYER;
xil_printf("\r\nComputer Player's turn!\r\n");
}
}
}
if (RxBuffer==0x29 && turn==HUMAN_PLAYER && win_flag==0) {
count=0;time0=0;
if (status==PVP) {
x_cur=7;
y_cur=7;
for (i=0; i<256; i++) {
board_record[i].x=0;
board_record[i].y=0;
}
InitializeGame(x_cur, y_cur);status=PVP;
DrawStatus(1, 21, EMPTY,status);
status=PVC;
DrawNumber(level,3,2,0);
DrawStatus(1, 21, COMPUTER_PLAYER,status);
}
else if(status==PVC) {
x_cur=7;
y_cur=7;
for (i=0; i<256; i++) {
board_record[i].x=0;
board_record[i].y=0;
}
InitializeGame(x_cur, y_cur);status=PVP;
DrawStatus(1, 21, EMPTY,status);
status=CVP;
DrawNumber(level,3,2,1);
DrawStatus(1, 21, COMPUTER_PLAYER,status);
turn=COMPUTER_PLAYER;
}
else if(status==CVP) {
x_cur=7;
y_cur=7;
for (i=0; i<256; i++) {
board_record[i].x=0;
board_record[i].y=0;
}
InitializeGame(x_cur, y_cur);status=PVP;
DrawStatus(1, 21, EMPTY,status);
status=PVP;
DrawStatus(1, 21, COMPUTER_PLAYER,status);
}
}
if (RxBuffer==0x76) {
x_cur=7;
y_cur=7;
for (i=0; i<256; i++) {
board_record[i].x=0;
board_record[i].y=0;
}
InitializeGame(x_cur, y_cur);status=PVP;
}
if (RxBuffer==0x2D) {
if(BackTimes>0){
BackTimes--;
x_cur=board_record[BackTimes].x;
y_cur=board_record[BackTimes].y;
board_state[x_cur][y_cur]=EMPTY;
DrawChess(x_cur,y_cur,EMPTY);
turn=1-turn;
if(status==PVC)
{
BackTimes--;
x_cur=board_record[BackTimes].x;
y_cur=board_record[BackTimes].y;
board_state[x_cur][y_cur]=EMPTY;
DrawChess(x_cur,y_cur,EMPTY);
turn=HUMAN_PLAYER;
}
DrawBack(3,1119,turn);
}
}
}
}
if (turn==COMPUTER_PLAYER && (status==PVC ||status==CVP )&& win_flag==0) {
if (step_flag==0) {
if (x_cur-1<0)
x_pos=x_cur+1;
else
x_pos=x_cur-1;
y_pos=y_cur;
step_flag=1;
}
else {
if(level==2||level==3){
EvaluateComputerMove(board_state, 0, MIN_INFINITY, MAX_INFINITY, 0, 0);
x_pos=maxMoveX;
y_pos=maxMoveY;
xil_printf("\r\n computer \r\n");}
else
{
everyScore(Computer);
current_pos=best(Computer);
x_pos=current_pos.y;
y_pos=current_pos.x;
xil_printf("\r\n computer \r\n");
}
}
xil_printf("\r\n%x, %x\r\n", x_pos, y_pos);
if(status==CVP)
DrawChess(x_pos, y_pos, 1-turn);
else
DrawChess(x_pos, y_pos, turn);
board_state[x_pos][y_pos]=COMPUTER_PLAYER;
board_record[BackTimes].x=x_pos;
board_record[BackTimes].y=y_pos;
BackTimes++;
count=0;
time0=0;
if (CheckWin(x_pos, y_pos, turn)) {
xil_printf("\r\nComputer Player wins!\r\n");
win_flag=1;
DrawWinning(0,1, EMPTY);
if(status==CVP)
DrawWinning(0,1, 1-turn);
else
DrawWinning(0,1, turn);
turn=HUMAN_PLAYER;
}
else {
turn=HUMAN_PLAYER;
xil_printf("\r\nHuman Player's turn!\r\n");
}
}
}
return 0;
}
XStatus init_axi_fifo(struct xemac_s *xemac)
{
xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
#if XPAR_INTC_0_HAS_FAST == 1
xaxiemacif_fast = xaxiemacif;
xemac_fast = xemac;
#endif
#if NO_SYS
struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
#endif
/* initialize ll fifo */
XLlFifo_Initialize(&xaxiemacif->axififo,
XAxiEthernet_AxiDevBaseAddress(&xaxiemacif->axi_ethernet));
/* Clear any pending FIFO interrupts */
XLlFifo_IntClear(&xaxiemacif->axififo, XLLF_INT_ALL_MASK);
/* enable fifo interrupts */
XLlFifo_IntEnable(&xaxiemacif->axififo, XLLF_INT_ALL_MASK);
#if NO_SYS
#if XPAR_INTC_0_HAS_FAST == 1
/* Register temac interrupt with interrupt controller */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XFastInterruptHandler)xaxiemac_fasterror_handler);
/* connect & enable FIFO interrupt */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XFastInterruptHandler)xllfifo_fastintr_handler);
#else
/* Register temac interrupt with interrupt controller */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
/* connect & enable FIFO interrupt */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
#endif
/* Enable EMAC interrupts in the interrupt controller */
do {
/* read current interrupt enable mask */
unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr + XIN_IER_OFFSET);
/* form new mask enabling SDMA & ll_temac interrupts */
cur_mask = cur_mask
| (1 << xaxiemacif->axi_ethernet.Config.AxiFifoIntr)
| (1 << xaxiemacif->axi_ethernet.Config.TemacIntr);
/* set new mask */
XIntc_EnableIntr(xtopologyp->intc_baseaddr, cur_mask);
} while (0);
#else
/* connect & enable TEMAC interrupts */
register_int_handler(xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
enable_interrupt(xaxiemacif->axi_ethernet.Config.TemacIntr);
/* connect & enable FIFO interrupts */
register_int_handler(xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
enable_interrupt(xaxiemacif->axi_ethernet.Config.AxiFifoIntr);
#endif
return 0;
}
//------------------------------------------------------------------------------
tHostifReturn hostif_sysIrqRegHandler(tHostifIrqCb pfnIrqCb_p, void* pArg_p)
{
XIntc_RegisterHandler(HOSTIF_IRQ_IC_ID, HOSTIF_IRQ, pfnIrqCb_p, pArg_p);
return kHostifSuccessful;
}
tEplKernel PUBLIC EplTimerSynckAddInstance (void)
{
tEplKernel Ret = kEplSuccessful;
EPL_MEMSET(&EplTimerSynckInstance_l, 0, sizeof (EplTimerSynckInstance_l));
EplTimerSynckDrvCompareInterruptDisable();
EplTimerSynckDrvSetCompareValue( 0 );
#ifdef EPL_TIMER_USE_COMPARE_PDI_INT
EplTimerSynckDrvCompareTogPdiInterruptDisable();
EplTimerSynckDrvSetCompareTogPdiValue( 0 );
#endif //EPL_TIMER_USE_COMPARE_PDI_INT
#ifdef __NIOS2__
if (alt_ic_isr_register(EPL_TIMER_SYNC_IRQ_IC_ID, EPL_TIMER_SYNC_IRQ,
EplTimerSynckDrvInterruptHandler, NULL, NULL))
{
Ret = kEplNoResource;
}
#elif defined(__MICROBLAZE__)
{
DWORD curIntEn = TSYN_RD32(EPL_TIMER_INTC_BASE, XIN_IER_OFFSET);
XIntc_RegisterHandler(EPL_TIMER_INTC_BASE, EPL_TIMER_SYNC_IRQ,
(XInterruptHandler)EplTimerSynckDrvInterruptHandler, (void*)NULL);
XIntc_EnableIntr(EPL_TIMER_INTC_BASE, EPL_TIMER_SYNC_IRQ_MASK | curIntEn);
}
#else
#error"Configuration unknown!"
#endif
return Ret;
}
