XStatus
init_ll_fifo(struct xemac_s *xemac)
{
xlltemacif_s *xlltemacif = (xlltemacif_s *)(xemac->state);
#if NO_SYS
struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
#endif
/* initialize ll fifo */
XLlFifo_Initialize(&xlltemacif->llfifo,
XLlTemac_LlDevBaseAddress(&xlltemacif->lltemac));
/* Clear any pending FIFO interrupts */
XLlFifo_IntClear(&xlltemacif->llfifo, XLLF_INT_ALL_MASK);
/* enable fifo interrupts */
XLlFifo_IntEnable(&xlltemacif->llfifo, XLLF_INT_ALL_MASK);
#if NO_SYS
/* Register temac interrupt with interrupt controller */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xlltemacif->lltemac.Config.TemacIntr,
(XInterruptHandler)xlltemac_error_handler,
&xlltemacif->lltemac);
/* connect & enable FIFO interrupt */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xlltemacif->lltemac.Config.LLFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
/* Enable EMAC interrupts in the interrupt controller */
do {
/* read current interrupt enable mask */
unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr + XIN_IER_OFFSET);
/* form new mask enabling SDMA & ll_temac interrupts */
cur_mask = cur_mask
| (1 << xlltemacif->lltemac.Config.LLFifoIntr)
| (1 << xlltemacif->lltemac.Config.TemacIntr);
/* set new mask */
XIntc_mEnableIntr(xtopologyp->intc_baseaddr, cur_mask);
} while (0);
#else
/* connect & enable TEMAC interrupts */
register_int_handler(xlltemacif->lltemac.Config.TemacIntr,
(XInterruptHandler)xlltemac_error_handler,
&xlltemacif->lltemac);
enable_interrupt(xlltemacif->lltemac.Config.TemacIntr);
/* connect & enable FIFO interrupts */
register_int_handler(xlltemacif->lltemac.Config.LLFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
enable_interrupt(xlltemacif->lltemac.Config.LLFifoIntr);
#endif
return 0;
}
/**
*
* This function demonstrates the usage of the TEMAC by sending and receiving
* frames in polled mode.
*
*
* @param TemacDeviceId is device ID of the Temac Device , typically
* XPAR_<TEMAC_instance>_DEVICE_ID value from xparameters.h
*
* @return XST_SUCCESS to indicate success, otherwise XST_FAILURE
*
* @note None.
*
******************************************************************************/
int TemacPolledExample(u16 TemacDeviceId, u16 FifoDeviceId)
{
int Status;
XLlTemac_Config *MacCfgPtr;
u32 Rdy;
int LoopbackSpeed;
/*************************************/
/* Setup device for first-time usage */
/*************************************/
/*
* Initialize the FIFO and TEMAC instance
*/
MacCfgPtr = XLlTemac_LookupConfig(TemacDeviceId);
Status = XLlTemac_CfgInitialize(&TemacInstance, MacCfgPtr,
MacCfgPtr->BaseAddress);
if (Status != XST_SUCCESS) {
TemacUtilErrorTrap("Error in initialize");
return XST_FAILURE;
}
XLlFifo_Initialize(&FifoInstance,
XLlTemac_LlDevBaseAddress(&TemacInstance));
/*
* Check whether the IPIF interface is correct for this example
*/
if (!XLlTemac_IsFifo(&TemacInstance)) {
TemacUtilErrorTrap
("Device HW not configured for FIFO direct mode\r\n");
return XST_FAILURE;
}
/*
* Set the MAC address
*/
Status = XLlTemac_SetMacAddress(&TemacInstance, (u8 *) TemacMAC);
if (Status != XST_SUCCESS) {
TemacUtilErrorTrap("Error setting MAC address");
return XST_FAILURE;
}
/* Make sure the hard temac is ready */
Rdy = XLlTemac_ReadReg(TemacInstance.Config.BaseAddress,
XTE_RDY_OFFSET);
while ((Rdy & XTE_RDY_HARD_ACS_RDY_MASK) == 0) {
Rdy = XLlTemac_ReadReg(TemacInstance.Config.BaseAddress,
XTE_RDY_OFFSET);
}
/*
* Set PHY to loopback, speed depends on phy type.
* MII is 100 and all others are 1000.
*/
if (XLlTemac_GetPhysicalInterface(&TemacInstance) == XTE_PHY_TYPE_MII)
{
LoopbackSpeed = TEMAC_LOOPBACK_SPEED;
} else {
LoopbackSpeed = TEMAC_LOOPBACK_SPEED_1G;
}
Status = TemacUtilEnterLoopback(&TemacInstance, LoopbackSpeed);
if (Status != XST_SUCCESS) {
TemacUtilErrorTrap("Error setting the PHY loopback");
return XST_FAILURE;
}
/*
* Set PHY<-->MAC data clock
*/
XLlTemac_SetOperatingSpeed(&TemacInstance, (u16)LoopbackSpeed);
/*
* Setting the operating speed of the MAC needs a delay. There
* doesn't seem to be register to poll, so please consider this
* during your application design.
*/
TemacUtilPhyDelay(2);
/****************************/
/* Run through the examples */
/****************************/
/*
* Run the Single Frame polled example
*/
Status = TemacSingleFramePolledExample();
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Run the Multiple Frames polled example
*/
Status = TemacMultipleFramesPolledExample();
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return XST_SUCCESS;
}
XStatus init_axi_fifo(struct xemac_s *xemac)
{
xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
#if XPAR_INTC_0_HAS_FAST == 1
xaxiemacif_fast = xaxiemacif;
xemac_fast = xemac;
#endif
#if NO_SYS
struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
#endif
#ifdef OS_IS_FREERTOS
struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
#endif
/* initialize ll fifo */
XLlFifo_Initialize(&xaxiemacif->axififo,
XAxiEthernet_AxiDevBaseAddress(&xaxiemacif->axi_ethernet));
/* Clear any pending FIFO interrupts */
XLlFifo_IntClear(&xaxiemacif->axififo, XLLF_INT_ALL_MASK);
/* enable fifo interrupts */
XLlFifo_IntEnable(&xaxiemacif->axififo, XLLF_INT_ALL_MASK);
#if XLWIP_CONFIG_INCLUDE_AXIETH_ON_ZYNQ == 1
XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
XScuGic_RegisterHandler(xtopologyp->scugic_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
xaxiemacif->axi_ethernet.Config.TemacIntr,
AXIETH_INTR_PRIORITY_SET_IN_GIC,
TRIG_TYPE_RISING_EDGE_SENSITIVE);
XScuGic_SetPriTrigTypeByDistAddr(INTC_DIST_BASE_ADDR,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
AXIFIFO_INTR_PRIORITY_SET_IN_GIC,
TRIG_TYPE_RISING_EDGE_SENSITIVE);
XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
xaxiemacif->axi_ethernet.Config.TemacIntr);
XScuGic_EnableIntr(INTC_DIST_BASE_ADDR,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr);
#else
#if NO_SYS
#if XPAR_INTC_0_HAS_FAST == 1
/* Register temac interrupt with interrupt controller */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XFastInterruptHandler)xaxiemac_fasterror_handler);
/* connect & enable FIFO interrupt */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XFastInterruptHandler)xllfifo_fastintr_handler);
#else
/* Register temac interrupt with interrupt controller */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
/* connect & enable FIFO interrupt */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
#endif
/* Enable EMAC interrupts in the interrupt controller */
do {
/* read current interrupt enable mask */
unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr + XIN_IER_OFFSET);
/* form new mask enabling SDMA & ll_temac interrupts */
cur_mask = cur_mask
| (1 << xaxiemacif->axi_ethernet.Config.AxiFifoIntr)
| (1 << xaxiemacif->axi_ethernet.Config.TemacIntr);
/* set new mask */
XIntc_EnableIntr(xtopologyp->intc_baseaddr, cur_mask);
} while (0);
#else
#ifdef OS_IS_XILKERNEL
/* connect & enable TEMAC interrupts */
register_int_handler(xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
enable_interrupt(xaxiemacif->axi_ethernet.Config.TemacIntr);
/* connect & enable FIFO interrupts */
register_int_handler(xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
enable_interrupt(xaxiemacif->axi_ethernet.Config.AxiFifoIntr);
#else
#if XPAR_INTC_0_HAS_FAST == 1
/* Register temac interrupt with interrupt controller */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XFastInterruptHandler)xaxiemac_fasterror_handler);
/* connect & enable FIFO interrupt */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XFastInterruptHandler)xllfifo_fastintr_handler);
#else
/* Register temac interrupt with interrupt controller */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
/* connect & enable FIFO interrupt */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
#endif
/* Enable EMAC interrupts in the interrupt controller */
do {
/* read current interrupt enable mask */
unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr + XIN_IER_OFFSET);
/* form new mask enabling SDMA & ll_temac interrupts */
cur_mask = cur_mask
| (1 << xaxiemacif->axi_ethernet.Config.AxiFifoIntr)
| (1 << xaxiemacif->axi_ethernet.Config.TemacIntr);
/* set new mask */
XIntc_EnableIntr(xtopologyp->intc_baseaddr, cur_mask);
} while (0);
#endif
#endif
#endif
return 0;
}
/**
*
* This function demonstrates the usage Traffic Generator
* It does the following:
* - Set up the output terminal if UART16550 is in the hardware build
* - Initialize the AXI Traffic Generator device
* - Initialize the Streaming FIFO device
* - Set the Desired Transfer Count and Transfer Length
* - Enable the Traffic Genration on the Core
* - Check for the Streaming data on the FIFO
* - Return test status and exit
*
* @param InstancePtr is a pointer to the instance of the
* XTrafGen component.
* @param DeviceId is Device ID of the Axi Traffic Generator Device,
*
*
* @param InstancePtr is a pointer to the instance of the
* XTrafGen component.
* @param DeviceId is Device ID of the Axi Traffic Generator Device,
* typically XPAR_<TRAFGEN_instance>_DEVICE_ID value from
* xparameters.h.
*
* @return -XST_SUCCESS to indicate success
* -XST_FAILURE to indicate failure
*
******************************************************************************/
int XTrafGenStremingModeMasterExample(XTrafGen *InstancePtr, u16 DeviceId)
{
XTrafGen_Config *Config;
int Status = XST_SUCCESS;
u32 Len;
u32 TransferCnt;
u32 AtgPacket;
u32 FifoOcy;
u32 FifoLen;
/* Initial setup for Uart16550 */
#ifdef XPAR_UARTNS550_0_BASEADDR
Uart550_Setup();
#endif
/* Initialize the Device Configuration Interface driver */
Config = XTrafGen_LookupConfig(DeviceId);
if (!Config) {
xil_printf("No config found for %d\r\n", DeviceId);
return XST_FAILURE;
}
/*
* This is where the virtual address would be used, this example
* uses physical address.
*/
Status = XTrafGen_CfgInitialize(InstancePtr, Config,
Config->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("Initialization failed\n\r");
return Status;
}
/* Check for the Streaming Mode */
if(InstancePtr->OperatingMode != XTG_MODE_STREAMING) {
return XST_FAILURE;
}
/* Initialize the Fifo Instance */
XLlFifo_Initialize(&XLlFifoInstance , STR_FIFO0_ADDR);
Status = XLlFifo_Status(&XLlFifoInstance);
XLlFifo_IntClear(&XLlFifoInstance,0xffffffff);
Status = XLlFifo_Status(&XLlFifoInstance);
if(Status != 0x0) {
xil_printf("\n ERROR : Reset value of ISR0 : 0x%x\t"
"Expected : 0x0\n\r",
XLlFifo_Status(&XLlFifoInstance));
return XST_FAILURE;
}
/*
* Set the Required trasaction length
* and required transaction count
*/
XTrafGen_ResetStreamingRandomLen(InstancePtr);
XTrafGen_SetStreamingTransLen(InstancePtr , 3);
XTrafGen_SetStreamingTransCnt(InstancePtr , 2);
Len = XTrafGen_GetStreamingTransLen(InstancePtr);
TransferCnt = XTrafGen_GetStreamingTransCnt(InstancePtr);
/*
* Calculate the ATG data that is sent on the
* CORE when Streaming is Enabled
*/
AtgPacket = (Len +1) * TransferCnt;
/* Enable the traffic genration */
XTrafGen_StreamEnable(InstancePtr);
FifoOcy = XLlFifo_iRxOccupancy(&XLlFifoInstance);
if(FifoOcy != AtgPacket) {
xil_printf("\n ERROR : Not received complete packets : 0x%x \t"
"Expected : 0x%x \n\r",
XLlFifo_iRxOccupancy(&XLlFifoInstance), AtgPacket);
return XST_FAILURE;
}
FifoLen = XLlFifo_iRxGetLen(&XLlFifoInstance);
if(FifoLen != (AtgPacket*4/TransferCnt)) {
xil_printf("\n ERROR : Not received complete bytes : 0x%x \t"
"Expected : 0x%x \n\n\r",
XLlFifo_iRxGetLen(&XLlFifoInstance),Len);
return XST_FAILURE;
}
while(XLlFifo_iRxGetLen(&XLlFifoInstance)) {
xil_printf("Recived packet DATA: 0x%x \n\r",
XLlFifo_RxGetWord(&XLlFifoInstance));
}
if(XLlFifo_iRxOccupancy(&XLlFifoInstance) != 0) {
xil_printf("\n ERROR : RDFO is not becoming Empty : 0x%x \t"
"Expected : 0x0 \n\n\r",
XLlFifo_iRxOccupancy(&XLlFifoInstance));
return XST_FAILURE;
}
if(XLlFifo_iRxGetLen(&XLlFifoInstance) != 0) {
xil_printf("\n ERROR : RLR is not becoming Empty : 0x%x \t"
"Expected : 0x0 \n\n\r",
XLlFifo_iRxGetLen(&XLlFifoInstance));
return XST_FAILURE;
}
return XST_SUCCESS;
}
XStatus init_axi_fifo(struct xemac_s *xemac)
{
xaxiemacif_s *xaxiemacif = (xaxiemacif_s *)(xemac->state);
#if XPAR_INTC_0_HAS_FAST == 1
xaxiemacif_fast = xaxiemacif;
xemac_fast = xemac;
#endif
#if NO_SYS
struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
#endif
/* initialize ll fifo */
XLlFifo_Initialize(&xaxiemacif->axififo,
XAxiEthernet_AxiDevBaseAddress(&xaxiemacif->axi_ethernet));
/* Clear any pending FIFO interrupts */
XLlFifo_IntClear(&xaxiemacif->axififo, XLLF_INT_ALL_MASK);
/* enable fifo interrupts */
XLlFifo_IntEnable(&xaxiemacif->axififo, XLLF_INT_ALL_MASK);
#if NO_SYS
#if XPAR_INTC_0_HAS_FAST == 1
/* Register temac interrupt with interrupt controller */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XFastInterruptHandler)xaxiemac_fasterror_handler);
/* connect & enable FIFO interrupt */
XIntc_RegisterFastHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XFastInterruptHandler)xllfifo_fastintr_handler);
#else
/* Register temac interrupt with interrupt controller */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
/* connect & enable FIFO interrupt */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
#endif
/* Enable EMAC interrupts in the interrupt controller */
do {
/* read current interrupt enable mask */
unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr + XIN_IER_OFFSET);
/* form new mask enabling SDMA & ll_temac interrupts */
cur_mask = cur_mask
| (1 << xaxiemacif->axi_ethernet.Config.AxiFifoIntr)
| (1 << xaxiemacif->axi_ethernet.Config.TemacIntr);
/* set new mask */
XIntc_EnableIntr(xtopologyp->intc_baseaddr, cur_mask);
} while (0);
#else
/* connect & enable TEMAC interrupts */
register_int_handler(xaxiemacif->axi_ethernet.Config.TemacIntr,
(XInterruptHandler)xaxiemac_error_handler,
&xaxiemacif->axi_ethernet);
enable_interrupt(xaxiemacif->axi_ethernet.Config.TemacIntr);
/* connect & enable FIFO interrupts */
register_int_handler(xaxiemacif->axi_ethernet.Config.AxiFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
enable_interrupt(xaxiemacif->axi_ethernet.Config.AxiFifoIntr);
#endif
return 0;
}
