void Clock::init(Clock::Frequency freq) {
XMC_SCU_CLOCK_CONFIG_t config;
config.pclk_src = XMC_SCU_CLOCK_PCLKSRC_MCLK;
config.rtc_src = XMC_SCU_CLOCK_RTCCLKSRC_DCO2;
config.fdiv = 0;
config.idiv = freq;
XMC_SCU_CLOCK_Init(&config);
}
/**
* @brief Function to initialize the Clock Tree based on UI configuration
* @note -
* @param None
* @retval None
*/
void SystemCoreClockSetup(void)
{
/* Local data structure for initializing the clock functional block */
const XMC_SCU_CLOCK_CONFIG_t CLOCK_XMC4_0_CONFIG =
{
.syspll_config.n_div = 80U,
.syspll_config.p_div = 2U,
.syspll_config.k_div = 4U,
.syspll_config.mode = XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL,
.syspll_config.clksrc = XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP,
.enable_oschp = true,
.enable_osculp = false,
.calibration_mode = XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY,
.fstdby_clksrc = XMC_SCU_HIB_STDBYCLKSRC_OSI,
.fsys_clksrc = XMC_SCU_CLOCK_SYSCLKSRC_PLL,
.fsys_clkdiv = 1U,
.fcpu_clkdiv = 1U,
.fccu_clkdiv = 1U,
.fperipheral_clkdiv = 1U
};
/* Initialize the SCU clock */
XMC_SCU_CLOCK_Init(&CLOCK_XMC4_0_CONFIG);
/* RTC source clock */
XMC_SCU_HIB_SetRtcClockSource(XMC_SCU_HIB_RTCCLKSRC_OSI);
/* USB/SDMMC source clock */
XMC_SCU_CLOCK_SetUsbClockSource(XMC_SCU_CLOCK_USBCLKSRC_USBPLL);
/* USB/SDMMC divider setting */
XMC_SCU_CLOCK_SetUsbClockDivider(4U);
/* Start USB PLL */
XMC_SCU_CLOCK_StartUsbPll(1U, 32U);
/* WDT source clock */
XMC_SCU_CLOCK_SetWdtClockSource(XMC_SCU_CLOCK_WDTCLKSRC_OFI);
/* WDT divider setting */
XMC_SCU_CLOCK_SetWdtClockDivider(1U);
/* EBU divider setting */
XMC_SCU_CLOCK_SetEbuClockDivider(1U);
}
