/* API to disable the POSIF module */
void XMC_POSIF_Disable(XMC_POSIF_t *const peripheral)
{
if (peripheral == POSIF0)
{
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF0);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF0);
#endif
}
#if defined(POSIF1)
else if (peripheral == POSIF1)
{
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF1);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF1);
#endif
}
#endif
else
{
XMC_ASSERT("XMC_POSIF_Disable:Invalid module pointer", 0);
}
}
__STATIC_INLINE void XMC_CCU4_lAssertReset(const XMC_CCU4_MODULE_t *const module)
{
switch ((uint32_t)module)
{
case (uint32_t)CCU40:
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU40);
break;
#if defined(CCU41)
case (uint32_t)CCU41:
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU41);
break;
#endif
#if defined(CCU42)
case (uint32_t)CCU42:
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU42);
break;
#endif
#if defined(CCU43)
case (uint32_t)CCU43:
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_CCU43);
break;
#endif
default:
XMC_ASSERT("XMC_CCU4_lAssertReset:Invalid Module Pointer", 0);
break;
}
}
/* API to disable the POSIF module */
void XMC_POSIF_Disable(XMC_POSIF_t *const peripheral)
{
switch ((uint32_t)peripheral)
{
case (uint32_t)POSIF0:
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF0);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF0);
#endif
break;
#if defined(POSIF1)
case (uint32_t)POSIF1:
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF1);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF1);
#endif
break;
#endif
default:
XMC_ASSERT("XMC_POSIF_Disable:Invalid module pointer", 0);
break;
}
}
/* Disables watchdog clock and resets watchdog. */
void XMC_WDT_Disable(void)
{
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_WDT);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_WDT);
#endif
#if UC_FAMILY == XMC4
XMC_SCU_CLOCK_DisableClock(XMC_SCU_CLOCK_WDT);
#endif
}
/* Disable the clock and Reset the ERU module. */
void XMC_ERU_Disable(XMC_ERU_t *const eru)
{
#if defined(XMC_ERU1)
if (eru == XMC_ERU1)
{
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ERU1);
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ERU1);
#endif
}
#else
XMC_UNUSED_ARG(eru);
#endif
}
/* Disable GPDMA module */
void XMC_DMA_Disable(XMC_DMA_t *const dma)
{
dma->DMACFGREG = 0x0U;
#if defined(GPDMA1)
if (dma == XMC_DMA0)
{
#endif
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_GPDMA0);
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_GPDMA0);
#endif
#if defined(GPDMA1)
}
else
{
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_GPDMA1);
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_GPDMA1);
#endif
}
#endif
}
/* Initializes HRPWM global registers */
XMC_HRPWM_STATUS_t XMC_HRPWM_Init(XMC_HRPWM_t *const hrpwm)
{
uint32_t *csg_memory;
uint32_t ccu_clock;
uint32_t clkc;
XMC_HRPWM_STATUS_t status;
XMC_ASSERT("XMC_HRPWM_Init:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm));
status = XMC_HRPWM_STATUS_ERROR;
/* Apply reset to HRPWM module */
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_HRPWM0);
/* Release reset for HRPWM module */
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_HRPWM0);
/* Ungate clock */
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_HRPWM0);
hrpwm->GLBANA = (uint32_t)0x00004A4E; /* Initialization sequence */
hrpwm->HRBSC |= (uint32_t)HRPWM0_HRBSC_HRBE_Msk; /* Enable Bias Generator of HRPWM */
/* Update CSG0 memory data */
csg_memory = (uint32_t *)XMC_HRPWM_CSG0_MEMORY_ADDRESS;
*csg_memory = g_hrpwm_char_data[0];
/* write csg memory bits[14:11] with 0b1100 */
*csg_memory &= (uint32_t)(0xFFFF87FF);
*csg_memory |= (uint32_t)(0x00006000);
/* Update CSG1 trimming data */
csg_memory = (uint32_t *)XMC_HRPWM_CSG1_MEMORY_ADDRESS;
*csg_memory = g_hrpwm_char_data[1];
/* write csg memory bits[14:11] with 0b1100 */
*csg_memory &= (uint32_t)(0xFFFF87FF);
*csg_memory |= (uint32_t)(0x00006000);
/* Update CSG2 trimming data */
csg_memory = (uint32_t *)XMC_HRPWM_CSG2_MEMORY_ADDRESS;
*csg_memory = g_hrpwm_char_data[2];
/* write csg memory bits[14:11] with 0b1100 */
*csg_memory &= (uint32_t)(0xFFFF87FF);
*csg_memory |= (uint32_t)(0x00006000);
/* Set CSG units to high speed mode */
hrpwm->CSGCFG = (uint32_t)(0x0000003F);
/* Read CCU clock frequency */
ccu_clock = XMC_SCU_CLOCK_GetCcuClockFrequency();
if ((ccu_clock > XMC_HRPWM_70MHZ_FREQUENCY) && (ccu_clock <= XMC_HRPWM_100MHZ_FREQUENCY))
{
clkc = 3U; /* Clock frequency range 70MHz+ - 100MHz is considered as 80MHz HRC operation */
}
else if ((ccu_clock > XMC_HRPWM_100MHZ_FREQUENCY) && (ccu_clock <= XMC_HRPWM_150MHZ_FREQUENCY))
{
clkc = 2U; /* Clock frequency range 100MHz+ - 150MHz is considered as 120MHz HRC operation */
}
else if ((ccu_clock > XMC_HRPWM_150MHZ_FREQUENCY) && (ccu_clock <= XMC_HRPWM_200MHZ_FREQUENCY))
{
clkc = 1U; /* Clock frequency range 150MHz+ - 200MHz is considered as 180MHz HRC operation */
}
else
{
clkc = 0U; /* Invalid frequency for HRC operation: Clock frequency <= 60MHz & Clock frequency > 200MHz */
}
if (clkc != 0U) /* Enter the loop only if the clock frequency is valid */
{
/* Program HRC clock configuration with clock frequency information */
hrpwm->HRCCFG |= (clkc << HRPWM0_HRCCFG_CLKC_Pos);
hrpwm->HRCCFG |= (uint32_t)HRPWM0_HRCCFG_HRCPM_Msk; /* Release HR generation from power down mode */
XMC_HRPWM_lDelay(); /* As per Initialization sequence */
/* Enable global high resolution generation / Force charge pump down */
hrpwm->GLBANA |= (uint32_t)HRPWM0_GLBANA_GHREN_Msk;
XMC_HRPWM_lDelay();
/* Check High resolution ready bit field */
if ((hrpwm->HRGHRS & HRPWM0_HRGHRS_HRGR_Msk) == 1U)
{
/* High resolution logic unit is ready */
status = XMC_HRPWM_STATUS_OK;
}
}
else
{
status = XMC_HRPWM_STATUS_ERROR; /* Clock frequency is invalid */
}
return (status);
}
