bool _CPU_SMP_Start_processor(uint32_t cpu_index) { bool started; if (cpu_index == 1) { alt_write_word( ALT_SYSMGR_ROMCODE_ADDR + ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST, ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET((uint32_t) _start) ); alt_clrbits_word( ALT_RSTMGR_MPUMODRST_ADDR, ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK ); /* * Wait for secondary processor to complete its basic initialization so * that we can enable the unified L2 cache. */ started = _Per_CPU_State_wait_for_non_initial_state(cpu_index, 0); } else { started = false; } return started; }
bool _CPU_SMP_Start_processor(uint32_t cpu_index) { /* * Wait for secondary processor to complete its basic initialization so that * we can enable the unified L2 cache. */ return _Per_CPU_State_wait_for_non_initial_state(cpu_index, 0); }
bool _CPU_SMP_Start_processor( uint32_t cpu_index ) { bool started; uint32_t cpu_index_self = _SMP_Get_current_processor(); if (cpu_index != cpu_index_self) { BCM2835_REG(BCM2836_MAILBOX_3_WRITE_SET_BASE + 0x10 * cpu_index) = (uint32_t)_start; /* * Wait for secondary processor to complete its basic initialization so * that we can enable the unified L2 cache. */ started = _Per_CPU_State_wait_for_non_initial_state(cpu_index, 0); } else { started = false; } return started; }